This cache-as-RAM (CAR) code is common to several Intel chips. Create a new
intel_common directory and move it in there.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

These two identifiers can be useful for drivers which need to adjust their
behaviour depending on the CPU family or stepping (revision).
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

At present on x86 machines with use cache-as-RAM, the memory goes away just
before board_init_r() is called. This means that serial drivers are
no-longer unavailable, until initr_dm() it called, etc.

Any attempt to use printf() within this period will cause a hang.

To fix this, mark the serial devices as 'unavailable' when it is no-longer
available. Bring it back when serial_initialize() is called. This means that
the debug UART will be used instead for this period.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Add one more step into the init sequence. This fixes the keyboard on samus,
which otherwise does not work.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>

If the device cannot be probed, syscon_get_by_driver_data() will still
return a useful value in its devp parameter. Ensure that it returns NULL
instead.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Commit 1057e6cf broke use of the timer with driver model. If the timer is used
before relocation, then it becomes broken after relocation. This prevents
some x86 boards from booting. Fix it.

Fixes: 1057e6cf (timer: Set up the real timer after driver model is available)
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Add two microcode files for broadwell.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NBin Meng <bmeng.cn@gmail.com>

The Intel SIPI (start-up inter-processor interrupt) vector is the entry
point for each secondary CPU (also called an AP - applications processor).
The assembler and C code are linked, so add comments to indicate this.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

The timeout step is always 50us. By updating apic_wait_timeout() to print
the debug messages we can simplify the code. Also tidy up a few messages and
comments while we are here.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Two power-on-self-test values are the same. Fix this.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

It is useful to automate the process of converting code from coreboot a
little. Add a sed script which performs some common transformations.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NBin Meng <bmeng.cn@gmail.com>

The Intel GPIO driver can set up the GPIO pin mapping when the first GPIO
is probed. However, it assumes that the first GPIO to be probed is in the
first GPIO bank. If this is not the case then the init will write to the
wrong registers.

Fix this. Also add a note that this code is deprecated. We should move to
using device tree instead.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

At present the board ID GPIOs are hard-coded. Move them to the device tree
so that we can use general SDRAM init code.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

The SDRAM SPD (Serial Presence Detect) information should be contained
with the SDRAM controller. This makes it easier for the controller to access
it and removes the need for a separate compatible string.

As a first step, move the information.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

In order to use GPIO phandles we need to add some GPIO properties as
specified by the GPIO bindings. Add these for link.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Many of the model-specific indexes are common to several Intel CPUs. Add
some more common ones, and remove them from the ivybridge-specific header
file.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

This does not need to be modified at run-time, so make it const.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Output the pointer returned by each call to malloc(). This can be useful
when debugging memory problems.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Two comments are missing a parameter and there is an extra blank line. Also
two of the region access macros are misnamed. Correct these problems.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

It is common to read a config register value, clear and set some bits, then
write back the updated value. Add functions to do this in one step, for
convenience.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Some functions do not change the struct gpio_desc parameter. Update these to
use const so this is clear.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

We can use GPIOs as binary digits for reading 'strapping' values. Each GPIO
is assigned a single bit and can be set high or low on the circuit board. We
already have a legacy function for reading these values. Add one that
supports driver model.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Some CPUs use microcode and each core can have a different version of
microcode loaded. Also some CPUs support the concept of an integer ID used
for identification purposes. Add support for these in the CPU uclass.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

At present simple-panel requires regulator support and will not build
without it. But some panels do not have a power supply, or at least not one
that can be controlled. Update the implementation to cope with this.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NAnatolij Gustschin <agust@denx.de>

Boting SeaBIOS is done via U-Boot's bootelf command. Document this.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Now that ACPI is supported on QEMU, enable it.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

SeaBIOS is an open source implementation of a 16-bit x86 BIOS.
It can run in an emulator or natively on x86 hardware with the
use of coreboot. With SeaBIOS's help, we can boot some OSes
that require 16-bit BIOS services like Windows/DOS.

As U-Boot, we have to manually create a table where SeaBIOS gets
system information (eg: E820) from. The table unfortunately has
to follow the coreboot table format as SeaBIOS currently supports
booting as a coreboot payload.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

To prepare generating coreboot table from U-Boot, implement functions
to handle the writing.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

For those secondary bootloaders like SeaBIOS who want to live in
the F segment, which conflicts the configuration table address,
now we allow write_tables() to write the configuration tables in
high area (malloc'ed memory).
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Given all table write routines have the same signature, we can
simplify the codes by using a function table.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Change the parameter and return value of write_acpi_tables() to u32
to conform with other table write routines.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Define ROM_TABLE_ALIGN instead of using 1024 directly.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add a new variable rom_table_start and pass it to ROM table write
routines. This reads better than previous single rom_table_end.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Clean up this file a little bit:
- Remove inclusion of <linux/compiler.h>
- Use tab in the macro definition
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

coreboot_tables.h should not include sysinfo related stuff.
Move those to asm/arch-coreboot/sysinfo.h.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Move asm/arch-coreboot/tables.h to asm/coreboot_tables.h so that
coreboot table definitions can be used by other x86 builds.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Starting with 96e5b03c we use a linker list for partition table
information.  However since we use this in SPL we need to make sure that
the SPL linker scripts include these as well.  While doing this, it's
best to simply include all linker lists to future proof ourselves.

Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reported-by: NNishanth Menon <nm@ti.com>
Tested-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTom Rini <trini@konsulko.com>

When we switch to including all linker lists in SPL it is important to
not include commands as that may lead to link errors due to other things
we have already discarded.  In this case as we don't have other common
code nor other Synology borads, move the cmd_syno.c file (which claims
to be ds414 specific anyways!) into the ds414 directory and only build
it for non-SPL builds.
Signed-off-by: NTom Rini <trini@konsulko.com>

On OMAP4 platforms that also need to calculate their DDR settings we are
now getting very close to the linker limit size.  Since OMAP44XX is only
seen with LPDDR2, remove some run time tests for LPDDR2 or DDR3 as we
will know that we don't have it for OMAP44XX.

Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: NTom Rini <trini@konsulko.com>

When we switch to including all linker lists in SPL it is important
to not include commands as that may lead to link errors due to other
things we have already discarded.  In this case change things so that we
only build the right objects for SPL or non-SPL

Cc: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Signed-off-by: NTom Rini <trini@konsulko.com>