Enable USB IP support for both EHCI and XHCI for
ls1021atwr platform
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>

Add base register address information for USB
XHCI controller on LS1021A
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>

Add xhci driver support for all FSL socs
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>

Remove all redundant dwc3 driver function calls that
are defined by dwc3 driver
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>

Remove all redundant dwc3 driver function calls that
are defined by dwc3 driver
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>

Remove all redundant dwc3 driver function calls that
are defined by dwc3 driver
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>

Add support for DWC3 XHCI controller driver
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>

When final MMU table is setup in DDR, TCR attributes must match
those of the memroy for cacheability and shareability.
Signed-off-by: NZhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit
position [13:12] of TCR_ELx register.
Signed-off-by: NZhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

Freescale DSPI driver has been converted to Driver Model.
The new driver depends on OF_CONTROL, DM, DM_SPI.
This patch enable FSL_DSPI and its dependence configure options.
Signed-off-by: NHaikun Wang <haikun.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Enable DSPI flash related configurations for LS2085ARDB.
Signed-off-by: NHaikun Wang <haikun.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Enable DSPI flash related configurations.
Signed-off-by: NHaikun Wang <haikun.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

DSPI has pin muxing with SDHC and other IPs, this patch check the
value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check
the "hwconfig" variable. If those pins are configured to DSPI and
"hwconfig" enable DSPI, set the BRDCFG5 of QIXIS CPLD to configure
the routing to on-board SPI memory. Otherwise will configure to SDHC.
DSPI is enabled in "hwconfig" by appending "dspi", eg.
setenv hwconfig "$hwconfig;dspi"
Signed-off-by: NHaikun Wang <Haikun.Wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

DSPI has pin muxing with SDHC and other IPs, this patch check the
value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check
the "hwconfig" variable. If those pins are configured to DSPI and
"hwconfig" enable DSPI, set the BRDCFG5 of QIXIS FPGA to configure
the routing to on-board SPI memory. Otherwise will configure to SDHC.
DSPI is enabled in "hwconfig" by appending "dspi", eg.
setenv hwconfig "$hwconfig;dspi"
Signed-off-by: NHaikun Wang <haikun.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Signed-off-by: NHaikun Wang <haikun.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Add dts source files for LS2085AQDS and LS2085ARDB boards.
Signed-off-by: NHaikun Wang <haikun.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Add DSPI controller dts node in fsl-ls2085a.dtsi
Signed-off-by: NHaikun Wang <haikun.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Bring in required device tree files for ls2085a from Linux. These are
initially unchanged and have a number of pieces not needed by U-Boot.
Signed-off-by: NHaikun Wang <Haikun.Wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

As SCFG_ENDIANCR register is added to choose little-endian or big-endian
for audio IPs on Rev2.0 silion, little-endian mode is selected.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform.

Tested on LS1021AQDS, LS1021ATWR.
Test CPU hotplug times: 60K
Test kernel boot times: 1.2K
Signed-off-by: NWang Dongsheng <dongsheng.wang@freescale.com>
Acked-by: NAlison Wang <alison.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted
completely into a reusable armv7 generic timer. LS1021A will use it
as well.
Signed-off-by: NWang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

As the function 'sprintf' does not check buffer boundaries but outputs
to the buffer 'enet' of fixed size (16), this patch removes the function
'sprintf', and uses 'strcpy' instead. It will assign the character
arrays 'enet' and 'phy' the corresponding character strings.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Linux itb image size has been increased from 30MB.

So updating kernel_size to 40MB in env variable.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Export functions required by Aquntia PHY firmware load application.
functions are memset, strcpy, mdelay, mdio_get_current_dev,
phy_find_by_mask, mdio_phydev_for_ethname and miiphy_set_current_dev
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Change infinite loop mechanism to timer based polling for QBMAN release in
ldpaa_eth_rx.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Polling of TX conf frames is not a mandatory option.
Packets can be transferred via WRIOP without TX conf frame.

Configure ldpaa_eth driver to use TX path without confirmation frame
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Volatile command does not return frame immidiately, need to wait till a frame
is available in DQRR. Ideally it should be a blocking call.

Add timeout handling for DQRR frame instead of retry counter.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Do not immediately return if the enqueue function returns -EBUSY; re-try
mulitple times.

if timeout occures, release the buffer.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This patch adds the infrastructure to update device
tree nodes to convey SMMU stream IDs in the device
tree.  Fixups are implemented for PCI controllers
initially.
Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

delete any existing ICID pools in the DPC and create
a new one based on the stream ID partitioning for
the SoC
Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Stream IDs on ls2085a devices are not hardwired and are
programmed by sw.  There are a limited number of stream IDs
available, and the partitioning of them is scenario dependent.
This header defines the partitioning between legacy, PCI,
and DPAA2 devices.
Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Management complex major version should match to the firmware present in flash.

Return error during mismatch of major version.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Update qbman driver
 - As per latest available qbman driver
 - Use of atomic APIs
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
CC: Geoff Thorpe <Geoff.Thorpe@freescale.com>
CC: Haiying Wang <Haiying.Wang@freescale.com>
CC: Roy Pledge <Roy.Pledge@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Update flibs changes to mc-0.6.0.1 for dpmang, dprc, dpni and dpio objects
Also rename qbman_portal_ce/ci_paddr to qbman_portal_ce/ci_offset in
dpio_attr. These are now offsets from the SoC QBMan portals base.
Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Load AIOP image from NOR flash into DDR so that the MC firmware
the MC fw can start it at boot time
Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Flush buffer before releasing to BMan after TX_conf to ensure, the core does
not have any cachelines that the WRIOP will DMA to.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Make it easier for the user to notice when the MC firmware
had problems booting.
Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Signed-off-by: Stuart Yoder <stuart.yoder at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

The agreed split of the top of memory is 256M for debug server and 256M
 for MC. This patch implements the split.

 In addition, the MC mem must be 512MB aligned, so the amount of memory
 to hide must be 512MB to achieve that alignment.
Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>