- 21 10月, 2013 1 次提交
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由 Vivek Gautam 提交于
Adding required compatible string for xHCI host controller as well as USB 3.0 PHY to enable dt support for usb 3.0 on exynos5. Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Dan Murphy <dmurphy@ti.com> Cc: Marek Vasut <marex@denx.de>
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- 24 7月, 2013 1 次提交
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: NTom Rini <trini@ti.com>
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- 23 7月, 2013 1 次提交
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由 naveen krishna chatradhi 提交于
Adds a new COMPAT string exynos5-hsi2c for high speed i2c controller available on exynos5 SoCs from Samsung. Signed-off-by: NNaveen Krishna Chatradhi <ch.naveen@samsung.com>
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- 12 7月, 2013 1 次提交
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由 Jim Lin 提交于
Tegra30 and Tegra114 are compatible except PLL parameters. Tested on Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well. Signed-off-by: NJim Lin <jilin@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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- 26 6月, 2013 2 次提交
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由 Hung-ying Tyan 提交于
This patch adds the driver for keyboard that's controlled by ChromeOS EC. Signed-off-by: NRandall Spangler <rspangler@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NVincent Palatin <vpalatin@chromium.org> Signed-off-by: NHung-ying Tyan <tyanh@chromium.org> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Hung-ying Tyan 提交于
This patch adds the cros_ec driver that implements the protocol for communicating with Google's ChromeOS embedded controller. Signed-off-by: NBernie Thompson <bhthompson@chromium.org> Signed-off-by: NBill Richardson <wfrichar@chromium.org> Signed-off-by: NChe-Liang Chiou <clchiou@chromium.org> Signed-off-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NGabe Black <gabeblack@chromium.org> Signed-off-by: NHung-ying Tyan <tyanh@chromium.org> Signed-off-by: NLouis Yung-Chieh Lo <yjlou@chromium.org> Signed-off-by: NRandall Spangler <rspangler@chromium.org> Signed-off-by: NSean Paul <seanpaul@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NVincent Palatin <vpalatin@chromium.org> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org>
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- 24 6月, 2013 1 次提交
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由 Rajeshwari Shinde 提交于
Add required compatible information for s5p serial driver Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: NRajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 13 6月, 2013 1 次提交
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由 Amar 提交于
Add required compatible information for DWMMC driver. Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com> Signed-off-by: NAmar <amarendra.xt@samsung.com> Acked-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 03 6月, 2013 1 次提交
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由 Vincent Palatin 提交于
Add support for Infineon's new SLB 9645 TT 1.2 I2C TPMs, which supports clockstretching, combined reads and a bus speed of up to 400khz. The device also has a new device id. This is based on the kernel patch provided by Infineon : https://gerrit.chromium.org/gerrit/42332Signed-off-by: NVincent Palatin <vpalatin@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NLuigi Semenzato <semenzato@chromium.org> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NVincent Palatin <vpalatin@chromium.org> Tested-by: NTom Wai-Hong Tam <waihong@chromium.org> Tested-by: NVincent Palatin <vpalatin@chromium.org>
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- 13 4月, 2013 1 次提交
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由 Rong Chang 提交于
Add a driver for the I2C TPM from Infineon. Signed-off-by: NChe-Liang Chiou <clchiou@chromium.org> Signed-off-by: NRong Chang <rongchang@chromium.org> Signed-off-by: NTom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 27 3月, 2013 2 次提交
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由 Ajay Kumar 提交于
Add required compatible information for FIMD. Signed-off-by: NAjay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Ajay Kumar 提交于
Add required compatible information for FIMD. Signed-off-by: NAjay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 26 3月, 2013 1 次提交
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由 Allen Martin 提交于
Add "nvidia,tegra114-spi" to represent t114 SPI controller hardware. Signed-off-by: NAllen Martin <amartin@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com>
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- 19 3月, 2013 2 次提交
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由 Simon Glass 提交于
Enable device tree control of SPI flash, and use this to implement memory-mapped SPI flash, which is supported on Intel chips. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
It is common to have a "reg = <address size>" property in the FDT. Add a function to handle this, similar to the existing fdtdec_get_addr(); Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 15 3月, 2013 3 次提交
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由 Tom Warren 提交于
Tegra30 SD/MMC controller differs enough from Tegra20 that it needs its own entry in the compat_names/compat_id tables and in the Tegra MMC driver. Signed-off-by: NTom Warren <twarren@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com>
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由 Tom Warren 提交于
tegra_mmc_init() now parses the DT info for bus width, WP/CD GPIOs, etc. Tested on Seaboard, fully functional. Tamonten boards (medcom-wide, plutux, and tec) use a different/new dtsi file w/common settings. Signed-off-by: NTom Warren <twarren@nvidia.com> Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de> Reviewed-by: NStephen Warren <swarren@nvidia.com>
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由 Tom Warren 提交于
T114 has a slightly different I2C clock, with a new (extra) divisor in standard/fast mode and HS mode. Tested on my Dalmore, and the I2C clock is 100KHz +/- 3Hz on my Saleae Logic analyzer. Added a new entry in compat_names for T114 I2C since it differs from the previous Tegra SoCs. A flag is set when T114 I2C HW is found so new features like the extra clock divisor can be used. Signed-off-by: NTom Warren <twarren@nvidia.com> Acked-by: NLaxman Dewangan <ldewangan@nvidia.com>
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- 12 3月, 2013 1 次提交
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由 Akshay Saraswat 提交于
Fdt entry for Exynos TMU driver specific pre-defined values used for calibration of current temperature and defining threshold values. Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 08 3月, 2013 1 次提交
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由 Rajeshwari Shinde 提交于
Add required compatible information for MAX98095 codec Signed-off-by: NRajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 12 2月, 2013 2 次提交
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由 Allen Martin 提交于
Add driver for tegra SPI "SLINK" style driver. This controller is similar to the tegra20 SPI "SFLASH" controller. The difference is that the SLINK controller is a genernal purpose SPI controller and the SFLASH controller is special purpose and can only talk to FLASH devices. In addition there are potentially many instances of an SLINK controller on tegra and only a single instance of SFLASH. Tegra20 is currently ths only version of tegra that instantiates an SFLASH controller. This driver supports basic PIO mode of operation and is configurable (CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4 devices per controller may be attached, although typically only a single chip select line is exposed from tegra per controller so in reality this is usually limited to 1. To enable this driver, use CONFIG_TEGRA_SLINK Signed-off-by: NAllen Martin <amartin@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Allen Martin 提交于
Add support for configuring tegra SPI driver from devicetree. Support is keyed off CONFIG_OF_CONTROL. Add entry in seaboard dts file for spi controller to describe seaboard spi. Signed-off-by: NAllen Martin <amartin@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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- 10 1月, 2013 1 次提交
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由 Rajeshwari Shinde 提交于
Add required compatible information for PMIC Signed-off-by: NRajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 08 1月, 2013 4 次提交
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由 Rajeshwari Shinde 提交于
Add required compatible information for USB Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Rajeshwari Shinde 提交于
Add required compatible information for SPI driver. Signed-off-by: NRajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Rajeshwari Shinde 提交于
Add required compatible information for sound driver. Signed-off-by: NRajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Rajeshwari Shinde 提交于
Add required compatible information for I2C driver. Signed-off-by: NRajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Acked-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 26 12月, 2012 1 次提交
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由 Hatim RV 提交于
Add the compatibility string and constant for the ethernet driver so the device tree parsing code can recognize it. Signed-off-by: NHatim Ali <hatim.rv@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 19 11月, 2012 2 次提交
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由 Wei Ni 提交于
Add support for the LCD peripheral at the Tegra2 SOC level. A separate LCD driver will use this functionality to configure the display. Signed-off-by: NMayuresh Kulkarni <mkulkarni@nvidia.com> Mayuresh Kulkarni: - changes to remove bitfields and clean up for submission Signed-off-by: NSimon Glass <sjg@chromium.org> Simon Glass: - simplify code, move clock control into here, clean-up Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Simon Glass 提交于
The pulse width/frequency modulation peripheral supports generating a repeating pulse. It is useful for controlling LCD brightness. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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- 13 11月, 2012 8 次提交
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由 Sean Paul 提交于
Add get and set gpio functions to fdtdec that take into account the polarity field in fdtdec_gpio_state.flags. Signed-off-by: NSean Paul <seanpaul@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Che-Liang Chiou 提交于
It decodes a 64-bit value from a property that is at least 8 bytes long. Signed-off-by: NChe-Liang Chiou <clchiou@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Gabe Black 提交于
Signed-off-by: NVincent Palatin <vpalatin@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Commit-Ready: Gabe Black <gabeblack@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Gerald Van Baren 提交于
The name of this function is not consistent, so fix it, and export the function for external use. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Abhilash Kesavan 提交于
Samsung's SDHCI bindings require multiple gpios to be parsed and configured at a time. Export the already available fdtdec_decode_gpios for this purpose. Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com> Commit-Ready: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
A memory region has a start and a size and is often specified in a node by a 'reg' property. Add a function to decode this information from the fdt. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Add a function to look up a configuration string such as board name and returns its value. We look in the "/config" node for this. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Abhilash Kesavan 提交于
Add a function to look up a configuration item such as machine id and return its value. Note: The code has been taken as is from the Chromium u-boot development tree and needs Simon Glass' sign-off. Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 22 9月, 2012 1 次提交
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由 Simon Glass 提交于
This makes it easier to include this header from other headers. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NMike Frysinger <vapier@gentoo.org>
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- 08 9月, 2012 1 次提交
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由 Jim Lin 提交于
A device tree is used to configure the NAND, including memory timings and block/pages sizes. If this node is not present or is disabled, then NAND will not be initialized. Signed-off-by: NJim Lin <jilin@nvidia.com> Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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