- 17 10月, 2013 1 次提交
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由 Po Liu 提交于
This patch is for board config file not to add CONFIG_SECURE_BOOT condition for include the asm/fsl_secure_boot.h. Signed-off-by: NPo Liu <Po.Liu@freescale.com>
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- 24 7月, 2013 1 次提交
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: NTom Rini <trini@ti.com>
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- 25 5月, 2013 1 次提交
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由 Ruchika Gupta 提交于
Boot ROM code creates TLB entries for 3.5G space before entering the u-boot. Earlier we were deleting these entries after early initialization of CPU. In recent past, code has been added to invalidate all these entries before relocation of u-boot code. So this code to delete TLB entries after CPU initialization is no longer required. Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> Acked-by: NMatthew McClintock <msm@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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- 03 10月, 2011 1 次提交
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由 Ruchika Gupta 提交于
Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: NKuldip Giroh <kuldip.giroh@freescale.com> Acked-by: NWood Scott-B07421 <B07421@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 20 5月, 2011 1 次提交
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
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- 28 4月, 2011 1 次提交
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由 Kumar Gala 提交于
The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NShaohui Xie <b21989@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 20 1月, 2011 1 次提交
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由 Kumar Gala 提交于
Add new headers that capture common defines for a given SoC/processor rather than duplicating that information in board config.h and random other places. Eventually this should be handled by Kconfig & defconfigs Signed-off-by: NKumar Gala <galak@kernel.crashing.org> Acked-by: NWolfgang Denk <wd@denx.de>
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- 14 1月, 2011 6 次提交
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由 Kumar Gala 提交于
Simultaneous FCM and GPCM or UPM operation may erroneously trigger bus monitor timeout. Set timeout to maximum to avoid. Based on a patch from Lan Chunhe <b25806@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Roy Zang 提交于
False multi-bit ECC errors will be reported by the eSDHC buffer which can trigger a reset request. We disable all ECC error checking on SDHC. Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Roy Zang 提交于
The default value of the SRS, VS18 and VS30 and ADMAS fields in the host controller capabilities register (HOSTCAPBLT) are incorrect. The default of these bits should be zero instead of one. Clear these bits out when we read HOSTCAPBLT. Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Jerry Huang 提交于
Do not issue a manual asynchronous CMD12. Instead, use a (software) synchronous CMD12 or AUTOCMD12 to abort data transfer. Signed-off-by: NJerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 12 11月, 2010 2 次提交
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由 Kumar Gala 提交于
We appear to have different refclk's on the different corenet DS boards so move the define out of the common header. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
CONFIG_SYS_TEXT_BASE setting is common across the 'corenet_ds' board family so move it out of P4080DS.h and into corenet_ds.h Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 19 10月, 2010 1 次提交
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由 Wolfgang Denk 提交于
Clean up Makefile, and drop a lot of the config.mk files on the way. We now also automatically pick all boards that are listed in boards.cfg (and with all configurations), so we can drop the redundant entries from MAKEALL to avoid building these twice. Signed-off-by: NWolfgang Denk <wd@denx.de>
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- 02 8月, 2010 1 次提交
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由 Kumar Gala 提交于
Add support for the P4080DS board, with the following features: * 36-bit only * Boots from NOR flash * FMAN drivers NOT supported * SPD DDR initialization Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com> Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org> Signed-off-by: NAshish Kalra <Ashish.Kalra@freescale.com> Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com> Signed-off-by: NDave Liu <daveliu@freescale.com> Signed-off-by: NLan Chunhe-B25806 <b25806@freescale.com> Signed-off-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com> Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 13 4月, 2010 1 次提交
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由 Peter Tyser 提交于
This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
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- 13 2月, 2010 1 次提交
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由 Jens Scharsig 提交于
* prepare joining at91 and at91rm9200 * add modified copy of soc files to cpu/arm920t/at91 to make possible to compile at91rm9200 boards in at91 tree instead of at91rm9200 * add header files with c structure defs for AT91 MC, ST and TC * the new cpu files are using at91 c structure soc access * please read README.soc-at91 for details Signed-off-by: NJens Scharsig <js_at_ng@scharsoft.de>
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- 31 10月, 2008 1 次提交
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由 Ricardo Ribalda Delgado 提交于
Xilinx ppc440 and ppc405 have many similarities. This patch merge the config files of both infrastuctures Signed-off-by: NRicardo Ribalda Delgado <ricardo.ribalda@uam.es> Signed-off-by: NStefan Roese <sr@denx.de>
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- 24 10月, 2008 1 次提交
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由 Ricardo Ribalda Delgado 提交于
As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx ppc440 boards, this patch presents a common architecture for all the xilinx ppc405 boards. Any custom xilinx ppc405 board can be added very easily with no code duplicity. This patch also adds a simple generic board, that can be used on almost any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h This patch is prepared to work with the latest version of EDK (10.1) Signed-off-by: NRicardo Ribalda Delgado <ricardo.ribalda@uam.es> Signed-off-by: NStefan Roese <sr@denx.de>
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