Fix the DDR2 configuration to make SPL work.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>

Add the "u-boot,dm-pre-reloc" property to determine which nodes
which are needed by SPL and by the board_init_f stage.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>

Add clock property for uart1 node.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>

One some keystone2 platforms like K2G ICE, there is an option
to switch between 24MHz or 25MHz as sysclk. But the existing
driver assumes it is always 24MHz. Add support for getting
all reference clocks dynamically by reading boot pins.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

K2G supports various sysclk frequencies which can be
determined using sysboot pins. PLLs should be configured
based on this sysclock frequency. Add PLL configurations
for all supported sysclk frequencies.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

ARM errata 852421 and 852423 applies to r1p0, r1p1 and r1p2
revisions of Cortex-A17 processors. These workarounds
exist in Linux kernel and I thought it would be better
to add them in to U-Boot.
Signed-off-by: NNisal Menuka <nisalmenuka23@gmail.com>

Remove unnecessary apb and ahb nodes and just override necessary
nodes/values.
Signed-off-by: NMaxim Sloyko <maxims@google.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Refactor SCU header to use consistent Mask & Shift values.
Now, consistently, to read value from SCU register, mask needs
to be applied before shift.
Signed-off-by: NMaxim Sloyko <maxims@google.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add support for clocks needed by MACs to ast2500 clock driver.
The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and
PCLK_MAC2 for MAC1 and MAC2 respectively.

The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed
SDK. It is not entirely clear from the datasheet how this clock is used
by MACs, so not clear if the rate would ever need to be different. So,
for now, hardcoding it is probably safer.

The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through
hardware strapping.

So, the network driver would only need to enable these clocks, no need
to configure the rate.
Signed-off-by: NMaxim Sloyko <maxims@google.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add P-Bus Clock support to ast2500 clock driver.
This is the clock used by I2C devices.
Signed-off-by: NMaxim Sloyko <maxims@google.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This driver uses Generic Pinctrl framework and is compatible with
the Linux driver for ast2500: it uses the same device tree
configuration.

Not all pins are supported by the driver at the moment, so it actually
compatible with ast2400. In general, however, there are differences that
in the future would be easier to maintain separately.
Signed-off-by: NMaxim Sloyko <maxims@google.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This change switches all existing users of ast2500 Watchdog to Driver
Model based Watchdog driver.

To perform system reset Sysreset Driver uses first Watchdog device found
via uclass_first_device call. Since the system is going to be reset
anyway it does not make much difference which watchdog is used.

Instead of using Watchdog to reset itself, SDRAM driver now uses Reset
driver to do that.

These were the only users of the old Watchdog API, so that API is
removed.

This all is done in one change to avoid having to maintain dual API for
watchdog in between.
Signed-off-by: NMaxim Sloyko <maxims@google.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add Reset Driver configuration to ast2500 SoC Device Tree and bindings
for various reset signals
Signed-off-by: NMaxim Sloyko <maxims@google.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to
perform resets and thus depends on it. The actual Watchdog device used
needs to be configured in Device Tree using "aspeed,wdt" property, which
must be WDT phandle, for example:

rst: reset-controller {
    compatible = "aspeed,ast2500-reset";
    aspeed,wdt = <&wdt1>;
}
Signed-off-by: NMaxim Sloyko <maxims@google.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Make functions for locking and unlocking SCU part of SCU API.
Many drivers need to modify settings in SCU and thus need to unlock it
first. This change makes it possible.
Signed-off-by: NMaxim Sloyko <maxims@google.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This driver supports ast2500 and ast2400 SoCs.
Only ast2500 supports reset_mask and thus the option of resettting
individual peripherals using WDT.
Signed-off-by: NMaxim Sloyko <maxims@google.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Pull in the Device Tree for ast2500 from the mainline Linux kernel.
The file is copied from
https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsiSigned-off-by: NMaxim Sloyko <maxims@google.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This patch is required for correct SPL device tree creation by fdtgrep
as fdtgrep looks for u-boot,dm-pre-reloc property of the node to include
it in the spl device tree.

Not adding it in these subnodes ignores the pin muxing of peripherals
which is almost always in the subnodes.
Signed-off-by: NVikas Manocha <vikas.manocha@st.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

The IGEP SMARC AM335x is an industrial processor module with
following highlights:

  o AM3352 TI processor (Up to AM3359)
  o Cortex-A8 ARM CPU
  o SMARC form factor module
  o Up to 512 MB DDR3 SDRAM / 512 MB FLASH
  o WiFi a/b/g/n and Bluetooth v4.0 on-board
  o Ethernet 10/100/1000 Mbps and 10/100 Mbps controller on-board
  o JTAG debug connector available
  o Designed for industrial range purposes
Signed-off-by: NPau Pajuelo <ppajuelo@iseebcn.com>
Signed-off-by: NLadislav Michl <ladis@linux-mips.org>
Tested-by: NPau Pajuelo <ppajuel@gmail.com>

Rename igep0033 to igep003x as IGEP SMARC AM335x module (igep0034)
can use the same source files.
Signed-off-by: NLadislav Michl <ladis@linux-mips.org>
Tested-by: NPau Pajuelo <ppajuel@gmail.com>

am33xx does not support OneNAND, but we need this define anyway
to let UBI SPL code compile.
Signed-off-by: NLadislav Michl <ladis@linux-mips.org>
Tested-by: NPau Pajuelo <ppajuel@gmail.com>

Signed-off-by: NLadislav Michl <ladis@linux-mips.org>
Tested-by: NPau Pajuelo <ppajuel@gmail.com>

This board support stm32f7 family device stm32f769-I with 2MB internal Flash &
512KB RAM.
STM32F769 lines offer the performance of the Cortex-M7 core (with double
precision floating point unit) running up to 216 MHz.

To compile for stm32f769 board, use same defconfig as stm32f746-disco,
the only difference is to pass "DEVICE_TREE=stm32f769-disco".
Signed-off-by: NVikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

Signed-off-by: NVikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

Actually the sdram memory on stm32f746 discovery board is micron part
MT48LC_4M32_B2B5_6A. This patch does the modification required in the
device tree node & driver for the same.

Also we are passing here all the timing parameters in terms of clock
cycles, so no need to convert time(ns or ms) to cycles.
Signed-off-by: NVikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

All discovery boards have one user button & one user LED. Here we are
just reading the button status & switching ON the user LED.
Signed-off-by: NVikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

With this gpio driver supporting DM, there is no need to enable clocks
for different gpios (for pin muxing) in the board specific code.

Need to increase the allocatable area required before relocation from 0x400 to
0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree.
Signed-off-by: NVikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Also created alias for gpios for stm32f7 discovery board. Based on these
aliases, it would be possible to get gpio devices by sequence.
Signed-off-by: NVikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

This patch adds gpio driver supporting driver model for stm32f7 gpio.
Signed-off-by: NVikas Manocha <vikas.manocha@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Cc: Christophe KERELLO <christophe.kerello@st.com>
[trini: Add depends on STM32]
Signed-off-by: NTom Rini <trini@konsulko.com>

Signed-off-by: NVikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

This patch also removes the sdram/fmc clock enable from board specific
code.
Signed-off-by: NVikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

Also added DT binding doc for stm32 fmc(flexible memory controller).
Signed-off-by: NVikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

Signed-off-by: NVikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

At present fdt blob or argument address being passed to kernel is fixed at
compile time using macro CONFIG_SYS_SPL_ARGS_ADDR. FDT blob from
different media like nand, nor flash are copied to the address pointed
by the macro.
The problem is, it makes args/fdt blob compulsory to copy which is not required
in cases like for NOR Flash. This patch removes this limitation.
Signed-off-by: NVikas Manocha <vikas.manocha@st.com>

The symbol CONFIG_DRA7XX is needed for Kconfig conditions.

Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NUri Mashiach <uri.mashiach@compulab.co.il>
Reviewed-by: NTom Rini <trini@konsulko.com>

In dram_init_banksize there seems to be a typo concerning
a plausibility check of the fdt.
Testing sc > 2 twice does not make any sense.

The problem was indicated by cppcheck.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

R40 has a similar SATA controller with the ones on A10/A20, but with a
reset line added (like other peripherals on sun6i+), and two extra VDD
pins added (1.2v and 2.5v).

Add clock configuration of R40 SATA.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.io>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Fix annoying config redefines in SoC/board level Kconfig.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

For the consistent location of SoC-level Kconfig.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

With 3f66149d we no longer have a common call fdt_fixup_ethernet.
This was fine to do on PowerPC as they largely had calls already in
ft_cpu_fixup.  On ARM however we largely relied on this call.  Rather
than introduce a large number of changes to ft_cpu_fixup /
ft_board_fixup we recognize that this is a common enough call that we
should be doing it in a central location.  Do it early enough that we
can do any further updates in ft_cpu_fixup / ft_board_fixup.

Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Thomas Chou <thomas@wytron.com.tw> (maintainer:NIOS)
Cc: York Sun <york.sun@nxp.com> (maintainer:POWERPC MPC85XX)
Cc: Stefan Roese <sr@denx.de> (maintainer:POWERPC PPC4XX)
Cc: Simon Glass <sjg@chromium.org>
Cc: Joakim Tjernlund <Joakim.Tjernlund@infinera.com>
Fixes: 3f66149d ("Remove extra fdt_fixup_ethernet() call")
Signed-off-by: NTom Rini <trini@konsulko.com>
Acked-by: NStefan Roese <sr@denx.de>
Acked-by: NYork Sun <york.sun@nxp.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>