Enable CONFIG_OF_BOAD to support delivery dtb to u-boot
at run time instead of embedded.

There are two methods to delivery dtb.
 1 Pass from loader:
   When u-boot boot from RAM, gdb or loader can pass dtb
   via a2 to u-boot dynamically. Of course gdb or loader
   shall be in charge of dtb delivery.

 2 Configure CONFIG_SYS_FDT_BASE:
   It can be configured as RAM or ROM base statically,
   no mater u-boot boot from RAM or ROM.
   If it was configured as ROM base, dtb can be burned
   into ROM(spi flash) by spi driver.

Meanwhile remove CONFIG_SKIP_LOWLEVEL_INIT which is
useless in nx25-ae250 configuration.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>

Remove CONFIG_MMC_NDS32 from the three config
(adp-ae3xx_defconfig, adp-ag101p_defconfig, nx25-ae250_defconfig).
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>

nsd32_mmc was created to support ftsdc010 dm.
It is not necessary to separate both, so merge it
to ftsdc010.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>

Convert CONFIG_FTSDC010_SDIO to Kconfig.
So CONFIG_FTSDC010_SDIO can also be
removed from config_whitelist.txt.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>

CONFIG_FTSDC010_NUMBER was not used anymore,
can be removed now.

So CONFIG_FTSDC010_NUMBER
can also be removed from config_whitelist.txt.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>

After drop non-dm code of ftsdc010, the sd register
base definition can be droppped now.

So CONFIG_FTSDC010_BASE and CONFIG_FTSDC010_BASE_LIST both
can be removed from config_whitelist.txt
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>

Remove board_mmc_init() in adp-ag101p, adp-ae3xx
and nx25-ae250 boards.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>

Only three defconfig(adp-ag101p_defconfig,
adp-ae3xx_defconfig, nx25-ae250_defconfig)
set CONFIG_FTSDC010=y. And they all also
enable CONFIG_DM_MMC. So the non-dm code
of ftsdc010 can be dropped now.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>

Enable High-Speed mode with cap-sd-highspeed in dts
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>

Enable High-Speed mode with cap-sd-highspeed in dts.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>

ftsdc010 dm driver has been disable High-Speed mode
as default to work around Andes AE3XX platform's problem,
because of it does not support High-Speed mode in
commit id 73cd56b2.

But other platforms or SoCs maybe support this function.
So High-Speed mode can be enabled from dts with
cap-mmc-highspeed or cap-sd-highspeed property.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>

Simply record riscv-linux booting steps and messages
from bbl via u-boot on QEMU in README.ae250.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>

Add riscv uimage arch to support riscv-linux booting.
It can Convert riscv-linux to image which can be
booted by bootm command.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>

ATAGS is not supported and will be replaced
by DT in riscv-linux. So can be removed now.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>

riscv-linux should use BBL (Berkeley bootloader) for
loading the Linux kernel.

U-Boot can play as FSBL(first stage bootloader)
to boot BBL and riscv-linux.

In BBL's init_first_hart(), it will pass dtb with a1.
So implement bootm to pass arguments to BBL correctly.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>

It is reported by checkpatch.pl
WARNING: static const char * array
should probably be static const char * const
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>

It is reported by checkpatch.pl
WARNING: Missing a blank line after declarations.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>

It is reported by checkpatch.pl.
CHECK: Alignment should match open parenthesis
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>

It is reported by checkpatch.pl
WARNING: Use of volatile is usually wrong: see
Documentation/process/volatile-considered-harmful.rst
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>

It is CHECK reported by checkpatch.pl
CHECK: Macro argument reuse 'PTE' - possible side-effects?
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>

The Rockchip-specific SDHCI wrapper does not process the 'bus-width'
property in the SDHCI node. Consequently, the bus is always kept in
4bit mode, even if 8bit wide operation is available, supported and
requested in the DTS.

This change adds processing of the 'bus-width' property and sets the
host capability flag for an 8bit wide bus, if set to 8. As the logic
in sdhci.c does not support clearing the 4bit capability, we assume
that 4bit operation is always supported.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

The Rockchip-specific wrappers to the DW-MMC and the SDHCI driver
were not covered as part of what's maintained by the architecture
maintainers.  Add them here.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

For the RK3399-Q7, we have a fast eMMC connected in an 8 bit wide
configuration to the SDHCI controller (sdhci@fe330000).  Enable DMA
within the SDHCI driver to get the best performance out of it.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Signed-off-by: NMark Kettenis <kettenis@openbsd.org>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: NKlaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

The patch set dpll settings for 300MHz to values used by binary
blob[1]. With new values dpll still generate 300MHz clock, but
EMAC work. Probably with new values dpll generate more stable clock.

dpll on rk3188 provide clocks to DDR and EMAC. With current
dpll settings EMAC doesn't work on radxa rock. EMAC sends packets
to network, but it doesn't receive anything. ifconfig shows a lot
of framing errors.

[1] https://github.com/linux-rockchip/u-boot-rockchip/blob/u-boot-rk3288/
    tools/rk_tools/3188_LPDDR2_300MHz_DDR3_300MHz_20130830.bin
Signed-off-by: NAlexander Kochetkov <al.kochet@gmail.com>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Signed-off-by: NPunit Agrawal <punit.agrawal@arm.com>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

The error checking should also catch the case that no range has beeen
defined.
syscon_get_first_range() returns NULL if no range is defined.
cf. rk3399_mipi.c
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Signed-off-by: NPunit Agrawal <punit.agrawal@arm.com>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Pointers are never negative. Use macro IS_ERR() for checking.
cf. rk3288_mipi.c
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Assigning f_rkusb->reboot_flag twice doesn't make sense.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

If we want to check the duration we need to increment the counter.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Clean the iomux definitions at grf_rk3188.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
Signed-off-by: NAlexander Kochetkov <al.kochet@gmail.com>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Clean the iomux definitions at grf_rk3036.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
Signed-off-by: NAlexander Kochetkov <al.kochet@gmail.com>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

This adds support for the (to date unsupported) I2C controllers 1~4
and 6~7 (i.e. now all controllers except I2C5, which is not accessible
on the RK3399-Q7, are supported by pinctrl).
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: NKlaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

The shift values for GPIO2B1 and GPIO2B2 had in fact referred to
GPIO2B0 and GPIO2B1, respectively.  This substitutes the correct
values.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>