- 02 7月, 2015 1 次提交
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由 Jagan Teki 提交于
Since the help text is added in drivers/mtd/spi/Kconfig Signed-off-by: NJagan Teki <jteki@openedev.com>
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- 01 7月, 2015 1 次提交
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由 Jagan Teki 提交于
This patch adds CONFIG_SPI_FLASH_DATAFLASH descrition on README file for more readble for users. Signed-off-by: NJagan Teki <jteki@openedev.com>
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- 30 6月, 2015 1 次提交
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由 Daniel Schwierzeck 提交于
Add MTD layer driver for spi, original patch from: http://git.denx.de/?p=u-boot/u-boot-mips.git;a=commitdiff;h=bb246819cdc90493dd7089eaa51b9e639765cced Changes from Heiko Schocher against this patch: - Remove compile error if not defining CONFIG_SPI_FLASH_MTD: LD drivers/mtd/spi/built-in.o drivers/mtd/spi/sf_probe.o: In function `spi_flash_mtd_unregister': /home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: multiple definition of `spi_flash_mtd_unregister' drivers/mtd/spi/sf_params.o:/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: first defined here drivers/mtd/spi/sf_ops.o: In function `spi_flash_mtd_unregister': /home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: multiple definition of `spi_flash_mtd_unregister' drivers/mtd/spi/sf_params.o:/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: first defined here make[1]: *** [drivers/mtd/spi/built-in.o] Fehler 1 make: *** [drivers/mtd/spi] Fehler 2 - Add a README entry. - Add correct writebufsize, to fit with Linux v3.14 MTD, UBI/UBIFS sync. Note (From Jagan): For testing raw mtd parition erase/read/write operations using cmd_sf, sf_mtd should be required to register the spi flash device to MTD layer but the sf_mtd_info ops were not required until and unless if we use any flash filesystem layer say for example UBI. Due to this the foot-print got increased ~290bytes in non-UBI case here that should be acceptible. Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: NHeiko Schocher <hs@denx.de> Tested-by: NJagannadh Teki <jteki@openedev.com> Reviewed-by: NJagannadh Teki <jteki@openedev.com>
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- 26 6月, 2015 1 次提交
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由 Joe Hershberger 提交于
This sets the default commands Kconfig to match include/config_cmd_default.h commands in the common/Kconfig and removes them from include/configs. Signed-off-by: NJoe Hershberger <joe.hershberger@ni.com> [trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates] Signed-off-by: NTom Rini <trini@konsulko.com>
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- 20 6月, 2015 1 次提交
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由 Chris Packham 提交于
Unlike most configuration options defining this actually disables support for a feature (parallel flash). Eventually the logic behind this should probably be flipped so that '#ifndef CONFIG_SYS_NO_FLASH' becomes '#ifdef CONFIG_HAS_PARALLEL_FLASH' but for now lets document the existing behaviour. Signed-off-by: NChris Packham <judge.packham@gmail.com> Reviewed-by: NStefan Roese <sr@denx.de>
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- 08 6月, 2015 1 次提交
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由 Stefan Roese 提交于
These defines for a 2nd autoboot stop and delay string are nearly unused. Only sc3 defines CONFIG_AUTOBOOT_DELAY_STR2. And a patch to remove this most likely unmaintained board is also posted to the list. By removing these defines the code will become cleaner and moving the remaining compile options to Kconfig will get easier. Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
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- 21 5月, 2015 1 次提交
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由 Joe Hershberger 提交于
Allow the features that use env_attrs to specify regexs for the name Signed-off-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 20 5月, 2015 3 次提交
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由 Joe Hershberger 提交于
We really don't want boards defining fixed MAC addresses in their config so we just remove the option to set it in a fixed way. If you must have a MAC address that was not provisioned, then use the random MAC address functionality. Signed-off-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Joe Hershberger 提交于
Implement the random ethaddr fallback in eth.c so it is in a common place and not reimplemented in each board or driver that wants this behavior. Signed-off-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Hans de Goede 提交于
On my A10 OlinuxIno Lime I noticed a huge (5+ seconds) delay coming from console_init_r. This turns out to be caused by the preconsole buffer flushing to the cfb_console. The Lime only has a 16 bit memory bus and that is already heavy used to scan out the 1920x1080 framebuffer. The problem is that print_pre_console_buffer() was printing the buffer once character at a time and the cfb_console code then ends up doing a cache-flush for touched display lines for each character. This commit fixes this by first building a 0 terminated buffer and then printing it in one puts() call, avoiding unnecessary cache flushes. This changes the time for the flush from 5+ seconds to not noticable. The downside of this approach is that the pre-console buffer needs to fit on the stack, this is not that much to ask since we are talking about plain text here. This commit also adjusts the sunxi CONFIG_PRE_CON_BUF_SZ to actually fit on the stack. Sunxi currently is the only user of the pre-console code so no other boards need to be adjusted. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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- 09 5月, 2015 1 次提交
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由 Fabio Estevam 提交于
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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- 30 4月, 2015 1 次提交
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由 Bin Meng 提交于
CONFIG_VIDEO_VGA is no longer needed thus remove it. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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- 23 4月, 2015 4 次提交
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由 York Sun 提交于
The timer clock is system clock divided by 4, not fixed 12MHz. This is common to the SoC, not board specific. Primary core is fixed when u-boot still runs in board_f. Secondary cores are fixed by reading a variable set by u-boot. Signed-off-by: NYork Sun <yorksun@freescale.com> CC: Mark Rutland <mark.rutland@arm.com>
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由 York Sun 提交于
Add built-in memory test to catch errors after DDR is initialized, before any other transactions. To enable this test, define CONFIG_FSL_DDR_BIST. An environmental variable "ddr_bist" is checked before starting test. It takes a while (several seconds) depending on system memory size. Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
Some SoCs have more than two I2C busses. Instead of adding ifdef to the driver, macros are put into board header file where CONFIG_SYS_I2C_MXC is defined. Signed-off-by: NYork Sun <yorksun@freescale.com> CC: Heiko Schocher <hs@denx.de>
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This reverts commit 562f8df1. Note: Even un-reverting this patch couldn't works as expected, based on the latest testing from Heiko Schocher. Signed-off-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Cc: Heiko Schocher <hs@denx.de>
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- 19 4月, 2015 2 次提交
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由 Simon Glass 提交于
Move CONFIG_BOOT_STAGE and its associated options to Kconfig. Adjust existing users and code. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Joe Hershberger 提交于
Finish eliminating CamelCase from net.c and other failures Signed-off-by: NJoe Hershberger <joe.hershberger@ni.com> Acked-by: NSimon Glass <sjg@chromium.org>
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- 18 4月, 2015 1 次提交
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由 Hannes Petermaier 提交于
Sometimes, for example if the display is mounted in portrait mode or even if it is mounted landscape but rotated by 180 degrees, we need to rotate our content of the display respectively the framebuffer, so that user can read the messages which are printed out. For this we introduce the feature called "CONFIG_LCD_ROTATION", this may be defined in the board-configuration if needed. After this the lcd_console will be initialized with a given rotation from "vl_rot" out of "vidinfo_t" which is provided by the board specific code. If CONFIG_LCD_ROTATION is not defined, the console will be initialized with 0 degrees rotation. Signed-off-by: NHannes Petermaier <hannes.petermaier@br-automation.com> Signed-off-by: NHannes Petermaier <oe5hpm@oevsv.at> Acked-by: NNikita Kiryanov <nikita@compulab.co.il> [agust: fixed 'struct vidinfo' has no member named 'vl_rot' errors] Signed-off-by: NAnatolij Gustschin <agust@denx.de>
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- 10 4月, 2015 1 次提交
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由 Albert ARIBAUD \(3ADEV\) 提交于
introduce CONFIG_SPL_PANIC_ON_RAW_IMAGE. An SPL which define this will panic() if the image it has loaded does not have a mkimage signature. Signed-off-by: NAlbert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
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- 31 3月, 2015 1 次提交
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由 Peter Tyser 提交于
The CONFIG_MTD_NAND_VERIFY_WRITE has been removed from Linux for some time and a more generic method of NAND verification now exists in U-Boot. Signed-off-by: NPeter Tyser <ptyser@xes-inc.com> Tested-by: NHeiko Schocher <hs@denx.de> Acked-by: NHeiko Schocher <hs@denx.de>
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- 28 3月, 2015 1 次提交
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由 Masahiro Yamada 提交于
Move the option to Kconfig renaming it to CONFIG_HAVE_GENERIC_BOARD. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NAlexey Brodkin <abrodkin@synopsys.com>
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- 13 3月, 2015 5 次提交
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由 Masahiro Yamada 提交于
The Driver Model description in README was removed by commit 65eb659e (README: remove description about driver model configuration options), and was revived by mistake by commit b79dadf8 when resolving the conflict. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Cc: Tom Rini <trini@konsulko.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Nishanth Menon 提交于
621766: Under a specific set of conditions, executing a sequence of NEON or vfp load instructions can cause processor deadlock Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set L1NEON to 1 Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: NNishanth Menon <nm@ti.com> Tested-by: NMatt Porter <mporter@konsulko.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Nishanth Menon 提交于
430973: Stale prediction on replaced inter working branch causes Cortex-A8 to execute in the wrong ARM/Thumb state Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE to 1 Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: NNishanth Menon <nm@ti.com> Tested-by: NMatt Porter <mporter@konsulko.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Nishanth Menon 提交于
454179: Stale prediction may inhibit target address misprediction on next predicted taken branch Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE and disable branch size mispredict to 1 Also provide a hook for SoC specific handling to take place if needed. Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: NNishanth Menon <nm@ti.com> Tested-by: NMatt Porter <mporter@konsulko.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Nishanth Menon 提交于
Add workaround for Cortex-A15 ARM erratum 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." Implementations for SoC families such as Exynos, OMAP5/DRA7 etc will be widely different. Every SoC has slightly different manner of setting up access to L2ACLR and similar registers since the Secure Monitor handling of Secure Monitor Call(smc) is diverse. Hence an weak function is introduced which may be overriden to implement SoC specific accessor implementation. Based on ARM errata Document revision 18.0 (22 Nov 2013) Signed-off-by: NNishanth Menon <nm@ti.com> Tested-by: NMatt Porter <mporter@konsulko.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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- 06 3月, 2015 1 次提交
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由 Masahiro Yamada 提交于
All the DM-related configuration options are described in Kconfig helps. They should not be duplicated in README. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: NSimon Glass <sjg@chromium.org>
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- 05 3月, 2015 2 次提交
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由 Simon Glass 提交于
At present SPL uses a single stack, either CONFIG_SPL_STACK or CONFIG_SYS_INIT_SP_ADDR. Since some SPL features (such as MMC and environment) require a lot of stack, some boards set CONFIG_SPL_STACK to point into SDRAM. They then set up SDRAM very early, before board_init_f(), so that the larger stack can be used. This is an abuse of lowlevel_init(). That function should only be used for essential start-up code which cannot be delayed. An example of a valid use is when only part of the SPL code is visible/executable, and the SoC must be set up so that board_init_f() can be reached. It should not be used for SDRAM init, console init, etc. Add a CONFIG_SPL_STACK_R option, which allows the stack to be moved to a new address before board_init_r() is called in SPL. The expected SPL flow (for CONFIG_SPL_FRAMEWORK) is documented in the README. Signed-off-by: NSimon Glass <sjg@chromium.org> For version 1: Acked-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: NStefan Roese <sr@denx.de> Tested-by: NBo Shen <voice.shen@atmel.com> Acked-by: NBo Shen <voice.shen@atmel.com> Acked-by: NHeiko Schocher <hs@denx.de> Tested-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Stephen Warren 提交于
When the CPU is in non-secure (NS) mode (when running U-Boot under a secure monitor), certain actions cannot be taken, since they would need to write to secure-only registers. One example is configuring the ARM architectural timer's CNTFRQ register. We could support this in one of two ways: 1) Compile twice, once for secure mode (in which case anything goes) and once for non-secure mode (in which case certain actions are disabled). This complicates things, since everyone needs to keep track of different U-Boot binaries for different situations. 2) Detect NS mode at run-time, and optionally skip any impossible actions. This has the advantage of a single U-Boot binary working in all cases. (2) is not possible on ARM in general, since there's no architectural way to detect secure-vs-non-secure. However, there is a Tegra-specific way to detect this. This patches uses that feature to detect secure vs. NS mode on Tegra, and uses that to: * Skip the ARM arch timer initialization. * Set/clear an environment variable so that boot scripts can take different action depending on which mode the CPU is in. This might be something like: if CPU is secure: load secure monitor code into RAM. boot secure monitor. secure monitor will restart (a new copy of) U-Boot in NS mode. else: execute normal boot process Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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- 26 2月, 2015 1 次提交
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由 gaurav rana 提交于
Currently only normal hashing is supported using hardware acceleration. Added support for progressive hashing using hardware. Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: NGaurav Rana <gaurav.rana@freescale.com> CC: Simon Glass <sjg@chromium.org> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 25 2月, 2015 1 次提交
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由 York Sun 提交于
Add sync of refresh for multiple DDR controllers. DDRC initialization needs to complete first. Code is re-ordered to keep refresh close. Signed-off-by: NYork Sun <yorksun@freescale.com>
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- 17 2月, 2015 1 次提交
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由 Christian Gmeiner 提交于
A SoC like the i.MX6 supports more then one i2c bus. In oder to be able to use the eeprom command add a new define to specify the i2c bus to use. If CONFIG_SYS_I2C_EEPROM_BUS is not defined there is no functional change, else a call to i2c_set_bus_num(..) is done before calling i2c_read(..) and i2c_write(..). Signed-off-by: NChristian Gmeiner <christian.gmeiner@gmail.com> Acked-by: NStefano Babic <sbabic@denx.de>
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- 08 2月, 2015 1 次提交
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由 Heiko Schocher 提交于
make the HW WDT timeout configurable through the define CONFIG_AT91_HW_WDT_TIMEOUT. Signed-off-by: NHeiko Schocher <hs@denx.de>
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- 30 1月, 2015 2 次提交
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由 Ruchika Gupta 提交于
Modify rsa_verify to use the rsa driver of DM library .The tools will continue to use the same RSA sw library. CONFIG_RSA is now dependent on CONFIG_DM. All configurations which enable FIT based signatures have been modified to enable CONFIG_DM by default. Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> CC: Simon Glass <sjg@chromium.org> Acked-by: NSimon Glass <sjg@chromium.org>
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Some image types, like "KeyStone GP", do not have magic numbers to distinguish them from other image types. Thus, the automatic image type discovery does not work correctly. This patch also fix some integer type mismatches. Signed-off-by: NGuilherme Maciel Ferreira <guilherme.maciel.ferreira@gmail.com>
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- 16 1月, 2015 1 次提交
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由 Masahiro Yamada 提交于
All the 74xx_7xx boards are still non-generic boards: P3G4, ZUMA, ppmc7xx, ELPPC, mpc7448hpc2 Acked-by: NMarek Vasut <marex@denx.de> Acked-by: NStefan Roese <sr@denx.de> Acked-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Nye Liu <nyet@zumanetworks.com> Cc: Roy Zang <tie-fei.zang@freescale.com>
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- 06 1月, 2015 2 次提交
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由 Jeremiah Mahler 提交于
Fix various spelling and grammatical errors in the README. Signed-off-by: NJeremiah Mahler <jmmahler@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Masahiro Yamada 提交于
All the MPC824X boards are still non-generic boards: A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245 Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Josef Wagner <Wagner@Microsys.de> Cc: Torsten Demke <torsten.demke@fci.com> Cc: Jim Thompson <jim@musenki.com> Cc: Greg Allen <gallen@arlut.utexas.edu>
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- 19 12月, 2014 1 次提交
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由 Thierry Reding 提交于
Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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