- 25 4月, 2019 11 次提交
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由 Simon Goldschmidt 提交于
All socfpga boards except for vining_fpga use DM_I2C. Enable DM_I2C for this board and set the EEPROM defines via Kconfig (enabling CONFIG_I2C_EEPROM from MISC). Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Series-changes: 2 - added (this) patch to move socfpga_vining to DM_I2C
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由 Simon Goldschmidt 提交于
By enabling debug prints in malloc_simple, we can see that SPL for socfpga gen5 does by far not need the 8 KiB malloc pool currently allocated for SPL in pre-reloc phase. On socfpga_socrates, 1304 bytes are currently used (and this increases by ~200 bytes only for the sdram/reset fixes in socfpga-next). To prevent wasting precious SRAM space, let's reduce the initial heap used for SPL to 2 KiB. This is still some hundred bytes more than currently used. Also, the gen5 SPL enables stack and heap in DDR memory pretty early. Only the initial uclass/dm parsing, serial console and DDR initialization is done in the initial heap, so these 2 KiB should be enough for all boards. Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: NMarek Vasut <marex@denx.de>
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由 Simon Goldschmidt 提交于
This commit moves common config options used in all socfpga boards to select/imply in Kconfig. This both cleans up the defconfig files as well as makes future changes easier. Options implied/defaulted for all sub-arches: - SPL, SPL_DM, USE_TINY_PRINTF, NR_DRAM_BANKS Options implied/defaulted for implied for A10 & gen5: - FPGA_SOCFPGA, SYS_MALLOC_F_LEN, SYS_TEXT_BASE Options implied/defaulted for gen5: - SPL_STACK_R, SPL_SYS_MALLOC_SIMPLE, SPL_STACK_R_ADDR Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: NMarek Vasut <marex@denx.de>
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由 Simon Goldschmidt 提交于
If SPL post-reloc stage puts the stack into DDR, U-Boot should be able to do that, too. The reason to do so is that this way, U-Boot initial stack can be larger than SPL initial stack. In situations where we want to save the SPL in SRAM for next boot without reloading, this prevents overwriting the SPL DTB in SRAM if U-Boot stack usage gets too high. To achieve this, the malloc definition for a10 is moved up and sligthly changed to ensure CONFIG_SYS_INIT_RAM_SIZE is the remaining available size. Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: NMarek Vasut <marex@denx.de>
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由 Simon Goldschmidt 提交于
The comment about SPL memory layout for socfpga gen5 is outdated: the initial malloc memory is now at the end of the SRAM, gd is below it (see board_init_f_alloc_reserve). Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: NMarek Vasut <marex@denx.de>
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由 Simon Goldschmidt 提交于
This enables DM_RTC and RTC_M41T62 to enable support for the rtc on the socrates board. Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Simon Goldschmidt 提交于
This patch makes the on-board RTC work on the socfpga_socrates board. This rtc is present on the board, but it does not work (fails with a timeout). This patch adds a weak pull-up on the I2C0-SCL pin connected to the m41t82 RTC on this board. While the SDA line has a pull-up on the pcb, the pull-up on the SCL line seems to be missing. To work around this, enable the weak-pull-up feature on this pin. After applying this patch, the rtc timeout is gone and the 'date' command can access the rtc chip. Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Simon Goldschmidt 提交于
This adds a compatible string for m41t82. This ensures that this driver can be used for m41t82 in DM mode, too (asit was usable for this model in non-DM mode before). In addition, the HT bit has to be reset during probe, since the m41t82 chip sets it when entering battery standby mode. This patch ensures this driver works on socfpga_socrates. Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Simon Goldschmidt 提交于
Using this driver on socfpga gen5 with DM_I2C enabled leads to a data abort as the 'i2c' reset property cannot be found (the gen5 dtsi does not provide reset-names). The actual bug was to check 'if (&priv->reset_ctl)', which is never false. While at it, convert the driver to use 'reset_get_bulk' instead of looking at a specific named reset and also make it release the reset on driver remove before starting the OS. Fixes: 622597de ("i2c: designware: add reset ctrl to driver") Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: NHeiko Schocher <hs@denx.de>
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由 Simon Goldschmidt 提交于
This reverts commit 65a97e7f. The 'eeprom' command has been converted to work with DM_I2C in a patch submitted around the same time as this commit: commit 0c07a9b4 ("eeprom: Add device model based I2C support to eeprom command") Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NHeiko Schocher <hs@denx.de>
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由 Simon Goldschmidt 提交于
The current device model enabled eeprom code only works if CONFIG_SYS_I2C_EEPROM_BUS is set. This patch makes it work without that define so that the bus number passed to 'eeprom_init' is used. Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: NHeiko Schocher <hs@denx.de>
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- 24 4月, 2019 29 次提交
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由 Simon Goldschmidt 提交于
This updates MAINTAINERS and git-mailrc to add me as a co-custodian for socfpga. Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: NStefan Roese <sr@denx.de> Acked-by: NMarek Vasut <marex@denx.de>
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由 Tom Rini 提交于
- Add and enable brcmnand driver on a number of relevant platforms. Also add and enable LED drivers on more bcm platforms. - Various ARMv8 fixes/improvements, including extending PSCI functionality. - fs_loader improvments - Various FIT/SPL improvements - PCI bugfixes - Poplar platform ethernet support - MediaTek MMC improvements - Android boot improvements
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由 Eugeniu Rosca 提交于
Fix below CP warning triggered by the 'iminfo' output in another patch: WARNING: 'addrress' may be misspelled - perhaps 'address'? Fixes: 4f1318b2 ("common: image: minimal android image iminfo support") Signed-off-by: NEugeniu Rosca <erosca@de.adit-jv.com> Acked-by: NMarek Vasut <marek.vasut@gmail.com>
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由 Eugeniu Rosca 提交于
According to Android image format [1], kernel image resides at 1 page offset from the boot image address. Grab the magic number from there and allow U-Boot to handle LZ4-compressed KNL binaries instead of hardcoding compression type to IH_COMP_NONE. Other compression types, if needed, can be added later. Tested on H3ULCB-KF using the image detailed in [2]. [1] Excerpt from include/android_image.h +-----------------+ | boot header | 1 page +-----------------+ | kernel | n pages +-----------------+ | ramdisk | m pages +-----------------+ | second stage | o pages +-----------------+ [2] => iminfo 4c000000 ## Checking Image at 4c000000 ... Android image found kernel size: 85b9d1 kernel address: 48080000 ramdisk size: 54ddbc ramdisk addrress: 4a180000 second size: 0 second address: 48000800 tags address: 48000100 page size: 800 os_version: 1200012a (ver: 0.9.0, level: 2018.10) name: cmdline: buildvariant=userdebug Signed-off-by: NEugeniu Rosca <erosca@de.adit-jv.com>
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由 Heinrich Schuchardt 提交于
If CONFIG_UNIT_TEST is enabled we should enable the individual tests by default to ensure good test coverage. Reviewed-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
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由 Lars Povlsen 提交于
This fixes relaction isses with the PSCI_TABLE entries in the psci_32_table and psci_64_table. When using 32-bit adress pointers relocation was not being applied to the tables, causing PSCI handlers to point to the un-relocated code area. By using 64-bit data relocation is properly applied. The handlers are thus in the "secure data" area, which is protected by /memreserve/ in the FDT. Signed-off-by: NLars Povlsen <lars.povlsen@microchip.com>
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由 Trent Piepho 提交于
The cache flush of the kernel load area needs to be aligned outward to the DMA cache alignment. The operations are simpler if we think of this as aligning the start down, ALIGN_DOWN(load, ARCH_DMA_MINALIGN), and aligning the end up, ALIGN(load_end, ARCH_DMA_MINALIGN), and then find the length of the flushed region by subtracting the former from the latter. Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: NTrent Piepho <tpiepho@impinj.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Andreas Dannenberg 提交于
When using memalign() in a scenario where U-Boot is configured for full malloc support with simple malloc not explicitly enabled and before the full malloc support is initialized, a memory block is being allocated and returned without the alignment parameter getting honored. Fix this issue by replacing the existing memalign pre-full malloc init logic with a call to memalign_simple() this way ensuring proper alignment of the returned memory block. Fixes: ee038c58 ("malloc: Use malloc simple before malloc is fully initialized in memalign()") Signed-off-by: NAndreas Dannenberg <dannenberg@ti.com> Reviewed-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Stefan Roese 提交于
This patch adds a short message to the SPL NAND loader, which displays the source and destinations addresses including the size of the loaded image, like this: U-Boot SPL 2019.04-rc3-00113-g486efd8aaf (Mar 15 2019 - 14:18:02 +0100) Trying to boot from NAND Loading U-Boot from 0x00040000 (size 0x000a0000) to 0x22900000 I find this message quite helpful - hopefully others do so as well. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Fabien Parent 提交于
Add support for MediaTek MT8516 SoC. This include the file that will initialize the SoC after boot and its device tree. Signed-off-by: NFabien Parent <fparent@baylibre.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Fabien Parent 提交于
Add Pinctrl driver for MediaTek MT8516 SoC. Signed-off-by: NFabien Parent <fparent@baylibre.com> Acked-by: NRyder Lee <ryder.lee@mediatek.com>
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由 Fabien Parent 提交于
Add clock driver for MediaTek MT8516 SoC. Signed-off-by: NFabien Parent <fparent@baylibre.com> Acked-by: NRyder Lee <ryder.lee@mediatek.com> [trini: Redo whitespace] Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Fabien Parent 提交于
Add the implementation for the CLK_GATE_SETCLR_INV and CLK_GATE_NO_SETCLR flags. Signed-off-by: NFabien Parent <fparent@baylibre.com> Acked-by: NRyder Lee <ryder.lee@mediatek.com>
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由 Fabien Parent 提交于
We either need to use IS_ENABLED(CONFIG_FOO) or CONFIG_IS_ENABLED(FOO). IS_ENABLE(FOO) will always return false. This commit fixes the comparison by using the CONFIG_IS_ENABLED(FOO) syntax. Signed-off-by: NFabien Parent <fparent@baylibre.com>
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由 Fabien Parent 提交于
Add config for handling MT8516 SoC. Signed-off-by: NFabien Parent <fparent@baylibre.com> Acked-by: NRyder Lee <ryder.lee@mediatek.com>
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由 Fabien Parent 提交于
Some MediaTek SoC need an additional clock "source_cg". Enable this new clock. We reuse the same clock name as in the kernel. Signed-off-by: NFabien Parent <fparent@baylibre.com> Acked-by: NRyder Lee <ryder.lee@mediatek.com>
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由 Shawn Guo 提交于
The 'phy' reset of gmac device in kernel device tree is not generic enough for u-boot to use, so we need to overwrite the 'resets' property as needed. With this device tree fixup and poplar_defconfig changes, Ethernet starts working on Poplar board. Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Shawn Guo 提交于
It adds the driver for HIGMACV300 Ethernet controller found on HiSilicon SoCs like Hi3798CV200. It's based on a downstream U-Boot driver, but quite a lot of code gets rewritten and cleaned up to adopt driver model and PHY API. Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Shawn Guo 提交于
It adds a Driver Model compatible reset driver for HiSlicon platform. The driver implements a custom .of_xlate function, and uses .data field as reset register offset and .id field as bit shift. Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Shawn Guo 提交于
Some reset controllers support different polarities for reset operation, so let's add a polarity field into struct reset_ctl. Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thierry Reding 提交于
If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: NThierry Reding <treding@nvidia.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Thierry Reding 提交于
Make sure that we don't overflow the hose->regions array, otherwise we would end up overwriting the hose->region_count field and cause mayhem to ensue. Also print an error message when we'd be overflowing because it indicates that there aren't enough regions available and the number needs to be increased. Signed-off-by: NThierry Reding <treding@nvidia.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Adam Ford 提交于
With the migration to DM in SPL and the DT support, the old legacy code is no longer neaded, so this patch removes it Signed-off-by: NAdam Ford <aford173@gmail.com>
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由 Philippe Reynes 提交于
Enable the led support in the configuration of the board bcm963158. Signed-off-by: NPhilippe Reynes <philippe.reynes@softathome.com>
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由 Philippe Reynes 提交于
Enable the led controller in the device tree of the board bcm963158. Signed-off-by: NPhilippe Reynes <philippe.reynes@softathome.com>
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由 Philippe Reynes 提交于
Add the led controller in the bcm63158 device tree. Signed-off-by: NPhilippe Reynes <philippe.reynes@softathome.com>
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由 Philippe Reynes 提交于
Allow the led bcm6858 driver to be used on bcm63158. They have the same led controller. Signed-off-by: NPhilippe Reynes <philippe.reynes@softathome.com>
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由 Philippe Reynes 提交于
Enable the led support in the configuration of the board bcm968580xref. Signed-off-by: NPhilippe Reynes <philippe.reynes@softathome.com>
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由 Philippe Reynes 提交于
Enable the led controller in the device tree of the board bcm968580xref. Signed-off-by: NPhilippe Reynes <philippe.reynes@softathome.com>
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