This patch modifies the phy_zynqmp.c driver to use reset-controller
framework for asserting/de-asserting reset for High Speed modules.

Also fix documentation and dtsi.
Signed-off-by: NAnurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This patch add the reset nodes in zynqmp.dtsi which are used by
reset-controller framework
Signed-off-by: NAnurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Only silicon v1 requires this termination fix. With new nvmem soc
revision nvmem detection driver this can be autodetected at run time and
this flag is not needed.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add support for zynqmp nvmem firmware driver.
Signed-off-by: NNava kishore Manne <navam@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

1.0 rev is the latest rev. Describe information in eeprom.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Added pin control support in device tree for zynqmp.
Signed-off-by: NChirag Parekh <chirag.parekh@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Generic dtsi file can't use the same mac address for all.
U-Boot read mac from eeprom in zcu102 case and for others random mac
address is generated.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Just header change.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

dtc reports issues with it.
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb: Warning
(unit_address_format): Node
/amba/spi@ff040000/spi0_flash0@0/spi0_flash0@00000000 unit name should
not have leading 0s
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb: Warning
(unit_address_format): Node
/amba/spi@ff050000/spi1_flash0@0/spi1_flash0@00000000 unit name should
not have leading 0s
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning
(unit_address_format): Node
/amba/spi@ff040000/spi0_flash0@0/spi0_flash0@00000000 unit name should
not have leading 0s
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning
(unit_address_format): Node
/amba/spi@ff050000/spi1_flash0@0/spi1_flash0@00000000 unit name should
not have leading 0s
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add missing alias for gem0 for ep108 to have proper sequence number.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

- Enabling GTR lane-0 to PCIe
- Enabling PCIe node in device tree
Signed-off-by: NBharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Used defines rather than raw values for gpio configurations.
Signed-off-by: NChirag Parekh <chirag.parekh@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Some user space libraries reading platform compatible string and based
on that changing behavior. Mark revB board with revB string.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Trivial change.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Currently DP power domain (pd_dp) is not attached to any of the DP nodes which is
causing genpd to trigger a power down request for DP domain, making all DP related
peripherals unusable. So assign power domains for all DP related nodes to enable
proper accounting of DP power domain usage.
Signed-off-by: NJyotheeswar Reddy <jyothee@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This patch disables the smmu and also removes the mmu-masters
Signed-off-by: NNaga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This patch adds the calibration property with required value,
calculated based on rtc input crystal oscillator frequency (32.768Khz).
Signed-off-by: NNava kishore Manne <navam@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

AXI master interface in CEVA AHCI controller requires two unique
Write/Read ID tags per port. This is because, ahci controller uses
different AXI ID[3:0] bits for identifying non-data transfers(like
reading descriptors, updating PRD tables, etc) and data transfers
(like sending/receiving FIS).To make SMMU work with SATA we need to
add correct SMMU stream id for SATA. SMMU stream id for SATA is
determined based on the AXI ID[1:0] as shown below

	SATA SMMU ID =  <TBU number>, 0011, 00, 00, AXI ID[1:0]
	Note: SATA in  ZynqMp uses TBU1 so TBU number = 0x1, so
	      SMMU ID = 001, 0011, 00, 00, AXI ID[1:0]

Since we have four different AXI ID[3:0] (2 for port0 & 2 for port1
as said above) we get four different SMMU stream id's combinations
for SATA. These AXI ID can be configured using PAXIC register.
In this patch we assumed the below AXI ID values

 Read ID/ Write ID for Non-Data Port0 transfers = 0
 Read ID/ Write ID for Data Port0 transfers = 1
 Read ID/ Write ID for Non-Data Port1 transfers = 2
 Read ID/ Write ID for Data Port1 transfers = 3

Based on the above values,SMMU stream ID's for SATA will be 0x4c0 &
0x4c1 for PORT0, 0x4c2 & 0x4c3 for PORT1. These values needed to be
added to iommus dts property. This patch does the same.
Signed-off-by: NAnurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by: NRob Herring <robh@kernel.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

All gpio controllers should contain this property.
This property is not checked by the code that's why this issue wasn't
found earlier.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The correct register size is 0x10000, otherwise
it overlaps with other register space.
Signed-off-by: NHyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This patch will add names to the clocks used by GPU.
Signed-off-by: NMadhurkiran Harikrishnan <madhurki@xilinx.com>
Reviewed-by: NHyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This will simplify dt overlay structure for the whole PL.
Signed-off-by: NNava kishore Manne <navam@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Extract from Linux mainline patch:
The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).

A number of DTs are being remarkably creative, declaring the interrupt
to be edge triggered. A quick look at the TRM for the corresponding ARM
CPUs clearly shows that this is wrong, and I've corrected those.
For non-ARM designs (and in the absence of a publicly available TRM),
I've made them active low as well, which can't be completely wrong
as the GIC cannot disinguish between level low and level high.

The respective maintainers are of course welcome to prove me wrong.

While I was at it, I took the liberty to fix a couple of related issue,
such as some spurious affinity bits on ThunderX, and their complete
absence on ls1043a (both of which seem to be related to copy-pasting
from other DTs).
Acked-by: NDuc Dang <dhdang@apm.com>
Acked-by: NCarlo Caione <carlo@endlessm.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

PM callbacks are delivered to the NS OS. Let the PM driver handle the
IRQ and retrieve callback data from the secure HW.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Changed min-residence to 10ms(was 100 ms) for cpu-sleep-0.
Tried lower values 5ms and 8ms and it worked fine with Debug Off.
But to accommodate PM Debug On case, 10 ms is required. With this
change, low power idle state is into effect more frequently.
Measured boot time with PM debugs On and Off. No change observed
compared to 100ms value.
Signed-off-by: NJolly Shah <jollys@xilinx.com>
Acked-by: NWill Wong <willw@xilinx.com>
Tested-by: NKoteswararao Nayudu <kotin@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Fixed a typo in specifying "entry-method"
Signed-off-by: NJyotheeswar Reddy <jyothee@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add operating-points-v2.
Signed-off-by: NShubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add missing references to all cpu nodes.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

ZynqMP qspi driver is on the way to mainline
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Showing uart earlier.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This ID is available on zc1254.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Version string has unused fields 31:20 which can be used for exporting 9
bits from efuse IPDISABLE regs to recognize eg/cg/ev devices.

These efuse bits are setup for certain devices.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Warning is reported by checkpatch.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Extend Kconfig to cover SD1 level shifter mode.
Reported-by: NJason Wu <jason.hy.wu@gmail.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This modifies default value of config DEFINE_TCM_OCM_MMAP
to yes if CONFIG_MP is defined MP supports needs OCM and TCM
part of memory map.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The patch is adding external pmufw "Platform Management Unit firmware"
to boot.bin image. Boot.bin is a Xilinx format which bootrom is capable
to read and boot the system. pmufw is copied to the header data section
follows by u-boot-spl.bin. pmufw is consumed by PMU unit (Microblaze)
and SPL runs on a53-0.

This is generated command line when PMUFW_INIT_FILE is setup.

./tools/mkimage -T zynqmpimage -R ./"" -n
./"board/xilinx/zynqmp/pmufw.bin" -d spl/u-boot-spl.bin spl/boot.bin
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This patch provides a Kconfig option to use specified
memory for MMU table using reserve_mmu platform specific
routine. Here we used TCM space for MMU table.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This patch corrects the R5 release sequence by adding the
below steps.
1. Flush dcache to ensure that image loaded into memory.
2. Keep R5 reset just to ensure R5 in reset.
3. Disable caches before accessing TCM as with out this
   A53 can do speculative and may result in ECC failures
   if TCM's are not initialized. So, it is always better
   to disable dcaches before accessing TCM and enable back.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Reported-by: NJohn Linn <linnj@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This code is not used on this platform and it is not called.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>