1. 07 9月, 2016 3 次提交
  2. 02 9月, 2016 1 次提交
  3. 31 8月, 2016 1 次提交
    • S
      ARM: tegra: use numeric versioning for p2771-0000 · 7932d3e4
      Stephen Warren 提交于
      The board ID EEPROM and board ID stickers on p2771-0000 will use a numeric
      versioning scheme, with version numbers such as 000/100/200/300/400/500.
      Within NVIDIA, these versions are also known as A00/A01/A02/A03/A04/B00.
      However, that numbering scheme is not easily visible outside of NVIDIA,
      and so does not make much sense to use. Convert U-Boot to use the readily
      visible numeric scheme.
      
      Also, it turns out that the current A02 DT actually applies to board
      versions 000/100/200 (A00..A02). Consequently rename this to 000 not 200
      so that all U-Boot builds are named after the first version of the HW they
      support.
      Signed-off-by: NStephen Warren <swarren@nvidia.com>
      Signed-off-by: NTom Warren <twarren@nvidia.com>
      7932d3e4
  4. 30 8月, 2016 6 次提交
  5. 28 8月, 2016 13 次提交
  6. 27 8月, 2016 9 次提交
    • K
      rockchip: rk3399: update MAINTAINER file · bc2f8a54
      Kever Yang 提交于
      This patch add maintainer information for rk3399 evb.
      Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
      Acked-by: NSimon Glass <sjg@chromium.org>
      Reviewed-by: NAndreas Färber <afaerber@suse.de>
      bc2f8a54
    • T
      Merge branch 'master' of http://git.denx.de/u-boot-sunxi · c6b968da
      Tom Rini 提交于
      c6b968da
    • T
      nand: Fix set_dev checks for no device · 1cfce74f
      Tony Lindgren 提交于
      If we do nand device 0 command in u-boot on a device that has NAND support
      enabled but no NAND chip, we can get data abort at least on omaps.
      
      Fix the issue by replacing the check with nand_info[dev] as
      suggested by Scott Wood. The check for name existed before because before
      the array-to-pointer conversion there was no way to directly test
      nand_info[dev] for emptiness.
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      1cfce74f
    • M
      treewide: fix "followings" to "following" · c21fc7e2
      Masahiro Yamada 提交于
      Most of them are my mistakes.
      Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
      c21fc7e2
    • M
      tools: moveconfig: add Xtensa GCC prefix to CROSS_COMPILE list · 88e1346e
      Masahiro Yamada 提交于
      This is needed to move CONFIG options for the recently-added
      xtfpga_defconfig.
      
      The tarball of the pre-built toolchain can be downloaded from:
      https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
      88e1346e
    • S
      arm: cache: always flush cache line size for page table · 8f894a4d
      Stefan Agner 提交于
      The page table is maintained by the CPU, hence it is safe to always
      align cache flush to a whole cache line size. This allows to use
      mmu_page_table_flush for a single page table, e.g. when configure
      only small regions through mmu_set_region_dcache_behaviour.
      Signed-off-by: NStefan Agner <stefan.agner@toradex.com>
      Tested-by: NFabio Estevam <fabio.estevam@nxp.com>
      Reviewed-by: NSimon Glass <sjg@chromium.org>
      Reviewed-by: NHeiko Schocher <hs@denx.de>
      8f894a4d
    • S
      arm: cache: add support for LPAE for region D$ behavior · c5b3cabf
      Stefan Agner 提交于
      Add LPAE support for mmu_set_region_dcache_behaviour. The function
      is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7.
      Signed-off-by: NStefan Agner <stefan.agner@toradex.com>
      c5b3cabf
    • T
      arch/arm/Kconfig: Whitespace correction · e009bfa4
      Tom Rini 提交于
      Use a tab not 8 spaces.
      Signed-off-by: NTom Rini <trini@konsulko.com>
      e009bfa4
    • T
      ARM: Move SYS_CACHELINE_SIZE over to Kconfig · 067716ba
      Tom Rini 提交于
      This series moves the CONFIG_SYS_CACHELINE_SIZE.  First, in nearly all
      cases we are mirroring the values used by the Linux Kernel here.  Also,
      so long as (and in this case, it is true) we implement flushes in hunks
      that are no larger than the smallest implementation (and given that we
      mirror the Linux Kernel, again we are fine) it is OK to align higher.
      The biggest changes here are that we always use 64 bytes for CPU_V7 even
      if for example the underlying core is only 32 bytes (this mirrors
      Linux).  Second, we say ARM64 uses 64 bytes not 128 (as found in the
      Linux Kernel) as we do not need multi-platform support (to this degree)
      and only the Cavium ThunderX 88xx series has a use for such large
      alignment.
      
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Stefano Babic <sbabic@denx.de>
      Cc: Prafulla Wadaskar <prafulla@marvell.com>
      Cc: Luka Perkov <luka.perkov@sartura.hr>
      Cc: Stefan Roese <sr@denx.de>
      Cc: Nagendra T S <nagendra@mistralsolutions.com>
      Cc: Vaibhav Hiremath <hvaibhav@ti.com>
      Acked-by: NLokesh Vutla <lokeshvutla@ti.com>
      Cc: Steve Rae <steve.rae@raedomain.com>
      Cc: Igor Grinberg <grinberg@compulab.co.il>
      Cc: Nikita Kiryanov <nikita@compulab.co.il>
      Cc: Stefan Agner <stefan.agner@toradex.com>
      Acked-by: NHeiko Schocher <hs@denx.de>
      Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
      Cc: Peter Griffin <peter.griffin@linaro.org>
      Acked-by: NPaul Kocialkowski <contact@paulk.fr>
      Cc: Anatolij Gustschin <agust@denx.de>
      Acked-by: N"Pali Rohár" <pali.rohar@gmail.com>
      Cc: Adam Ford <aford173@gmail.com>
      Cc: Steve Sakoman <sakoman@gmail.com>
      Cc: Grazvydas Ignotas <notasas@gmail.com>
      Cc: Nishanth Menon <nm@ti.com>
      Cc: Stephen Warren <swarren@wwwdotorg.org>
      Cc: Robert Baldyga <r.baldyga@samsung.com>
      Cc: Minkyu Kang <mk7.kang@samsung.com>
      Cc: Thomas Weber <weber@corscience.de>
      Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
      Cc: David Feng <fenghua@phytium.com.cn>
      Cc: Alison Wang <b18965@freescale.com>
      Cc: Michal Simek <michal.simek@xilinx.com>
      Cc: Simon Glass <sjg@chromium.org>
      Cc: York Sun <york.sun@nxp.com>
      Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
      Cc: Mingkai Hu <mingkai.hu@nxp.com>
      Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
      Cc: Aneesh Bansal <aneesh.bansal@freescale.com>
      Cc: Saksham Jain <saksham.jain@nxp.com>
      Cc: Qianyu Gong <qianyu.gong@nxp.com>
      Cc: Wang Dongsheng <dongsheng.wang@nxp.com>
      Cc: Alex Porosanu <alexandru.porosanu@freescale.com>
      Cc: Hongbo Zhang <hongbo.zhang@nxp.com>
      Cc: tang yuantian <Yuantian.Tang@freescale.com>
      Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
      Cc: Josh Wu <josh.wu@atmel.com>
      Cc: Bo Shen <voice.shen@atmel.com>
      Cc: Viresh Kumar <viresh.kumar@linaro.org>
      Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
      Cc: Thomas Chou <thomas@wytron.com.tw>
      Cc: Joe Hershberger <joe.hershberger@ni.com>
      Cc: Sam Protsenko <semen.protsenko@linaro.org>
      Cc: Bin Meng <bmeng.cn@gmail.com>
      Cc: Christophe Ricard <christophe-h.ricard@st.com>
      Cc: Anand Moon <linux.amoon@gmail.com>
      Cc: Beniamino Galvani <b.galvani@gmail.com>
      Cc: Carlo Caione <carlo@endlessm.com>
      Cc: huang lin <hl@rock-chips.com>
      Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
      Cc: Xu Ziyuan <xzy.xu@rock-chips.com>
      Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
      Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar>
      Cc: Kever Yang <kever.yang@rock-chips.com>
      Cc: Samuel Egli <samuel.egli@siemens.com>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Hans de Goede <hdegoede@redhat.com>
      Cc: Ian Campbell <ijc@hellion.org.uk>
      Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com>
      Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
      Cc: Andre Przywara <andre.przywara@arm.com>
      Cc: Bernhard Nortmann <bernhard.nortmann@web.de>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Ben Whitten <ben.whitten@gmail.com>
      Cc: Tom Warren <twarren@nvidia.com>
      Cc: Alexander Graf <agraf@suse.de>
      Cc: Sekhar Nori <nsekhar@ti.com>
      Cc: Vitaly Andrianov <vitalya@ti.com>
      Cc: "Andrew F. Davis" <afd@ti.com>
      Cc: Murali Karicheri <m-karicheri2@ti.com>
      Cc: Carlos Hernandez <ceh@ti.com>
      Cc: Ladislav Michl <ladis@linux-mips.org>
      Cc: Ash Charles <ashcharles@gmail.com>
      Cc: Mugunthan V N <mugunthanvnm@ti.com>
      Cc: Daniel Allred <d-allred@ti.com>
      Cc: Gong Qianyu <Qianyu.Gong@freescale.com>
      Signed-off-by: NTom Rini <trini@konsulko.com>
      Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
      Acked-by: NChin Liang See <clsee@altera.com>
      Tested-by: NStephen Warren <swarren@nvidia.com>
      Acked-by: NPaul Kocialkowski <contact@paulk.fr>
      067716ba
  7. 26 8月, 2016 7 次提交