Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on
the PHYTEC phyCORE-i.MX6UL SOM (PCL063).

CPU:   Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 44C
Reset cause: POR
Board: PHYTEC phyCORE-i.MX6UL
I2C:   ready
DRAM:  256 MiB
NAND:  512 MiB
MMC:   FSL_SDHC: 0
In:    serial
Out:   serial
Err:   serial
Net:   FEC0

Working:
 - Eth0
 - i2C
 - MMC/SD
 - NAND
 - UART (1 & 5)
 - USB (host & otg)
Signed-off-by: NMartyn Welch <martyn.welch@collabora.com>

Currently if we have more than one phy on the MDIO bus, we do not have a
good mechanism for determining which should be used at runtime. Enable the
FEC driver to determine the address for the PHY from the device tree.
Signed-off-by: NMartyn Welch <martyn.welch@collabora.com>
Reviewed-by: NLukasz Majewski <lukma@denx.de>

The following NXP application notes and manual recommend to ensure the
IVT DCD pointer is Null prior to calling HAB API authenticate_image()
function:

- AN12263: HABv4 RVT Guidelines and Recommendations
- AN4581: Secure Boot on i.MX50, i.MX53, i.MX 6 and i.MX7 Series using
  HABv4
- CST docs: High Assurance Boot Version 4 Application Programming
  Interface Reference Manual

Commit ca89df7d ("imx: hab: Convert DCD non-NULL error to warning")
converted DCD non-NULL error to warning due to the lack of documentation
at the time of first patch submission. We have warned U-Boot users since
v2018.03, and it makes sense now to follow the NXP recommendation to
ensure the IVT DCD pointer is Null.

DCD commands should only be present in the initial boot image loaded by
the SoC ROM. Starting in HAB v4.3.7 the HAB code  will generate an error
if a DCD pointer is present in an image being authenticated by calling the
HAB RVT API. Older versions of HAB will process and run DCD if it is
present, and this could lead to an incorrect authentication boot flow.
Signed-off-by: NBreno Lima <breno.lima@nxp.com>
Reviewed-by: NFabio Estevam <festevam@gmail.com>

mpc85xx config.mk: Add support for -msingle-pic-base

Print information about Aquantia system interface and firmware loaded
on the phy.
Signed-off-by: NValentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

If System Interface protocol is USXGMII then enable USXGMII autoneg
Signed-off-by: NValentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

No mainline board enables CONFIG_MCAST_TFTP and there have been
compilation issues with the code for some time. Additionally, it has a
potential buffer underrun issue (reported as a side note in
CVE-2018-18439).

Remove the multicast TFTP code but keep the driver API for the future
addition of IPv6.

Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

ether_crc was added to the core net code in commit 53a5c424
("multicast tftp: RFC2090") so that other drivers could use it. However
the only current user of it is tsec.c so move it there.
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

According to the datasheet to access the extended registers we have to:

1. Write Register 31 Data = 0x0XYZ (Page 0xXYZ)
2. Read/Write the target Register Data
3. Write Register 31 Data = 0x0000 or 0xa42 (switch back to IEEE
   Standard Registers)

Hook the missing functions so that we can use the `mdio rx/wx` command to
easily access the extended registers.
Signed-off-by: NCarlo Caione <ccaione@baylibre.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Some architectures (MIPS) needs mapping to access IOMEM.
Fix that.

Fixes: f1dcc19b ("net: macb: Convert to driver model")
Signed-off-by: NRamon Fried <ramon.fried@gmail.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This patch add GPIO configuration support in mvneta driver.
Driver will handle PHY reset. GPIO pins should be set in device tree.

Ported from mvpp2x
[https://patchwork.ozlabs.org/patch/799654/]

Initial discussion to port the changes into mvneta
[https://patchwork.ozlabs.org/patch/1005765/]
Signed-off-by: NAditya Prayoga <aditya@kobol.io>
Tested-by: NDennis Gilmore <dgilmore@redhat.com>
Reviewed-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Some existing device trees don't specify a phy-mode so fallback to GMII
when a phy-mode is not provided.
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Reviewed-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

For KSZ9021, all skew register fields are 4-bit wide.
For KSZ9031, the clock skew register fields are 5-bit wide.

The common code in ksz90x1_of_config_group calculating the combined
register value checks if the requested value is above the maximum
and uses this maximum if so. The calculation of this maximum uses
the register width, but the check itself does not. It uses a hardcoded
value of 0xf, which is too low in case of the 5-bit clock (0x1f).
This detail was probably lost during driver unification.

Effect (only for KSZ9031 clock skews): For values greater 900 (== 0ps),
this silently results in 1860 (== +960ps) instead of the requested one.

Fix the check by using the bit width instead of hardcoded value(s).
Signed-off-by: NAndreas Pretzsch <apr@cn-eng.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

With CONFIG_REGEX enabled, ETHADDR_WILDCARD is set up for up to 10
interfaces (0..9) as the number can only have one digit.

On boards with more than 10 interfaces, this leads to the protection
and format checks being absent for eth10addr and above.

Fix this by changing ETHADDR_WILDCARD from "\\d?" to "\\d*" to allow
more than one digit.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

ETHADDR_WILDCARD is defined as the same value in both env_flags.h
and env_callback.h

As env_callback.h includes env_flags.h, remove the duplicate definition
from env_callback.h
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

When dealing with two ethernet ports and having "netretry" set
to "once", it could occur that the connection (e.g. an ARP
request) failed, hence the status of the netloop was
"NETLOOP_FAIL". Due to the setting of "netretry", the network
logic would then switch to the other network interface,
assigning "ret" with the return value of "net_start_again()".
If this call succeeded we would return 0 (i.e. success) to
the caller when in reality the network action failed.
Signed-off-by: NThomas RIENOESSL <thomas.rienoessl@bachmann.info>
Reviewed-by: NChristian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Current code forces all ports on a given Ethernet device to use the same
mdio device. In practice different ports might be wired to separate mdio
devices. Move the mdio device from the container struct mvpp2 to the per
port struct mvpp2_port.

Cc: Ken Ma <make@marvell.com>
Cc: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
Reviewed-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Current mdio base lookup code relies on a 'reg' property at the upper CP
node. There is no 'reg' property there in current DT files of Armada
CP110. Use ofnode_get_addr() instead since it provides proper DT address
translation.

Cc: Ken Ma <make@marvell.com>
Cc: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
Reviewed-by: NStefan Roese <sr@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Short frames are padded to the minimum allowed size of 60 bytes.
However, the designware driver sends old data in these padding bytes.
It is common practice to zero out these padding bytes ro prevent
leaking memory contents to other hosts.

Fix the padding code to zero out the padded bytes at the end.

Tested on socfpga gen5.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

The designware driver has a bug in setting the tx length into the dma
descriptor: it always or's the length into the descriptor without
zeroing out the length mask before.

This results in occasional packets being transmitted with a length
greater than they should be (trailer). Due to the nature of Ethernet
allowing such a trailer, most packets seem to be parsed fine by remote
hosts, which is probably why this hasn't been noticed.

Fix this by correctly clearing the size mask before setting the new
length.

Tested on socfpga gen5.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

The phy devices can be accessed via clause 22 or via clause 45.
This information can be deduced when we read phy id. if the phy id
is read without giving any MDIO Manageable Device Address (MMD), then
it conforms to clause 22. otherwise it conforms to clause 45.
Signed-off-by: NPankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Xilinx changes for v2019.04

tools:
- Fix zynqmpimage generation

zynq:
- Some configs/Kconfig/DT updates
- Enable REMAKE_ELF and OF_SEPARATE
- Topic boards update
- i2c cleanups and conversion to DM_I2C

zynqmp:
- Some configs/Kconfig/DT updates
- Board config cleanup
- Move arch folder to mach-zynqmp

versal:
- Enable DM_I2C, CMD_DM

zynq-gem:
- Fix driver cache handling

i2c:
- Live tree simple update

phy:
- Fixed phy cleanup

travis:
- Wire Versal SoC

Both boards have only controllers enabled that's why move to DM_I2C is
easy.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

There is no i2c connected in base DT that's why disable I2C commands.
Also remove zynq_zybo which is not needed now.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

With DM in place there is no need to have GEM addresses in headers. None
is using them.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

With DM in place there is no need to have GEM addresses in headers. None
is using them.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Most of the memory is being consumed by device binding code,
more space needed for other data structures.

Z-turn board has already hit the limit, others may follow soon.

Measuring only the memory consumed in device_bind_common, I've got
the following results (in decimal):

  root_driver:               108
  mod_exp_sw:                108
  amba:                      120
  serial@e0000000 aka uart0: 112
  serial@e0001000 aka uart1: 88
  spi@e000d000 aka qspi:     120
  sdhci@e0100000 aka mmc0:   455
  sdhci@e0100000.blk:        208
  slcr@f8000000:             96
  clkc@100:                  72
  (total)                    1487 = 0x5cf of 0x600
Signed-off-by: NAnton Gerasimov <tossel@gmail.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The miamiplus can use GEM0 through MIO pins, which requires a 125 MHz TX
clock to be generated. With the IO PLL at 1200 MHz this isn't possible, so
change it to run at 1000 and adjust the divisors accordingly. Also set the
GEM0 clock source to MIO instead of EMIO.
Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The miamiplus contains a speedgrade-2 device, which may run the CPU at 800MHz.
Change the PLL setting to 800MHz, and adapt the setpoints in the devicetree.
Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Update cadence i2c driver to support livetree
Similar changes were done by:
"net: zynq_gem: convert to use livetree"
(sha1: 26026e69)
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

It is useful to have this command enable to see which devices are
bind/probed.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Enable communication over i2c.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Similar changes was done for Zynq in past and this patch just follow
this pattern to separate cpu code from SoC code.

Move arch/arm/cpu/armv8/zynqmp/* -> arch/arm/mach-zynqmp/*
And also fix references to these files.

Based on
"ARM: zynq: move SoC sources to mach-zynq"
(sha1: 0107f240)
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Build warning was added by:
"fdt: Add warning about CONFIG_OF_EMBED"
(sha1: 841d5fba)

Zynq mini configurations are not moved yet and it is questionable if
make sense to move them too.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This patch enables CONFIG_REMAKE_ELF for Zynq platform
so that it generates u-boot.elf from binary which works
for all Zynq boards with OF_SEPARATE option enabled.
Signed-off-by: NSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Build warning was added by:
"fdt: Add warning about CONFIG_OF_EMBED"
(sha1: 841d5fba)

ZynqMP mini configurations are not moved yet and it is questionable if
make sense to move them too.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Bootrom is not capable to work with non align bootloader partition
that's why it is necessary to align it before boot.bin creation.
The patch is creating new spl/u-boot-spl-align.bin which is used only
for boot.bin.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Bootrom is not capable to work with non aligned bootloader sizes.
SPL with OF_SEPARATE generates non-align images quite often that's
why this change is required before OF_SEPARATE enableding.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>