Enable EFI partition support for ZynqMP.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

PCS auto negotaiation bit should be enabled
along with SGMII autonegotation enabled
in phy.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add support of SGMII to TI phy dp838367
Enable the SGMII and PCS settings in phy
control, CFG2 and BIST registers
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Return error from probe in case of invalid phy address.
This fixes the issue of uboot crash if phy is not detected.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

preboot macro load the uEnv.txt from mmc 0 when bootmode is mmc. uenvcmd is
executed after load of uEnv.txt if it is defined in the uEnv.txt env text
file.

The default importbootenv macro reads the uEnv.txt from mmc.

Additional to this, usb_loadbootenv is added to support loading uEnv.txt
from usb dev 0.
Signed-off-by: NJason Wu <jason.wu.misc@gmail.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Enable FLASH_BAR for these targets to be in sync with all zynq boards.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Initial Ceva Sata init code.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Handle all Xilinx ZynqMP boards with one fragment.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Read information about memory from DT. This patch simplify life with
synchronization between DT and board files.

dram_init() only needs maximum RAM size below 4GB that's why please sort
banks in memory node.
dram_init_banksize() copies memory setup to bi_dram[].
This will avoid reading information from DT twice.

Memory test start/end were changed to DDR location to let memtest still
compiled.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Simplify board config file.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This option enable adding new platform suport just by adding defconfig
and DTS file which will target generic configuration for SoC.
Make no sense to extend Kconfig just create a pointer between DTS and
configuration file.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Enabling writing files to FAT and EXT4 for USB.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Synchronize it with zynq platform.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Do not use debug() when printing error message. Use printf instead.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

OF_CONTROL is enabled by default that's why this is dead code.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Read information about timer and interrupts from DT. This is the first
small step to move timer and intc to DM.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

There is incorrect setting for USB which didn't work with origin
ps7_init_gpl.X files.
Use default setting for Digilent Zybo projects with HDMI in PL.
Signed-off-by: NMichal Simek <monstr@monstr.eu>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Zybo has on board I2C EEPROM which contains preprogrammed MAC address.
Signed-off-by: NMichal Simek <monstr@monstr.eu>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Provide board specific option how to read MAC address from ROM.
Do it in generic way to be reusable by differnet boards.
If this is not enough board specific functions can be created.

Signed-off-by: Joe Hershberger <joe.hershberger@gmail.com> # driver part
Signed-off-by: NMichal Simek <monstr@monstr.eu>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Enable overwriting variables out of main config file.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

In SGMII cases the isolate bit might set after DMA and
ethernet resets and hence check and clear during
setup_phy if it was set.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Pass appropriate interface type to phy_connect
instead of zero.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add support of Xilinx PCS/PMA core phy for Zynq
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add support of SGMII interface for zynq GEM.
Read xlnx,emio property from DT.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add phy driver support for xilinx PCS/PMA core
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The RTL8211B_driver structure in drivers/net/phy/realtek.c contains a
wrong PHY ID (0x1cc910 instead of 0x1cc912) in the uid field.

The lowest four bits of the PHY ID encode the chip revision (B+C/D/E/F)
of the RTL8211 and the code originally applied a mask of 0xfffff0 to
the PHY ID, so that matching the PHY ID to the appropriate driver code
was only done on the chip type (RTL8211), but not on a specific
revision.

After introduction of support for the RTL8211E, which needed another
startup function than the older chip revisions, commit
42205047 changed the mask to 0xffffff
to make the chip revision relevant for the match, but didn't provide
the now-relevant lower bits of the uid field for the RTL8211B/C.

Fix this by setting the full PHY ID in the RTL8211B_driver uid field.

Fixes: 42205047 ("net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is detected")
Signed-off-by: NKarsten Merker <merker@debian.org>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Freescale is now NXP.  I still work there, but I won't be using their
mail system for U-Boot development.
Signed-off-by: NScott Wood <oss@buserror.net>

Call blk_dread, blk_dwrite, blk_derase to ensure that the block cache is
used if enabled and to remove build breakage when CONFIG_BLK is enabled.
Signed-off-by: NEric Nelson <eric@nelint.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Call blk_dread, blk_dwrite, blk_derase to ensure that the block cache is
used if enabled and to remove build breakage when CONFIG_BLK is enabled.
Signed-off-by: NEric Nelson <eric@nelint.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Add a block device cache to speed up repeated reads of block devices by
various filesystems.

This small amount of cache can dramatically speed up filesystem
operations by skipping repeated reads of common areas of a block
device (typically directory structures).

This has shown to have some benefit on FAT filesystem operations of
loading a kernel and RAM disk, but more dramatic benefits on ext4
filesystems when the kernel and/or RAM disk are spread across
multiple extent header structures as described in commit fc0fc50f.

The cache is implemented through a minimal list (block_cache) maintained
in most-recently-used order and count of the current number of entries
(cache_count). It uses a maximum block count setting to prevent copies
of large block reads and an upper bound on the number of cached areas.

The maximum number of entries in the cache defaults to 32 and the maximum
number of blocks per cache entry has a default of 2, which has shown to
produce the best results on testing of ext4 and FAT filesystems.

The 'blkcache' command (enabled through CONFIG_CMD_BLOCK_CACHE) allows
changing these values and can be used to tune for a particular filesystem
layout.
Signed-off-by: NEric Nelson <eric@nelint.com>

- Update MAINTAINERS
- Update git-mailrc
Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This commit add support for 96Boards Dragonboard410C.
It is board based on APQ8016 Qualcomm SoC, complying with
96boards specification.
Features (present out of the box):
- 4x Cortex A53 (ARMv8)
- 2x USB Host port
- 1x USB Device port
- 4x LEDs
- 1x HDMI connector
- 1x uSD connector
- 3x buttons (Power, Vol+, Vol-/Reset)
- WIFI, Bluetooth with integrated antenna
- 8GiB eMMC

U-Boot boots chained with fastboot in 64-bit mode.
For detailed build instructions see readme.txt in board directory.
Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com>
Tested-by: NSimon Glass <sjg@chromium.org>

First supported chip is APQ8016 (that is compatible with MSM8916).
Drivers in SoC code:
- Reset controller (PSHOLD)
- Clock controller (very simple clock configuration for MMC and UART)
Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Tested-by: NSimon Glass <sjg@chromium.org>

This driver supports GPIOs present on PM8916 PMIC.
There are 2 device drivers inside:
- GPIO driver (4 "generic" GPIOs)
- Keypad driver that presents itself as GPIO with 2 inputs (power and reset)
Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Tested-by: NSimon Glass <sjg@chromium.org>

This PMIC is connected on SPMI bus so needs SPMI support enabled.
Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Tested-by: NSimon Glass <sjg@chromium.org>

Support SPMI arbiter on Qualcomm Snapdragon devices.
Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Tested-by: NSimon Glass <sjg@chromium.org>

This patch adds emulated spmi bus controller with part of
pm8916 pmic on it to sandbox and tests validating SPMI uclass.
Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Qualcom processors use proprietary bus to talk with PMIC devices -
SPMI (System Power Management Interface).
On wiring level it is similar to I2C, but on protocol level, it's
multi-master and has simple autodetection capabilities.
This commit adds simple uclass that provides bus read/write interface.
Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Tested-by: NSimon Glass <sjg@chromium.org>

This driver is able to reconfigure OTG controller into HOST mode.
Board can add board-specific initialization as board_prepare_usb().
It requires USB_ULPI_VIEWPORT enabled in board configuration.
Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: NMarek Vasut <marex@denx.de>
Tested-by: NSimon Glass <sjg@chromium.org>

Use definitions from ehci.h instead.
Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: NMarek Vasut <marex@denx.de>
Tested-by: NSimon Glass <sjg@chromium.org>