Disabling clk_ck clock leads to link up status loss in phy, which
leads to auto-negotiation restart before each network command
execution.

This issue is especially big for PXE boot protocol because of
auto-negotiation restarts before each configuration filename trial.

To avoid this issue don't disable clk_ck clock after it was enabled.
Signed-off-by: NDaniil Stas <daniil.stas@posteo.net>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: NRamon Fried <rfried.dev@gmail.com>

commit f1bcad22 ("net: e1000: add support for writing to EEPROM")
adds support for storing hwaddr in EEPROM however i210 devices do not
support this and thus results in errors such as:
Warning: e1000#0 failed to set MAC address'

Check if a flash device is present and if not return -ENOSYS indicating
this is not supported.
Signed-off-by: NTim Harvey <tharvey@gateworks.com>
Reviewed-by: NRamon Fried <rfried.dev@gmail.com>

Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NRamon Fried <rfried.dev@gmail.com>

- fsl-qoriq: Bug fixes related pfe, eth, thermal node, vid.c, cpu release,
  mmc, usb, env, etc for Layerscape boards
- powerpc: Update Maintainers for some boards.

- ae350 related dts fixes.

Add Priyanka Jain as MAINTAINER for
 T2080RDB_revD_defconfig,
 T2080RDB_revD_NAND_defconfig,
 T2080RDB_revD_SDCARD_defconfig and
 T2080RDB_revD_SPIFLASH_defconfig
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

Change the USB erratum number A-050106 to A-050204 as A-050106 is
a duplicate and never be published.

Fixes 0cfa00cd (“armv8: Add workaround for USB erratum A-050106”)
Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
[Rebased]
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

Under DM, we rely on u-boot's device tree to provide the correct PHY
addresses. The board_fix_fdt callback is intended to be used for
device tree fixups before relocation. Unfortunately, this isn't an
option when booting from flash since the device tree isn't writable
before relocation.

This patch introduces the CONFIG_T2080RDB_REV_D option to signal that a
board revision D or up is the target. The config option is used to set
the correct Aquantia PHY address in the board's u-boot device tree.

Defconfig files with the option enable explicitly are added for
convenience.
Signed-off-by: NCamelia Groza <camelia.groza@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

The T2080RDB boards revisions D and up have updated 10G Aquantia PHYs
connected to MAC1 and MAC2. The second Aquantia PHY is located at a
different address on the MDIO bus compared to rev C (0x8 instead of 0x1).

Fix-up the Linux device tree to update the PHY address for the second
Aquantia PHY on boards revisions D and up. Also rename the PHY node to
reflect the changes.
Signed-off-by: NCamelia Groza <camelia.groza@nxp.com>
[Rebased]
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

Detect and print the board revision version based on the CPLD registers.
Signed-off-by: NCamelia Groza <camelia.groza@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Both DM_ETH and DM_PCI are enabled for the T2080RDB board. Remove the
board_eth_init() callback and the non-DM_ETH code paths since they are not
needed anymore.
Signed-off-by: NCamelia Groza <camelia.groza@nxp.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

A system clock of 66MHz was chosen for the pg-wcom-ls102xa.
Compared to the Evalboard, this corresponds to a reduction of 1/3.
The system counter clock should have been reduced accordingly,
but that was not the case, so we had a system time that was
1/3 behind the real time.

This patch corrects the system counter clock to
8.333MHz = 66.667MHz / 8.
Signed-off-by: NRainer Boschung <rainer.boschung@hitachi-powergrids.com>
Signed-off-by: NAleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

This patch adds the front led initialization and the application
buffer enable to the eraly board inititlaization.
Signed-off-by: NRainer Boschung <rainer.boschung@hitachi-powergrids.com>
Signed-off-by: NAleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

In order to improve power consumption ls102x allows to disable peripherals
that are not in use.
This patch follows SELI8 HW design description and disables peripherals
that are not in use in our designs, the same configuration is applicable
and for EXPU1.

This patch uses available hwconfig option for updating ls102x device
disable configuration.
Signed-off-by: NAleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

The default behavior in the latest u-boot revisions is to rotate the
active net device to the next available if the requested link is not
established.

For our ls102x based devices this would mean that if active debug net
device is not available, u-boot will rotate and set the next net device
that is one of the estar adapters.
To return from this situation manual action to set correct ethact
adapter will be needed and this can be annoying when working in
debug mode.

Setting ethrotate=no will disable net adapter rotation and will make sure
that the primary adapter is always used.
Signed-off-by: NAleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

This is most probably a typo, and in older u-uboot versions is same as
'saveenv', in the newer uboot versions there is a separate 'save' command
that is different from 'saveenv'.
Signed-off-by: NAleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

In our designs we reserve PRAM area at the end of the RAM, and in order
this area to be visible and taken into account by the u-boot memory mgmt
CONFIG_PRAM has to be defined.
Signed-off-by: NAleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

From production view this is standard test executed during production on
all linux based foxmc cards.
On CENT2 HW defined memory region is zero means that some DDR accesses are
done by memory_post_dataline and memory_post_addrline but pattern tests
are skipped that's why mem_regions is fast there.

On ls102x for the complete DDR region of 1GiB memory_regions_post_test
takes approx. 4min and this is too much for production, so this patch
defines only 1MiB region as compromise.
Signed-off-by: NAleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

The EXPU1 design is a new 40G capable ethernet service unit card for
Hitachi-Powergrids wired-com product lines.

The base SoC is same as for already added SELI8 card, consequently the
already added u-boot support for SELI8 is reused.
Signed-off-by: NRainer Boschung <rainer.boschung@hitachi-powergrids.com>
Signed-off-by: NAleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
[Fixed new line error at EOF]
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

Add "Priyanka Jain <priyanka.jain@nxp.com>" as
MAINTAINER for t102xrdb board.
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

Add "Priyanka Jain <priyanka.jain@nxp.com>" as
MAINTAINER for p2041rdb board.
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

Add "Priyanka Jain <priyanka.jain@nxp.com>" as
MAINTAINER for p1_p2_rdb_pc board.
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

Add "Priyanka Jain <priyanka.jain@nxp.com>" as
MAINTAINER for t4rdb board.
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

Address and size cells on SOC are set to 1. But gpio nodes are specified
with 2 cells. This fixes the gpio nodes to correct cells.
Signed-off-by: NLasse Klok Mikkelsen <lkmi@prevas.dk>
Reviewed-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Current tsec adapter sets adapter gigabit capabilities by default, and in
reality this must not always be the case.
It is possible that tsec adapter is used for 100Mbps connection, and in
this case setting 1000Mbps capabilities can lead to some side effects such
longer autoneg process.

In our ls102x designs this problem leads to long autoneg times (> 4 sec)
in case board rgmii link is 100Mbps capable only.
Limiting the rgmii link capabilities provides faster and smoother
link establishment.
Signed-off-by: NAleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: NVladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Commit df86d324 breaks linux kernel and product application boot.

Linux kernel and our product application scripts are expecting 0x prefix
for hexadecimal values, while env_set_hex writes them without a prefix.

This patch partially revert env_set_hex usage for affected env variables.
Signed-off-by: NAleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

During the mainlining of the board this was by mistake set to sector size.
Our user space env scripts are expecting envsize of 0x4000, and setting
this differently will break our cross-platform compatibility.
Signed-off-by: NAleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33. CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT
is used instead.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Acked-by: Michael Walle <michael@walle.cc> [for kontron-sl28]
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

There is no i.MX board using such option. Drop it.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

For eSDHC, power supply is through peripheral circuit.
Some eSDHC versions have value 0 of the bit but that
does not reflect the truth. 3.3V is common for SD/MMC,
and is supported for all boards with eSDHC in current
u-boot. So, make 3.3V is supported in default in code.
CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT can be enabled if
future board does not support 3.3V.

This is also a fix-up for one previous patch, which converted
to use IS_ENABLED() for CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
that is not a Kconfig option.

Fixes: 52faec31 ("mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()")
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

These boards, according to the schematic and per the board I own, use an
M24256-BWDW6TP I2C EEPROM which requires two address bytes.

This fixes the 'mac' command which is used to program, among other
things, the MAC addresses for the ethernet interfaces on the board.
Signed-off-by: NMatt Merhar <mattmerhar@protonmail.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

IFC NOR flash base address of ls2088a is 0x580000000,
and offset of env crc is 0x500000, so fix the macro
CONFIG_ENV_ADDR to fix synchronous exception(access illegal address)

Fixes: 59071804 ("configs: ls2080a: Correct ENV_ADDR value")
Signed-off-by: NBiwen Li <biwen.li@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NKuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Add properties related to eMMC HS400 mode for esdhc1.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Stop to initialize the PCIe controller if it's disabled by RCW.

Fixes: 118e58e2 ("pci: layerscape: Split the EP and RC driver")
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Read Linux PPFE firmware from flash partition and pass it to Linux through
FDT entry. So that we can avoid placing PPFE firmware in Linux rootfs.
(FDT may increase at max by 64KB)
Signed-off-by: NChaitanya Sakinam <chaitanya.sakinam@nxp.com>
Signed-off-by: NAnji J <anji.jagarlmudi@nxp.com>
Signed-off-by: NBiwen Li <biwen.li@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Enable eMMC HS400 workarounds for LX2160A/LX2162A.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

For cpu release command, check whether PSCI is supported firstly,
if supported, use PSCI to kick off secondary cores, otherwise still
use spin table.
Signed-off-by: NJiafei Pan <Jiafei.Pan@nxp.com>
[Fixed checkpatch alignment CHECKs]
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

Add check for return value of adjust_vdd()
Signed-off-by: NBiwen Li <biwen.li@nxp.com>
Signed-off-by: NPriyanka Singh <priyanka.singh@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Current logic in riscv_get_ipi() for Andes PLICSW does not look
correct. The mask to test IPI pending bits for a hart should be
left shifted by (8 * gd->arch.boot_hart), just the same as what
is done in riscv_send_ipi().

Fixes: 8b3e97ba ("riscv: add functions for reading the IPI status")
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NRick Chen <rick@andestech.com>
Tested-by: NRick Chen <rick@andestech.com>