As the u-boot-spl.lds is moved to <arch/arm/mach-at91> directory.
So, correct the path for sama5d4 related boards.
Signed-off-by: NBo Shen <voice.shen@atmel.com>

Enable the power for MMC/SD port.
Signed-off-by: NBo Shen <voice.shen@atmel.com>

HUSH parser will handle the variable easier. That will be helpful for
write a complicated U-Boot commands or varaibles.
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Acked-by: NBo Shen <voice.shen@atmel.com>

Add a mmc default config, which will save the environment in a FAT file
(uboot.env) of MMC.
Signed-off-by: NJosh Wu <josh.wu@atmel.com>

This patch enable the MCI support for at91sam9rlek board.
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
[rebase on ToT]
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Update the nand flash offset mapping, default nand bootcmand and
bootargs to align with linux4sam.org.
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Acked-by: NBo Shen <voice.shen@atmel.com>

Signed-off-by: NTom Rini <trini@konsulko.com>

Boards that haven't been converted to GENERIC_BOARD does
*not* mean they should be removed.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

- add more targets for building with buildman:
  - avr32
  - m68k

and while at it, sort the list alphabetical
Reviewed-by: NRoger Meier <r.meier@siemens.com>
Signed-off-by: NHeiko Schocher <hs@denx.de>

This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Cc: Larry Johnson <lrj@acm.org>

This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Cc: Eric Millbrandt <emillbrandt@dekaresearch.com>

They have not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Cc: Erik Theisen <etheisen@mindspring.com>

They have not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Cc: Stephen Williams <steve@icarus.com>

This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

We don't want that CONSOLE is redirected to LCD upon init, we rather prefer
that console is still on the serial line.
Signed-off-by: NHannes Petermaier <oe5hpm@oevsv.at>

Commit f022d36e introduces
error register offset.

Change the "char reserved3[59]" to "char reserved3[56]".
Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
Tested-by: NFabio Estevam <fabio.estevam@freescale.com>

The build break was caused by one of my previous commit:
'odroid: defconfig: disable memset at malloc init'

It removes the dts from odroid defconfig - rebase mistake.
Signed-off-by: NPrzemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NMinkyu Kang <mk7.kang@samsung.com>

Signed-off-by: NHannes Petermaier <hannes.petermaier@br-automation.com>
Signed-off-by: NHannes Petermaier <oe5hpm@oevsv.at>

Since commit e02ee254 (kconfig: switch to single .config
configuration), the prefixes in defconfig files such as "+S:",
"+ST:", etc., are meaningless.

This commit was generated by the following command:

  find configs -name '*_defconfig' | xargs sed -i 's/^+*S*T*://'
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

In the case of BUILD_NBUILDS > 1, MAKEALL would try to print the size
immediately after the u-boot binary is deleted by the call to:

make -s clean

Move the size print to before the clean
Signed-off-by: NJoe Hershberger <joe.hershberger@ni.com>

Panasonic's System LSI products, UniPhier SoC family, have been
transferred to Socionext Inc.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

I have transferred to Socionext Inc.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

I have transferred to Socionext Inc.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The Driver Model description in README was removed by commit
65eb659e (README: remove description about driver model
configuration options), and was revived by mistake by commit
b79dadf8 when resolving the conflict.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Cc: Tom Rini <trini@konsulko.com>
Acked-by: NSimon Glass <sjg@chromium.org>

This should make it more clear why there appear to be C pre-processor
symbols in the file that contain mixed case. They're really error
messages.
Suggested-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

When Beagle X15 is connected to Gigabit switch, it takes
more time to finish auto-negotiation than on a 10/100 switch.

The default 4 second limit times-out more often than not. This is
observed when testing with a D-Link DGS-1008A desktop switch.

Increase the auto-negotiation time-out for Beagle-X15 to handle
this case.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

RX51 has a secure logic which uses different parameters compared to
traditional implementation. So, make the generic secure acr write
over-ride-able by board file and refactor rx51 code to use this.

While at it, enable the OMAP3 specific errata code for 454179, 430973,
621766.
Signed-off-by: NNishanth Menon <nm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Enable the OMAP3 specific errata code for 454179, 430973, 621766
and while at it, remove legacy non-revision checked errata logic.
Signed-off-by: NNishanth Menon <nm@ti.com>
Tested-by: NMatt Porter <mporter@konsulko.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Update to existing recommendation for L2ACTLR configuration to prevent
system instability and optimize performance.

These apply to both OMAP5 and DRA7.
Reported-by: NVivek Chengalvala <vchengalvala@ti.com>
Signed-off-by: NNishanth Menon <nm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

This patch enables the workaround for ARM errata 798870 for OMAP5 /
DRA7 which says "If back-to-back speculative cache line fills (fill
A and fill B) are issued from the L1 data cache of a CPU to the
L2 cache, the second request (fill B) is then cancelled, and the
second request would have detected a hazard against a recent write or
eviction (write B) to the same cache line as fill B then the L2 logic
might deadlock."

An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced
here as well.
Signed-off-by: NPraveen Rao <prao@ti.com>
Signed-off-by: NAngela Stegmaier <angelabaker@ti.com>
Signed-off-by: NNishanth Menon <nm@ti.com>
Tested-by: NMatt Porter <mporter@konsulko.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

omap_smc1 is now generic enough to remove duplicate
omap3_gp_romcode_call logic that omap3 introduced.

As part of this change, move to using the generic lowlevel_init.S for
omap3 as well.
Signed-off-by: NNishanth Menon <nm@ti.com>
Tested-by: NMatt Porter <mporter@konsulko.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

This is in preperation of using generic cross OMAP code.
Signed-off-by: NNishanth Menon <nm@ti.com>
Tested-by: NMatt Porter <mporter@konsulko.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup
PL310 control register, however, that is something that is generic
enough to be used for OMAP5 generation of processors as well. The only
difference being the service being invoked for the function.

So, convert the service to a macro and use a generic name (same as
that used in Linux for some consistency). While at that, also add a
data barrier which is necessary as per recommendation.

While at this, smc #0 is maintained as handcoded assembly thanks to
various gcc version eccentricities, discussion thread:
http://marc.info/?t=142542166800001&r=1&w=2Signed-off-by: NNishanth Menon <nm@ti.com>
Tested-by: NMatt Porter <mporter@konsulko.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

621766: Under a specific set of conditions, executing a sequence of
	NEON or vfp load instructions can cause processor deadlock
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set L1NEON to 1

Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: NNishanth Menon <nm@ti.com>
Tested-by: NMatt Porter <mporter@konsulko.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

430973: Stale prediction on replaced inter working branch causes
	Cortex-A8 to execute in the wrong ARM/Thumb state
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE to 1

Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: NNishanth Menon <nm@ti.com>
Tested-by: NMatt Porter <mporter@konsulko.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

454179: Stale prediction may inhibit target address misprediction on
	next predicted taken branch
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around:  Set IBE and disable branch size mispredict to 1

Also provide a hook for SoC specific handling to take place if needed.

Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: NNishanth Menon <nm@ti.com>
Tested-by: NMatt Porter <mporter@konsulko.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Add workaround for Cortex-A15 ARM erratum 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."

Implementations for SoC families such as Exynos, OMAP5/DRA7 etc
will be widely different.

Every SoC has slightly different manner of setting up access to L2ACLR
and similar registers since the Secure Monitor handling of Secure
Monitor Call(smc) is diverse. Hence an weak function is introduced
which may be overriden to implement SoC specific accessor implementation.

Based on ARM errata Document revision 18.0 (22 Nov 2013)
Signed-off-by: NNishanth Menon <nm@ti.com>
Tested-by: NMatt Porter <mporter@konsulko.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

The purpose of this build target is to do SPL over USB RNDIS.  We remove
YMODEM, MMC and NAND (and re-set ENV to be built-in) as when those are needed
we can use the other build targets.  This brings us well under size limit again.
Signed-off-by: NTom Rini <trini@konsulko.com>