- 05 4月, 2018 1 次提交
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由 Alexander Graf 提交于
When we enable CONFIG_OF_BOARD on Raspberry Pis, we may end up without serial console support in early boot. Hence we need to make the serial port optional, otherwise we will never get to the point where serial would be probed. Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 03 4月, 2018 1 次提交
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@konsulko.com>
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- 02 4月, 2018 1 次提交
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- 01 4月, 2018 5 次提交
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由 Masahiro Yamada 提交于
This header needs to know 'fdt_region' is a struct for the fit_region_make_list() prototype. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Masahiro Yamada 提交于
fdt_region.c does not depend on anything in libfdt_internal.h Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Masahiro Yamada 提交于
This macro is locally referenced in common/image-fdt.c Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Mario Six 提交于
Commit 286ede65 ("drivers: core: Add translation in live tree case") made dev_get_addr always use proper bus translations for addresses read from the device tree. But this leads to problems with certain busses, e.g. I2C busses, which run into an error during translation, and hence stop working. It turns out that of_translate_address() and fdt_translate_address() stop the address translation with an error when they're asked to translate addresses for busses where #size-cells == 0 (comment from drivers/core/of_addr.c): * Note: We consider that crossing any level with #size-cells == 0 to mean * that translation is impossible (that is we are not dealing with a value * that can be mapped to a cpu physical address). This is not really specified * that way, but this is traditionally the way IBM at least do things To fix this case, we check in both the live-tree and non-live tree-case, whether the bus of the device whose address is about to be translated has size-cell size zero. If this is the case, we just read the address as a plain integer and return it, and only apply bus translations if the size-cell size if greater than zero. Signed-off-by: NMario Six <mario.six@gdsys.cc> Signed-off-by: NMartin Fuzzey <mfuzzey@parkeon.com> Reported-by: NMartin Fuzzey <mfuzzey@parkeon.com> Fixes: 286ede65 ("drivers: core: Add translation in live tree case") Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Andy Yan 提交于
dm_scan_fdt_node can't work when live dt is active, we should use dm_scan_fdt_live instead. Signed-off-by: NAndy Yan <andy.yan@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 31 3月, 2018 7 次提交
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由 Andre Heider 提交于
The value at the end of the rom is not a pointer, it is an offset relative to the end of rom. Signed-off-by: NAndre Heider <a.heider@gmail.com>
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由 Andre Heider 提交于
The cast breaks the pointer on 64bit archs, so lets get rid of it. Signed-off-by: NAndre Heider <a.heider@gmail.com> Reviewed-by: NAlexander Graf <agraf@suse.de>
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由 Kever Yang 提交于
Use live dt interface for pinctrl_select_state_full() Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
Add api for who can not get phandle from a device property. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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- 30 3月, 2018 25 次提交
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由 Ken Ma 提交于
Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Wilson Ding 提交于
This patch enabled PCIe port on both devel-board and espressobin board. Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NWilson Ding <dingwei@marvell.com> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Wilson Ding 提交于
Signed-off-by: NWilson Ding <dingwei@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Wilson Ding 提交于
This patch introduced the Aardvark PCIe driver based driver model. The PCIe driver is supposed to work in Root Complex mode. It only supports X1 lane width. Signed-off-by: NWilson Ding <dingwei@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38725Reviewed-by: NVictor Gu <xigu@marvell.com> Reviewed-by: NHua Jing <jinghua@marvell.com> Tested-by: NHua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Wilson Ding 提交于
This patch added a new region of 32MiB AT 0xe800.0000 to Armada37x0's memory map. This region is supposed to be mapped in MMU in order to enable the access to the PCI I/O or MEM resources. Signed-off-by: NWilson Ding <dingwei@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38724Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Reviewed-by: NVictor Gu <xigu@marvell.com> Signed-off-by: NKen Ma <make@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
Since the new pinctrl/gpio driver is used, so this patch removes the old board specific pin control settings. Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
The commit "arm64: mvebu: Add pinctrl nodes for Armada 3700" has added new pinctrl nodes. This reverts commit f7cab0f9. Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
Reviewed-on: http://vgitil04.il.marvell.com:8080/43289Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Reviewed-by: NKostya Porotchkin <kostap@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
This patch corrects below mpp definitions for armada 3720 DB board and ESPRESSOBin board: - "smi" pins group is added and "smi" function is set for eth0; - Now pcie pins are used as gpio to implement PCIe function in hardware, so "pcie" group function is changed to "gpio". Reviewed-on: http://vgitil04.il.marvell.com:8080/43287Reviewed-by: NHua Jing <jinghua@marvell.com> Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
This patch corrects below mpp definitions: - The sdio_sb group is composed of 6 pins and not 5; - The rgmii group contains pins mpp2[17:6] and not mpp2[19:6]; - Pin of group "pmic0" is mpp1[6] but not mpp1[16]; - Pin of group "pmic1" is mpp1[7] but not mpp1[17]; - A new group "smi" is added in A0 with 2 pins - mpp2[19:18], its bitmask is bit4; - Group "pcie1" has 3 pins in A0 - mpp2[5:3], its bit mask is bit5 | bit9 | bit10 but not bit4; - Group "ptp" has 3 pins in A0 as Z1, but its bitmask is changed to bit11 | bit12 | bit13. Reviewed-on: http://vgitil04.il.marvell.com:8080/43288Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Reviewed-by: NHua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
For armada_37xx_update_reg(), the parameter offset should be pointer so that it can be updated, otherwise offset will keep old value, and then when offset is larger than or equal to 32 the mask calculated by "BIT(offset)" will be 0 in gpio chip hook functions, it's an error, this patch set offset parameter of armada_37xx_update_reg() as pointer. Reviewed-on: http://vgitil04.il.marvell.com:8080/43287Reviewed-by: NHua Jing <jinghua@marvell.com> Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
Pin 23 on South bridge does not belong to the rgmii group. It belongs to a separate group which can have 3 functions. Due to this the fix also have to update the way the functions are managed. Until now each groups used NB_FUNCS(which was 2) functions. For the mpp23, 3 functions are available but it is the only group which needs it, so on the loop involving NB_FUNCS an extra test was added to handle only the functions added. The bug was visible when the gpio regulator used the gpio 23, the whole rgmii group was setup to gpio which broke the Ethernet support on the Armada 3720 DB board. Thanks to this patch, the UHS SD cards (which need the vqmmc) _and_ the Ethernet work again. Reviewed-on: http://vgitil04.il.marvell.com:8080/43284Reviewed-by: NHua Jing <jinghua@marvell.com> Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
The number of pins in South Bridge is 30 and not 29. There is a fix for the driver for the pinctrl, but a fix is also need at device tree level for the GPIO. Reviewed-on: http://vgitil04.il.marvell.com:8080/43286Reviewed-by: NHua Jing <jinghua@marvell.com> Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
On the south bridge we have pin from 0 to 29, so it gives 30 pins (and not 29). Reviewed-on: http://vgitil04.il.marvell.com:8080/43285Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Reviewed-by: NHua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
Add mmc pins, pcie pins and sdio pins definition and do these pins' configuration for DB board and espressobin board; Add uart2 pins configuration for DB board. Reviewed-on: http://vgitil04.il.marvell.com:8080/40914Reviewed-by: NWilson Ding <dingwei@marvell.com> Tested-by: NWilson Ding <dingwei@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
Reviewed-on: http://vgitil04.il.marvell.com:8080/40913Reviewed-by: NWilson Ding <dingwei@marvell.com> Tested-by: NWilson Ding <dingwei@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
This patch enable the PINCTRL and GPIO support, including the GPIO command on the Armada 3720 espressobin board. Reviewed-on: http://vgitil04.il.marvell.com:8080/40746Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Reviewed-by: NWilson Ding <dingwei@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Mark Kettenis 提交于
The various load address values are taken from the a37xx configuration and match the dowstream 'u-boot-2017.03-armada-17.10' release where appropriate. Signed-off-by: NMark Kettenis <kettenis@openbsd.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Alexander Graf 提交于
The kwbimage format is reading beyond its header structure if it misdetects a Xilinx Zynq image and tries to read it. Fix it by sanity checking that the header we want to read fits inside our file size. Signed-off-by: NAlexander Graf <agraf@suse.de> Tested-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Baruch Siach 提交于
This makes the network devices usable when booting a blank board over UART, with no pre-configured MAC address stored in the environment area. Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Igal Liberman 提交于
Currently, ATU (address translation unit) implementation doesn't support translate addresses > 32 bits. This patch allows to configure ATU correctly for different memory accesses (memory, configuration and IO). The same approach is used in Linux Kernel. Signed-off-by: NIgal Liberman <igall@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ivan Gorinov 提交于
On x86 platforms, U-Boot does not pass Device Tree data to the kernel. This prevents the kernel from using FDT loaded by U-Boot. Read the working FDT address from the "fdtaddr" environment variable and add a copy of the FDT data to the kernel setup_data list. Signed-off-by: NIvan Gorinov <ivan.gorinov@intel.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> [bmeng: add #include <linux/libfdt.h> to zimage.c to fix build error] Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bernhard Messerklinger 提交于
Use dm_pci_map_bar function for BAR mapping. This has the advantage of clearing BAR flags and and only accepting mapped memory. Signed-off-by: NBernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: NHannes Schmelzer <hannes.schmelzer@br-automation.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
It makes no sense to set a PCI region that has 0 size. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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