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  1. 08 10月, 2013 1 次提交
  3. 07 10月, 2013 4 次提交
  5. 04 10月, 2013 7 次提交
    • A
      ARM: VExpress: enable ARMv7 virt support for VExpress A15 · e261c83a
      由 Andre Przywara 提交于 
      To enable hypervisors utilizing the ARMv7 virtualization extension
on the Versatile Express board with the A15 core tile, we add the
required configuration variable.
Also we define the board specific smp_set_cpu_boot_addr() function to
set the start address for secondary cores in the VExpress specific
manner.
There is no need to provide a custom smp_waitloop() function here.

This also serves as an example for what to do when adding support for
new boards.
Signed-off-by: NAndre Przywara <andre.przywara@linaro.org>
      e261c83a
    • A
      ARM: extend non-secure switch to also go into HYP mode · d4296887
      由 Andre Przywara 提交于 
      For the KVM and XEN hypervisors to be usable, we need to enter the
kernel in HYP mode. Now that we already are in non-secure state,
HYP mode switching is within short reach.

While doing the non-secure switch, we have to enable the HVC
instruction and setup the HYP mode HVBAR (while still secure).

The actual switch is done by dropping back from a HYP mode handler
without actually leaving HYP mode, so we introduce a new handler
routine in our new secure exception vector table.

In the assembly switching routine we save and restore the banked LR
and SP registers around the hypercall to do the actual HYP mode
switch.

The C routine first checks whether we are in HYP mode already and
also whether the virtualization extensions are available. It also
checks whether the HYP mode switch was finally successful.
The bootm command part only calls the new function after the
non-secure switch.
Signed-off-by: NAndre Przywara <andre.przywara@linaro.org>
      d4296887
    • A
      ARM: add SMP support for non-secure switch · ba6a1698
      由 Andre Przywara 提交于 
      Currently the non-secure switch is only done for the boot processor.
To enable full SMP support, we have to switch all secondary cores
into non-secure state also.

So we add an entry point for secondary CPUs coming out of low-power
state and make sure we put them into WFI again after having switched
to non-secure state.
For this we acknowledge and EOI the wake-up IPI, then go into WFI.
Once being kicked out of it later, we sanity check that the start
address has actually been changed (since another attempt to switch
to non-secure would block the core) and jump to the new address.

The actual CPU kick is done by sending an inter-processor interrupt
via the GIC to all CPU interfaces except the requesting processor.
The secondary cores will then setup their respective GIC CPU
interface.
While this approach is pretty universal across several ARMv7 boards,
we make this function weak in case someone needs to tweak this for
a specific board.

The way of setting the secondary's start address is board specific,
but mostly different only in the actual SMP pen address, so we also
provide a weak default implementation and just depend on the proper
address to be set in the config file.
Signed-off-by: NAndre Przywara <andre.przywara@linaro.org>
      ba6a1698
    • A
      ARM: trigger non-secure state switch during bootm execution · bb975455
      由 Andre Przywara 提交于 
      To actually trigger the non-secure switch we just implemented, call
the switching routine from within the bootm command implementation.
This way we automatically enable this feature without further user
intervention.
Signed-off-by: NAndre Przywara <andre.przywara@linaro.org>
      bb975455
    • A
      ARM: add C function to switch to non-secure state · 1ef92385
      由 Andre Przywara 提交于 
      The core specific part of the work is done in the assembly routine
in nonsec_virt.S, introduced with the previous patch, but for the full
glory we need to setup the GIC distributor interface once for the
whole system, which is done in C here.
The routine is placed in arch/arm/cpu/armv7 to allow easy access from
other ARMv7 boards.

We check the availability of the security extensions first.

Since we need a safe way to access the GIC, we use the PERIPHBASE
registers on Cortex-A15 and A7 CPUs and do some sanity checks.
Boards not implementing the CBAR can override this value via a
configuration file variable.

Then we actually do the GIC enablement:
a) enable the GIC distributor, both for non-secure and secure state
   (GICD_CTLR[1:0] = 11b)
b) allow all interrupts to be handled from non-secure state
   (GICD_IGROUPRn = 0xFFFFFFFF)

The core specific GIC setup is then done in the assembly routine.
Signed-off-by: NAndre Przywara <andre.przywara@linaro.org>
      1ef92385
    • A
      ARM: add assembly routine to switch to non-secure state · 16212b59
      由 Andre Przywara 提交于 
      While actually switching to non-secure state is one thing, another
part of this process is to make sure that we still have full access
to the interrupt controller (GIC).
The GIC is fully aware of secure vs. non-secure state, some
registers are banked, others may be configured to be accessible from
secure state only.
To be as generic as possible, we get the GIC memory mapped address
based on the PERIPHBASE value in the CBAR register. Since this
register is not architecturally defined, we check the MIDR before to
be from an A15 or A7.
For CPUs not having the CBAR or boards with wrong information herein
we allow providing the base address as a configuration variable.

Now that we know the GIC address, we:
a) allow private interrupts to be delivered to the core
   (GICD_IGROUPR0 = 0xFFFFFFFF)
b) enable the CPU interface (GICC_CTLR[0] = 1)
c) set the priority filter to allow non-secure interrupts
   (GICC_PMR = 0xFF)

Also we allow access to all coprocessor interfaces from non-secure
state by writing the appropriate bits in the NSACR register.

The generic timer base frequency register is only accessible from
secure state, so we have to program it now. Actually this should be
done from primary firmware before, but some boards seems to omit
this, so if needed we do this here with a board specific value.
The Versatile Express board does not need this, so we remove the
frequency from the configuration file here.

After having switched to non-secure state, we also enable the
non-secure GIC CPU interface, since this register is banked.

Since we need to call this routine also directly from the smp_pen
later (where we don't have any stack), we can only use caller saved
registers r0-r3 and r12 to not mess with the compiler.
Signed-off-by: NAndre Przywara <andre.przywara@linaro.org>
      16212b59
    • A
      ARM: add secure monitor handler to switch to non-secure state · 45b940d6
      由 Andre Przywara 提交于 
      A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state first.
Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine
which switches the CPU to non-secure state by setting the NS and
associated bits.
According to the ARM architecture reference manual this should not be
done in SVC mode, so we have to setup a SMC handler for this.
We create a new vector table to avoid interference with other boards.
The MVBAR register will be programmed later just before the smc call.
Signed-off-by: NAndre Przywara <andre.przywara@linaro.org>
      45b940d6
  7. 03 10月, 2013 1 次提交
  9. 02 10月, 2013 2 次提交
  11. 27 9月, 2013 6 次提交
  13. 24 9月, 2013 2 次提交
    • J
      README: update ARM register usage · 12eba1b4
      由 Jeroen Hofstee 提交于 
      Besides the change of this patchset it also updates the
README to reflect that GOT-generated relocations are no
longer supported on ARM.

cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
      12eba1b4
    • J
      ARM: use r9 for gd · fe1378a9
      由 Jeroen Hofstee 提交于 
      To be more EABI compliant and as a preparation for building
with clang, use the platform-specific r9 register for gd
instead of r8.

note: The FIQ is not updated since it is not used in u-boot,
and under discussion for the time being.

The following checkpatch warning is ignored:
WARNING: Use of volatile is usually wrong: see
Documentation/volatile-considered-harmful.txt
Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
      fe1378a9
  15. 23 9月, 2013 4 次提交
  17. 21 9月, 2013 6 次提交
  19. 20 9月, 2013 7 次提交