- 13 1月, 2014 4 次提交
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This patch added support for accessing dual memories in parallel connection with single chipselect line from controller. For more info - see doc/SPI/README.dual-flash Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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This patch added support for accessing dual memories in stacked connection with single chipselect line from controller. For more info - see doc/SPI/README.dual-flash Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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Unified the bar code from read_ops into a spi_flash_bar() Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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- comment typo's - func args have a proper names Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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- 11 1月, 2014 14 次提交
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QEB code comprises of couple of flash register read/write operations, this patch moved flash register operations on to sf_op Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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Added macronix flash quad read/write commands support and it's up to the respective controller driver usecase to configure the respective commands by defining SPI RX/TX operation modes from include/spi.h on the driver. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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This patch adds set QEB support for macronix flash devices which are trying to program/read quad operations. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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Discovered the read dummy_byte based on the configured read command. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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This patch adds support QUAD_IO_FAST read command. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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Moved the flash params table from sf_probe.c and placed on to sf_params.c, hence flash params file will alter based on new addons. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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This patch enabled RD_FULL and WR_QPP for supported flashes in micron, winbond and spansion. Remaining parts will be add in future patches. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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This patch provides support to set the quad enable bit on flash. quad enable bit needs to set before performing any quad IO operations on respective SPI flashes. Currently added set quad enable bit for winbond and spansion flash devices. stmicro flash doesn't require to set as qeb is volatile. remaining flash devices support will add in future patches. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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This patch provides support to program a flash config register. Configuration register contains the control bits used to configure the different configurations and security features of a device. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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This patch add quad commands support like - QUAD_PAGE_PROGRAM => for write program - QUAD_OUTPUT_FAST ->> for read program Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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Current sf uses FAST_READ command, this patch adds support to use the different/extended read command. This implementation will determine the fastest command by taking the supported commands from the flash and the controller, controller is always been a priority. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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由 Axel Lin 提交于
We have a sh_spi_clear_bit() function, there's no reason not to use it. Signed-off-by: NAxel Lin <axel.lin@ingics.com> Acked-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org> Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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由 Simon Glass 提交于
Add map_sysmem() calls so that this test works correctly on sandbox. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NHung-ying Tyan <tyanh@chromium.org> Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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由 Kuo-Jung Su 提交于
The Faraday FTSSP010 is a multi-function controller which supports I2S/SPI/SSP/AC97/SPDIF. However This patch implements only the SPI mode. NOTE: The DMA and CS/Clock control logic has been altered since hardware revision 1.19.0. So this patch would first detects the revision id of the underlying chip, and then switch to the corresponding software control routines. Signed-off-by: NKuo-Jung Su <dantesu@faraday-tech.com> Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com> CC: Tom Rini <trini@ti.com>
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- 10 1月, 2014 22 次提交
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git://git.denx.de/u-boot-arm由 Tom Rini 提交于
Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be added to include/configs/exynos5-dt.h now. Conflicts: include/configs/exynos5250-dt.h Signed-off-by: NTom Rini <trini@ti.com>
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Updated doc/README.zynq to current status Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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Enabled default dts files on respective pre-board config files this is way MAKEALL will works. and it's upto user to build specific dts by specifying at build time. $ make zynq_zc70x_config $ make --> with default dts zynq-zc702.dts or $ make DEVICE_TREE=zynq-zc702 --> Same configuration with zynq-zc706.dts Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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This patch adds initial dts support for supported zynq boards. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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CONFIG_FIT_SIGNATURE - signature node support in FIT image CONFIG_RSA - RSA lib support Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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GPIO dummy routines are required for fdt build, may be removed these dependencies once the u-boot fdt is fully optimized. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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This patch provides a basic fdt support for zynq u-boot. zynq-7000.dtsi-> initial arch dts file zynq-zed.dts -> initial zed board dts file more devices should be added in subsequent patches. u-boot build: once configuring of a board done for building dtb with zynq-zed.dts as an input zynq-uboot> make DEVICE_TREE=zynq-zed Enabled CONFIG_OF_SEPARATE for building dtb separately. There is a new binary called u-boot-dtb.bin which is a u-boot with devicetree supported. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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Defined CONFIG_ENV_OVERWRITE, which allow to overwrite serial baudrate and ethaddr. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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Last 128Kb sector of 1Mb flash is defined as u-boot environment partition. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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Changed Env. Sector size from 0x10000 to 128Kb Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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Defined default env. for autoboot FIT image from respective boot devices. Default settings: fit_image=fit.itb load_addr=0x2000000 fit_size=0x800000 flash_off=0x100000 nor_flash_off=0xE2100000 Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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Added support to find the bootmodes by reading slcr bootmode register. this can be helpful to autoboot the configurations w.r.t a specified bootmode. Added this functionality on board_late_init as it's not needed for normal initializtion part. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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ZC770 is a complete development board based on the Xilinx Zynq-7000 All Programmable SoC, similar to ZC70x board but which has four different daughter cards, like XM010, XM011, XM012 and XM013 ZC770 XM012: - 1GB DDR3 - 64MiB Numonyx NOR flash - USB-UART Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com> Cc: Stefan Roese <sr@denx.de>
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ZC770 is a complete development board based on the Xilinx Zynq-7000 All Programmable SoC, similar to ZC70x board but which has four different daughter cards, like XM010, XM011, XM012 and XM013 ZC770 XM013: - 1GB DDR3 - 128 Mb Quad-SPI Flash(dual parallel) - USB-UART Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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ZC770 is a complete development board based on the Xilinx Zynq-7000 All Programmable SoC, similar to ZC70x board but which has four different daughter cards, like XM010, XM011, XM012 and XM013 ZC770 XM010: - 1Gb DDR3 - 1Mb SST SPI flash - 128 Mb Quad-SPI Flash - 8 Mb SST SI flash - Full size SD/MMC card cage - 10/100/1000 Ethernet - USB-UART Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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MicroZed is a low-cost development board based on the Xilinx Zynq-7000 All Programmable SoC. APSOC: - XC7Z010-1CLG400C Memory: - 1 GB of DDR3 SDRAM - 128Mb of QSPI flash(S25FL128SAGBHI200) - Micro SD card interface Communication: - 10/100/1000 Ethernet - USB 2.0 - USB-UART User I/O: - 100 User I/O (50 per connector) - Configurable as up to 48 LVDS pairs or 100 single-ended I/O Misc: - Xilinx PC4 JTAG configuration port - PS JTAG pins accessible via Pmod - 33.33 MHz oscillator - User LED and push switch For more info - http://zedboard.org/product/microzedSigned-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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Adds configurations for Catalyst 24WC08 EEPROM, which is present on the zynq boards. Enable EEPROM support for zc70x boards. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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Defined TEXT_BASE for u-boot starts from 0x4000000 w.r.t zynq memory-map. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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CONFIG_SYS_SDRAM_SIZE is specific to a board hence moved to specific pre-config board files. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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Zed is a complete development board based on the Xilinx Zynq-7000 All Programmable SoC. APSOC: - XC7Z020-CLG484-1 Memory: - 512 MB DDR3 - 256 Mb Quad-SPI Flash( - Full size SD/MMC card cage Connectivity: - 10/100/1000 Ethernet - USB OTG (Device/Host/OTG) - USB-UART Expansion: - FMC (Low Pin Count) - Pmod. headers (2x6) Video/Display: - HDMI output (1080p60 + audio) - VGA connector - 128 x 32 OLED - User LEDs (9) User inputs: - Slide switches (8) - Push button switches (7) Audio: - 24-bit stereo audio CODEC - Stereo line in/out - Headphone - Microphone input Analog: - Xilinx XADC header - Supports 4 analog inputs - 2 Differential / 4 Single-ended Debug: - On-board USB JTAG programming port - ARM Debug Access Port (DAP) For more info - http://zedboard.org/product/zedboardSigned-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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The Zynq-7000 APSOC zc702 and zc706 enabled complte embedded processing includes ASIC and FPGA design. ZC702-: APSOC: - XC7Z020-CLG484-1 Memory: - DDR3 Component Memory 1GB - 16MB Quad SPI Flash - IIC - 1 KB EEPROM Connectivity: - Gigabit Ethernet GMII, RGMII and SGMII. - USB OTG - Host USB - IIC Bus Headers/HUB - 1 CAN with Wake on CAN - USB-UART Video/Display: - HDMI Video OUT - 8X LEDs Control & I/O: - 3 User Push Buttons - 2 User Switches - 8 User LEDs For more info on zc702 board: - http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm ZC706-: APSOC: - XC7Z045 FFG900 -2 AP SoC Memory: - DDR3 Component Memory 1GB (PS) - DDR3 SODIM Memory 1GB (PL) - 2X16MB Quad SPI Flash (dual parallel) - IIC - 1 KB EEPROM Connectivity: - PCIe Gen2x4 - SFP+ and SMA Pairs - GigE RGMII Ethernet (PS) - USB OTG 1 (PS) - Host USB - IIC Bus Headers/HUB (PS) - 1 CAN with Wake on CAN (PS) - USB-UART Video/Display: - HDMI 8 color RGB 4.4.4 1080P-60 OUT - HDMI IN 8 color RGB 4.4.4 Control & I/O: - 2 User Push Buttons/Dip Switch, 2 User LEDs - IIC access to GPIO - SDIO (SD Card slot) - 3 User Push Buttons, 2 User Switches, 8 User LEDs For more info on zc706 board: - http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htmSigned-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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Information on zynq u-boot about - zynq boards - mainline status - TODO Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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