Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL.
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL.
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL.
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Import the dts file from Linux 4.17 and enable CONFIG_OF_CONTROL.
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL.
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Without this USB3 won't work in U-Boot.
Signed-off-by: NMarek Behun <marek.behun@nic.cz>
Reviewed-by: NStefan Roese <sr@denx.de>
Signed-off-by: NStefan Roese <sr@denx.de>

Add FIT data-position & data-offset property support for bootm,
which were already supported in SPL.
Signed-off-by: NKelvin Cheung <keguang.zhang@gmail.com>

Follow implementation in mALLOc(). Check GD_FLG_FULL_MALLOC_INIT flag and use
malloc_simple if GD_FLG_FULL_MALLOC_INIT is unset. Adjust the malloc bytes
to align with the requested alignment.

The original memalign() function will access mchunkptr struct to adjust the
alignment if there is misalignment happen, but mchunkptr struct is not being
initialized before full malloc is initialized. This cause the system crash.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: NMarek Vasut <marek.vasut@gmail.com>

SDMMC_CMD_CPSMEN bit is wrongly check and set in
SDMMC_ARG register instead of SDMMC_CMD register.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

Use OTP57 and 58 for MAC address
- OTP57 = MAC address  bits [31:0]
- OTP58 = MAC address  bit  [47:32] stored in OTP  LSB's

Use manufacture information in OTP13 to OTP15 to build unique
chip id saved in env variable "serial#"
(used for USB device enumeration)
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

Add support of fuse command (read/write/program/sense)
on bank 0 to access to BSEC SAFMEM (4096 OTP bits).
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

Add a MISC driver with read and write access to BSEC IP
(Boot and Security and OTP control)
- offset 0: shadowed values
- offset 0x80000000: OTP fuse box values (SAFMEM)
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

The register TAMP_BOOT_CONTEXT is already updated in
get_bootmode() in cpu.c and no need to be done
twice.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

Add the needed information to enable the debug uart
to have printf before the serial driver probe
(so before probe for clock, pincontrol and reset drivers)

To enable the debug on uart 4 (default console):
+ CONFIG_DEBUG_UART=y
+ CONFIG_DEBUG_UART_STM32=y
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

Add possibility to update the serial parity used.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

Implements serial setparity ops to allow uart parity change.
It allows to select ODD, EVEN or NONE parity.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

Rename USART_ISR_FLAG_xxx bits to USART_ISR_xxx bits and
USART_ICR_OREF to USART_ICR_ORECF in order to match datasheets.
Sort defines by descendant order.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add support for early debug printf, before the availability of
driver model and device tree support.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

- adds reading FMC swap setting from DTB to SDRAM driver
- sets FMC swap for stm32f429-disco board
- changes ram start address to 0x90000000
Signed-off-by: NRadoslaw Pietrzyk <radoslaw.pietrzyk@gmail.com>
Acked-by: NPatrice Chotard <patrice.chotard@st.com>

Serial port configuration was missing from previous implementation.
It only worked because it was preconfigured by LK.
This patch configures the uart for 115200 8N1.
It also configures the pin mux for uart pins using DT bindings.
Signed-off-by: NRamon Fried <ramon.fried@gmail.com>

Added TLMM pinctrl node for pin muxing & config.
Additionally, added a serial node for uart.
Signed-off-by: NRamon Fried <ramon.fried@gmail.com>

This patch adds pinmux and pinctrl driver for TLMM
subsystem in snapdragon chipsets.
Currently, supporting only 8016, but implementation is
generic and 8096 can be added easily.

Driver is using the generic dt-bindings and doesn't
introduce any new bindings (yet).
Signed-off-by: NRamon Fried <ramon.fried@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.
Signed-off-by: NRamon Fried <ramon.fried@gmail.com>

The uart is already initialized prior to relocation,
reinitialization after relocation is unnecessary.
Signed-off-by: NRamon Fried <ramon.fried@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Failure to set the clocks will causes data abort exception when
trying to write to AHB uart registers.
This patch ensures that we don't touch these registers if clock
setting failed.
Signed-off-by: NRamon Fried <ramon.fried@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The clock and serial nodes are needed before relocation.
This patch ensures that the msm-serial driver will probe
and provide uart output before relocation.
Signed-off-by: NRamon Fried <ramon.fried@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Now that there are more boards defining this it can be removed from the
whitelist.
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add a doc comment for pciauto_region_allocate().
Signed-off-by: NTuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Currently, if we happen to allocate an address requiring 64 bits to a
device only supporting 32-bit BARs, the address eventually gets silently
truncated to 32 bits. Avoid this by adding a new flag to
pciauto_region_allocate() to bail out in such situations.
Signed-off-by: NTuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: NSimon Glass <sjg@chromium.org>

All of the debug output from this file is squished to one line. Fix
it.
Signed-off-by: NTuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Now that U-Boot works fine with highmem enabled, there is no need to
tell users to disable highmem.
Signed-off-by: NTuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Now that PCI devices work with highmem-enabled QEMU emulation, bump up
the RAM size in the MMU tables to gain access to the full 255 GB of RAM
potential instead of the puny 3 GB.
Signed-off-by: NTuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Currently, qemu_arm_defconfig and qemu_arm64_defconfig only work with
the 'highmem=off' parameter passed to QEMU's virt machine. The reason is
that when 'highmem' is not disabled, QEMU appends 64-bit a memory
resource to the PCI controller's regions property in DT in addition to
the 32-bit PCI memory window in low memory. And the current DT parsing
code picks the last (thus the 64-bit one) memory resource, whose address
eventually gets silently truncated to 32 bits because
CONFIG_SYS_PCI_64BIT is not set, which obviously causes PCI to break.

Avoid this problem by ignoring memory regions whose addresses are above
the 32-bit boundary when CONFIG_SYS_PCI_64BIT is not set.
Signed-off-by: NTuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Enable the Sandbox TPMv2 driver in all possible configurations.
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>

This node declares the presence of the Sandbox TPMv2.x emulated chip,
available for testing.
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>

Add Sandbox TPMv2.0 module bindings.
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>

This driver can emulate all the basic functionalities of a TPMv2.x
chip and should behave like them during regular testing.
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>

Add tests for the TPMv2.x commands.
These commands may run both on a physical TPM and with the sandbox
driver.
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>

Add TIS TPMv2.0 SPI module bindings.
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>

On some designs, the reset line could not be connected to the SoC reset
line, in this case, request the GPIO and ensure the chip gets reset.
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>