- 01 6月, 2018 21 次提交
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由 Takeshi Kihara 提交于
Basic support for the Renesas Ebisu board based on R-Car E3: - Memory, - Main crystal, - Serial console, Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> [shimoda: rebase and add SPDX-License-Identifier] Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Yoshihiro Shimoda 提交于
This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC: - PSCI - CPU (single) - Cache controller - Main clocks and controller - Interrupt controller - Timer - PMU - Reset controller - Product register - System controller - UART for console Inspried by a patch by Takeshi Kihara in the BSP. Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add ID and Kconfig entry for the Renesas R8A77990 E3 SoC. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add new compatible to the Ethernet AVB driver for R8A77990 E3 SoC. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add new compatible to the Uniphier SD driver for R8A77990 E3 SoC. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add new compatible to the GPIO driver for R8A77990 E3 SoC. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
This patch adds initial pinctrl driver to support for the R8A77990 SoC. Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Takeshi Kihara 提交于
This follows the style of existion PORT_GP_X macros and will be used by a follow-up patch for the r8a77990 SoC. Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add clock tables for R8A77990 E3 SoC . Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
The PE clock have two parents, add support for picking the correct one and deriving the clock from it. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add and use the PLL1 and PLL3 dividers. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
The PLL rate could be in the GHz range, which could overflow a 32bit data type. Since the hardware is 64bit anyway, pass the clock rates as 64bit number internally to avoid this. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
The mul and div arguments were reported in reverse order in the debug message, swap them to fix this. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add mtdparts description for the board. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add mtdparts description for the board. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add mtdparts description for the board. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add mtdparts description for the board. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add mtdparts description for the board. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add mtdparts description for the board. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add mtdparts description for the board. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Enable MTD partitioning support on Gen2 boards with SPI NORs. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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- 27 5月, 2018 19 次提交
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由 Kelvin Cheung 提交于
Add FIT data-position & data-offset property support for bootm, which were already supported in SPL. Signed-off-by: NKelvin Cheung <keguang.zhang@gmail.com>
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由 Ley Foon Tan 提交于
Follow implementation in mALLOc(). Check GD_FLG_FULL_MALLOC_INIT flag and use malloc_simple if GD_FLG_FULL_MALLOC_INIT is unset. Adjust the malloc bytes to align with the requested alignment. The original memalign() function will access mchunkptr struct to adjust the alignment if there is misalignment happen, but mchunkptr struct is not being initialized before full malloc is initialized. This cause the system crash. Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com> Reviewed-by: NMarek Vasut <marek.vasut@gmail.com>
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由 Patrice Chotard 提交于
SDMMC_CMD_CPSMEN bit is wrongly check and set in SDMMC_ARG register instead of SDMMC_CMD register. Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
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由 Patrick Delaunay 提交于
Use OTP57 and 58 for MAC address - OTP57 = MAC address bits [31:0] - OTP58 = MAC address bit [47:32] stored in OTP LSB's Use manufacture information in OTP13 to OTP15 to build unique chip id saved in env variable "serial#" (used for USB device enumeration) Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
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由 Patrick Delaunay 提交于
Add support of fuse command (read/write/program/sense) on bank 0 to access to BSEC SAFMEM (4096 OTP bits). Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
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由 Patrick Delaunay 提交于
Add a MISC driver with read and write access to BSEC IP (Boot and Security and OTP control) - offset 0: shadowed values - offset 0x80000000: OTP fuse box values (SAFMEM) Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
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由 Patrick Delaunay 提交于
The register TAMP_BOOT_CONTEXT is already updated in get_bootmode() in cpu.c and no need to be done twice. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
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由 Patrick Delaunay 提交于
Add the needed information to enable the debug uart to have printf before the serial driver probe (so before probe for clock, pincontrol and reset drivers) To enable the debug on uart 4 (default console): + CONFIG_DEBUG_UART=y + CONFIG_DEBUG_UART_STM32=y Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
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由 Patrick Delaunay 提交于
Add possibility to update the serial parity used. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
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由 Patrick Delaunay 提交于
Implements serial setparity ops to allow uart parity change. It allows to select ODD, EVEN or NONE parity. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
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由 Patrice Chotard 提交于
Rename USART_ISR_FLAG_xxx bits to USART_ISR_xxx bits and USART_ICR_OREF to USART_ICR_ORECF in order to match datasheets. Sort defines by descendant order. Signed-off-by: NPatrice Chotard <patrice.chotard@st.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Patrick Delaunay 提交于
Add support for early debug printf, before the availability of driver model and device tree support. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Signed-off-by: NPatrice Chotard <patrice.chotard@st.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Radoslaw Pietrzyk 提交于
- adds reading FMC swap setting from DTB to SDRAM driver - sets FMC swap for stm32f429-disco board - changes ram start address to 0x90000000 Signed-off-by: NRadoslaw Pietrzyk <radoslaw.pietrzyk@gmail.com> Acked-by: NPatrice Chotard <patrice.chotard@st.com>
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由 Ramon Fried 提交于
Serial port configuration was missing from previous implementation. It only worked because it was preconfigured by LK. This patch configures the uart for 115200 8N1. It also configures the pin mux for uart pins using DT bindings. Signed-off-by: NRamon Fried <ramon.fried@gmail.com>
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由 Ramon Fried 提交于
Added TLMM pinctrl node for pin muxing & config. Additionally, added a serial node for uart. Signed-off-by: NRamon Fried <ramon.fried@gmail.com>
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由 Ramon Fried 提交于
This patch adds pinmux and pinctrl driver for TLMM subsystem in snapdragon chipsets. Currently, supporting only 8016, but implementation is generic and 8096 can be added easily. Driver is using the generic dt-bindings and doesn't introduce any new bindings (yet). Signed-off-by: NRamon Fried <ramon.fried@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Ramon Fried 提交于
UART clock enabling flow was wrong. Changed the flow according to downstream implementation in LK. Signed-off-by: NRamon Fried <ramon.fried@gmail.com>
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由 Ramon Fried 提交于
The uart is already initialized prior to relocation, reinitialization after relocation is unnecessary. Signed-off-by: NRamon Fried <ramon.fried@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Ramon Fried 提交于
Failure to set the clocks will causes data abort exception when trying to write to AHB uart registers. This patch ensures that we don't touch these registers if clock setting failed. Signed-off-by: NRamon Fried <ramon.fried@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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