- 19 5月, 2020 1 次提交
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由 Simon Glass 提交于
Move this uncommon header out of the common header. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 23 1月, 2020 1 次提交
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由 Holger Brunck 提交于
This patch moves the qrio and i2c deblocking code to keymile/common as it will also be used by the upcoming CENT2 board. Signed-off-by: NHolger Brunck <holger.brunck@ch.abb.com> CC: Priyanka Jain <priyanka.jain@nxp.com>
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- 03 12月, 2019 1 次提交
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由 Simon Glass 提交于
This function can be dropped when all boards use driver model for PCI. For now, move it into init.h with a comment. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NTom Rini <trini@konsulko.com>
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- 07 5月, 2018 1 次提交
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由 Tom Rini 提交于
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: NTom Rini <trini@konsulko.com>
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- 05 3月, 2018 1 次提交
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由 Masahiro Yamada 提交于
Thomas reported U-Boot failed to build host tools if libfdt-devel package is installed because tools include libfdt headers from /usr/include/ instead of using internal ones. This commit moves the header code: include/libfdt.h -> include/linux/libfdt.h include/libfdt_env.h -> include/linux/libfdt_env.h and replaces include directives: #include <libfdt.h> -> #include <linux/libfdt.h> #include <libfdt_env.h> -> #include <linux/libfdt_env.h> Reported-by: NThomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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- 24 9月, 2016 1 次提交
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由 Masahiro Yamada 提交于
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: NTom Rini <trini@konsulko.com>
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- 13 5月, 2014 1 次提交
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由 Valentin Longchamp 提交于
This adds the reset support for the following devices that was until then not implemented: - BFTIC4 - QSFPs This also fixes the configuration of the prst behaviour for the other resets: Only the u-boot and kernel relevant subsystems are taken out of reset (pcie, ZL30158, and front eth phy). Most of the prst config move to misc_init_f(), except for the PCIe related ones that are in pci_init_board and the bftic and ZL30158 ones that should be done as soon as possible. Only the behavior of the Hooper reset is changed according to the documentation as the application is not able to not configure the switch when it is not reset. Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
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- 04 2月, 2014 1 次提交
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由 Valentin Longchamp 提交于
The PEXHC PCIe configuration mechanism ensures that the FPGA get configured at power-up. Since all the PCIe devices should be configured when the kernel start, u-boot has to take care that the FPGA gets configured also in other reset scenarios, mostly because of possible configuration change. The used mechanism is taken from the km_kirkwood design and adapted to the kmp204x case (slightly different HW and PCIe configuration). Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 25 10月, 2013 1 次提交
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由 Valentin Longchamp 提交于
This patch introduces the support for Keymile's kmp204x reference design. This design is based on Freescale's P2040/P2041 SoC. The peripherals used by this design are: - DDR3 RAM with SPD support - SPI NOR Flash as boot medium - NAND Flash - 2 PCIe busses (hosts 1 and 3) - 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5) - 3 Local Bus windows, with one dedicated to the QRIO reset/power mgmt FPGA - 2 HW I2C busses - last but not least, the mandatory serial port The board/keymile/kmp204x code is mostly based on Freescale's P2041rdb support and was changed according to our design (that means essentially removing what is not present on the designs and a few adaptations). There is currently only one prototype board that is based on this design and this patch also introduces it. The board is called kmlion1. Signed-off-by: NStefan Bigler <stefan.bigler@keymile.com> Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com> kmp204x: update the ENV #define The comments had to be refined as well as the total size Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix ddr.c] Acked-by: NYork Sun <yorksun@freescale.com>
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- 24 7月, 2013 1 次提交
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: NTom Rini <trini@ti.com>
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- 30 9月, 2011 1 次提交
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由 Kumar Gala 提交于
We currently support 4 SoC/Boards from the P-Series of QorIQ SoCs that are based on the 'CoreNet' Architecture: P2041RDB, P3041DS, P4080DS, and P5020DS. There is a significant amount of commonality shared between these boards that we can refactor into common code: * Initial LAW setup * Initial TLB setup * PCI setup We start by moving the shared code between P3041DS, P4080DS, and P5020DS into a common directory to be shared with other P-Series CoreNet boards. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 14 1月, 2011 1 次提交
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由 Kumar Gala 提交于
Remove duplicated code in corenet_ds boards and utilize the common fsl_pcie_init_board(). Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 15 11月, 2010 1 次提交
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由 Peter Tyser 提交于
Previously boards used a variety of indentations, newline styles, and colon styles for the PCI information that is printed on bootup. This patch unifies the style to look like: ... NAND: 1024 MiB PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d In: serial ... Signed-off-by: NPeter Tyser <ptyser@xes-inc.com> CC: wd@denx.de CC: sr@denx.de CC: galak@kernel.crashing.org
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- 07 10月, 2010 1 次提交
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由 Kumar Gala 提交于
We configure the controller but dont have virtual address space thus any devices on the 4th controller are not accessible in u-boot. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 02 8月, 2010 1 次提交
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由 Kumar Gala 提交于
Add support for the P4080DS board, with the following features: * 36-bit only * Boots from NOR flash * FMAN drivers NOT supported * SPD DDR initialization Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com> Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org> Signed-off-by: NAshish Kalra <Ashish.Kalra@freescale.com> Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com> Signed-off-by: NDave Liu <daveliu@freescale.com> Signed-off-by: NLan Chunhe-B25806 <b25806@freescale.com> Signed-off-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com> Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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