Add a test item for the phy_bulk API
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: NFrank Wunderlich <frank-w@public-files.de>
Reviewed-by: NWeijie Gao <weijie.gao@mediatek.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>

This patch adds a "bulk" API to the phy API in order to
get/init/exit/power on/off a group of phys associated
with a device.

The bulk API will avoid adding a copy of the same code to
manage a group of phys in drivers.
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: NFrank Wunderlich <frank-w@public-files.de>
Reviewed-by: NWeijie Gao <weijie.gao@mediatek.com>
Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>

Add a test item for ofnode_get_child_count()
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: NFrank Wunderlich <frank-w@public-files.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWeijie Gao <weijie.gao@mediatek.com>

This patch add function used to get the child count of
a ofnode or a device
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: NFrank Wunderlich <frank-w@public-files.de>
Reviewed-by: NWeijie Gao <weijie.gao@mediatek.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

- Assorted bug fixes
- Framework for enabling D-CACHE in SPL on ARM

Out documentation directory is doc/ and not docs/.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

The correct syntax is 'select SYS_...' and not 'select CONFIG_SYS...'

Fixes: d5c819b8 ("actions: Move defconfig options to Kconfig")
Signed-off-by: NTom Rini <trini@konsulko.com>

Drop initr_bedbug wrapper and call bedbug_init directly during the init
sequence.
Signed-off-by: NOvidiu Panait <ovpanait@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Do this as a preparation for removing initr_bedbug wrapper from
common/board_r.c.
Signed-off-by: NOvidiu Panait <ovpanait@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

initr_enable_interrupts() is an ARM-specific wrapper over
enable_interrupts(), which is run during the common init sequence. It can
be eliminated by moving the enable_interrupts() call to the end of
interrupt_init() function, in arch/arm/lib/interrupts*.c.
Signed-off-by: NOvidiu Panait <ovpanait@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Malloc gets initialized with a call to mem_malloc_init() with the address
the allocation starts to and its size. Currently it is not possible to
move the malloc from one memory area to another as the malloc would eventually
fail.

This patch adds in the ability to re-init the malloc with the updated
start address and the size.

One of the use cases of this feature is SPL U-Boot running from within
the static memory and calling to malloc init from within board_init_f():

	arch/arm/cpu/armv8/start.S:reset vector
	arch/arm/cpu/armv8/start.S:main()
	arch/arm/lib/crt0_64.S:board_init_f()
	board/<my_board>/common/spl.c:board_init_f()
        board/<my_board>/common/spl.c:mem_malloc_init((ulong)CONFIG_SYS_SPL_MALLOC_START,
                        CONFIG_SYS_SPL_MALLOC_SIZE);

Shortly after the DDR (main) memory is init and ready we call to malloc init
again but this time with the start address in the DDR memory and a much greater
size for moving the allocation off the static to the DDR memory:

	board/<my_board>/common/spl.c:mem_malloc_init((ulong)CONFIG_SPL_MALLOC_OFFSET,
			CONFIG_SPL_MALLOC_SIZE);

Where CONFIG_SYS_SPL_MALLOC_START and CONFIG_SPL_MALLOC_OFFSET are the start
addresses of the malloc in the static and DDR memories respectively and
CONFIG_SYS_SPL_MALLOC_SIZE=SZ_16K and CONFIG_SPL_MALLOC_SIZE=SZ_2M are
the sizes of the mallocs in these memories. Note, now we have a much greater
memory, enlarging from 16K to 2M, available for allocation.

There is an alternative approach already existing in U-Boot with the use of
an early (simplified) malloc and the proper (dlamalloc) malloc however
necessitating managing the two mallocs whereas this approach proposes using
a single dlmalloc.
Signed-off-by: NMarek Bykowski <marek.bykowski@gmail.com>

The signature check on config node is broken on fit with padding.
To compute the signature for config node, U-Boot compute the
signature on all properties of requested node for this config,
except for the property "data". But, when padding is used for
binary in a fit, there isn't a property "data" but two properties:
"data-offset" and "data-size". So to fix the check of signature,
we also don't use the properties "data-offset" and "data-size"
when checking the signature on config node.
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NPhilippe Reynes <philippe.reynes@softathome.com>

The pytest vboot does all his tests on fit without padding.
We add the same tests on fit with padding.
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NPhilippe Reynes <philippe.reynes@softathome.com>

free() checks if its argument is NULL. Don't duplicate this in the calling
code.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>

free() checks if its argument is NULL. Don't duplicate this in the calling
code.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

free() checks if its argument is NULL. Do not duplicate this in the calling
code.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NTom Rini <trini@konsulko.com>

Signed-off-by: NSven Roederer <devel-sven@geroedel.de>

The cmdline for calling the dtc was cut-off when using long filenames (e.g.
245 bytes) for output-file and datafile of "-f" parameter.
For FIT-images cmd[MKIMAGE_MAX_DTC_CMDLINE_LEN] is declared (hardcoded 512 bytes),
and contains some static values, the path of a tmpfile and a datafile. tmpfile is
max MKIMAGE_MAX_TMPFILE_LEN (256) and datafile might be also this size. Having two
very long pathname results in a truncation os the executed shell command, as the
truncated datafile path will not be found.
Redefine MKIMAGE_MAX_DTC_CMDLINE_LEN to "2 * MKIMAGE_MAX_TMPFILE_LEN + 35 for the
parameters.
This likely applies to the "-d" parameter, too.
Signed-off-by: NSven Roederer <devel-sven@geroedel.de>

This patch enables distro boot for the bananapi-r2, based on
a MediaTek mt7623n.
Signed-off-by: NMatthias Brugger <mbrugger@suse.com>

The upstream compatible is called mt6589-wdt.
Add this compatible to the driver.
Signed-off-by: NMatthias Brugger <mbrugger@suse.com>

The timers compatible string in upstream is called
mt6577-timer. Add this compatible to the driver.
Signed-off-by: NMatthias Brugger <mbrugger@suse.com>

Provide an overview of the analysis of U-Boot crash dumps.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: NIlias Apalodimas <ilias.apalodimas@linaro.org>

As noted in rtc_def.h, the tm_mon field in struct rtc_time is 1-12,
unlike in struct tm where it is 0-11. Currently, running "date" prints
the wrong

Date: 2020-04-01 (Friday)    Time: 13:05:30

and setting the RTC via the date command is also broken.
Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>

Solved the overflow on phys_addr_t type for start + size in
mmu_set_region_dcache_behaviour() function.

This overflow is avoided by dividing start and end by 2 before addition,
and we only expecting that start and size are even.

This patch doesn't change the current function behavior if the
parameters (start or size) are not aligned on MMU_SECTION_SIZE.

For example, this overflow occurs on ARM32 with:
start = 0xC0000000 and size = 0x40000000
then start + size = 0x100000000 and end = 0x0.

For information the function behavior change with risk of regression,
if we just shift start and size before the addition.
Example with 2MB section size:
  MMU_SECTION_SIZE 0x200000 and MMU_SECTION_SHIFT = 21
  with start = 0x1000000, size = 0x1000000,
  - with the proposed patch, start = 0 and end = 0x1 as previously
  - with the more simple patch:
    end = (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT)
    the value of end change:
    start >> 21 = 0, size >> 21 = 0 and end = 0x0 !!!
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Add the new flags DCACHE_DEFAULT_OPTION to define the default
option to use according the compilation flags
CONFIG_SYS_ARM_CACHE_*.

This new compilation flag allows to simplify dram_bank_mmu_setup()
and can be used as third parameter (option=dcache option to select)
of mmu_set_region_dcache_behaviour function.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Add protection in dram_bank_mmu_setup() to avoid access to bd->bi_dram
before relocation.

This patch allow to use the generic weak function dram_bank_mmu_setup
to activate the MMU and the data cache in SPL or in U-Boot before
relocation, when bd->bi_dram is not yet initialized.

In this cases, the MMU must be initialized explicitly with
mmu_set_region_dcache_behaviour function.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Move CONFIG_SYS_ARM_CACHE_WRITETHROUGH and
CONFIG_SYS_ARM_CACHE_WRITEALLOC into Kconfig done by moveconfig.py.

Kconfig uses a choice between the 3 values supported in U-Boot,
including the new configuration CONFIG_SYS_ARM_CACHE_WRITEBACK
(the default configuration).

The patch also avoids to select simultaneously 2 configurations.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

The most basic printf("%i", value) formating string was missing,
add it for the sake of convenience.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>

- distro boot support for SPI flash
- sifive spi flash driver

Pull request for UEFI sub-system for efi-2020-07-rc2

This pull request contains bug fixes needed due to the merged changes for
EFI secure boot.

Patches are supplied to identify EFI system partitions.

HiFive Unleashed A00 support is25wp256 spi-nor flash,
So enable the same and add test result log for future
reference.

Tested on SiFive FU540 board.

Thanks to Sagar for various use cases and tests.

[QUAD mode in dt with spi-tx-bus-width: <4>]
 pp opcode      = 0x34 [QUAD MODE]
 read opcode  = 0x6c  [QUAD MODE]
 erase opcode = 0x21

SPI-NOR:
1. erase entire flash: Pass
2. write entire flash: Pass
3. read entire flash: Pass
4. cmp 32MiB read back data: Pass
5. MMC: Booted Linux and dtb from mmc

[SPI MODE in dt with spi-tx-bus-width: <1>]
pp opcode     = 0x12 [SPI MODE]
read opcode  = 0xc   [SPI MODE]
erase opcode = 0x21

SPI-NOR:
1. erase entire flash: Pass
2. write entire flash: Pass
3. read entire flash: Pass
4. cmp 32MiB read back data: Pass
5. MMC: Booted Linux and dtb from mmc
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NSagar Kadam <sagar.kadam@sifive.com>

Add U-Boot specific dts file for hifive-unleashed-a00, this
would help to add u-boot specific properties and other node
changes without touching the base dts(i) files which are easy
to sync from Linux.

Added spi2 alias for qspi2 as an initial u-boot specific
property change.

spi probing in current dm model is very much rely on aliases
numbering. Even though the qspi2 can't come under any associated
spi nor flash it would require to specify the same to make proper
binding happen for other spi slaves.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NSagar Kadam <sagar.kadam@sifive.com>

The guessed reason is that the existing logic of filling
tx fifo with data, rx fifo with NULL for tx transfer and
filling rx fifo with data, tx fifo with NULL for rx transfer
is not clear enough to support the Quad Page Program.
   
SiFive SPI controllers have specific sets of watermark
registers and SPI I/O directions bits in order to program
SPI controllers clear enough to support all sets of operating
modes.
   
Here is the exact programing sequence that would follow on this
patch and tested via SPI-NOR and MMC_SPI.
   
- set the frame format proto, endian
- set the frame format dir, set it for tx and clear it for rx
- TX transfer:
  fill tx fifo with data.
  wait for TX watermark bit to clear.
- RX transfer:
  fill tx fifo with 0xff.
  write nbytes to rx watermark register
  wait for rx watermark bit to clear.
  read the rx fifo data.

So, this patch adopts this program sequence and fixes the existing
I/O direction bit.

Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Tested-by: NSagar Kadam <sagar.kadam@sifive.com>

SiFive SPI controller has a proto bit field in frame format
register which would be used to configure the SPI I/O protocol
lines used on specific transfer. 

Right now the driver is configuring this proto using slave->mode,
for all types of transctions. This makes the driver unable to
function since the proto needs to configure dynamically for
each and every transaction separately at runtime.

Now, the controller driver supports per transfer via spi-mem
exec_opo, so add the fmt_proto flag and fill the per transfer
buswidth so that the controller configures the proto bit at
runtime.

This patch fixes the SPI controller works with SPI NOR flash
on quad read with page program.

Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Tested-by: NSagar Kadam <sagar.kadam@sifive.com>

SiFive SPI controller is responsible to handle the
slave devices like mmc spi and spi nor flash.

The controller is designed such a way that it would
handle the slave transactions based on the I/O protocol
numbers, example if spi nor slave send quad write opcode
it has to send alone with I/O protocol number of 4 and
if it try to send data it has to send I/O protocol number
along with 4 line data.

But the current spi-xfer code from spi-mem is combining
the opcode and address in a single transaction, so the
SPI controller will be unable to identify the I/O protocol
number of opcode vs address.

So, add the spi-mem exec_op with spi-xfer of opcode, address
and data as a separate transaction. This doesn't remove
the .xfer of dm_spi_ops since mmc spi will make use of it.

Note: This code might have moved to the spi-mem core area
once we have done the dedicated tests on other controllers
and have real reason to move.

Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Tested-by: NSagar Kadam <sagar.kadam@sifive.com>

Spansion "s25fs512s" flash is incorrectly decoded as "s25fl512s" on
various platforms as former is not present. Add the entry.

Linux already has both the flashes present. A snippet below:
{ "s25fl512s",  INFO6(0x010220, 0x4d0080, 256 * 1024, 256...},
{ "s25fs512s",  INFO6(0x010220, 0x4d0081, 256 * 1024, 256...},
Signed-off-by: NKuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>

Enable designware watchdog driver for rk3399 if WDT defined.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

IS25WP256 flash chips do support 4byte address opcodes,
so enable support for it.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NSagar Kadam <sagar.kadam@sifive.com>

Enable QE bit for ISSI flash chips.

QE enablement logic is similar to what Macronix
has, so reuse the existing code itself.

Cc: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

Usually variable name slave is used for spi_slave structure
and slave_plat for the dm_spi_slave_platdata.

Let's follow this meaningful notation by replacing slave
with slave_plat for dm_spi_slave_platdata structure.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>