- 14 5月, 2018 23 次提交
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由 Chris Packham 提交于
No in-tree code defines SUPPORT_STATIC_DUNIT_CONFIG or STATIC_ALGO_SUPPORT. Remove ddr3_a38x_mc_static.h and use unifdef to remove unused sections in the rest of the ddr/marvell/a38x code. Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Chris Packham 提交于
Move sys_env_device_rev_get() from the ddr training code to sys_env_lib.c (which currently resides with the serdes code). This brings sys_env_device_rev_get() into line with sys_env_device_id_get() and sys_env_model_get(). Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Chris Packham 提交于
PEX_CFG_DIRECT_ACCESS was defined in ddr3_hws_hw_training_def.h despite only being used in the serdes code. Move this definition to ctrl_pex.h where all the other PEX defines are. Also remove the duplicate definition of PEX_DEVICE_AND_VENDOR_ID which is already defined in ctrl_pex.h. Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
This adds basic support for the Turris Mox board from CZ.NIC, which is currently being crowdfunded on Indiegogo. Turris Mox is as modular router based on the Armada 3720 SOC (same as EspressoBin). The basic module can be extended by different modules. The device tree binary for the kernel can be dependent on which modules are connected, and in what order. Because of this, the board specific code creates in U-Boot a variable called module_topology, which carries this information. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
This adds support for the CPU watchdog found on Marvell Armada 37xx SoCs. There are 4 counters which can be set as CPU watchdog counters. This driver uses the second counter (ID 1, counting from 0) (Marvell's Linux also uses second counter by default). In the future it could be adapted to use other counters, with definition in the device tree. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
The driver does not check id phy_connect failed (for example on wrong property name in device tree). In such a case a fault occurs and the CPU is restarted. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
Move the reg_set* functions into comphy.h as static inline functions. Change return type of get_*_string to const char *. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
Add support for the clk dump command on Armada 37xx. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
Since now we have driver for clocks on Armada 37xx, use it to determine SQF clock frequency for the SPI driver. Also change the default config files for Armada 37xx devices so that the clock driver is enabled by default, otherwise the SPI driver cannot be enabled. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
The drivers are based on Linux driver by Gregory Clement. The TBG clocks support only the .get_rate method. - since setting rate is not supported, the driver computes the rates when probing and so subsequent calls to the .get_rate method do not read the corresponding registers again The peripheral clocks support methods .get_rate, .enable and .disable. - the .set_parent method theoretically could be supported on some clocks (the parent would have to be one of the TBG clocks) - the .set_rate method would have to try all the divider values to find the best approximation of a given rate, and it doesn't seem like this should be needed in U-Boot, therefore not implemented Signed-off-by: NMarek Behun <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
In SGMII initialization PIN_PIPE_SEL has to be zero when resetting the PHY. Since comphy_mux already set the selector register to correct values, we have to store it's value before setting it to 0 and restore it after SGMII init. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
Lane 0 supports SGMII1 and USB3. Lane 1 supports SGMII0 and PEX0. Lane 2 supports SATA0 and USB3. This is needed for Armada 37xx. This introduces new device tree bindings. AFAIK there is currently no driver for Armada 37xx comphy in Linux. When such a driver will be pushed into Linux, this will need to be rewritten accordingly. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
The register addresses on lanes 0 and 1 are switched, first comes 1 and then 0. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
Currently comphy_mux supports only trivial order of nodes in pin selector register, that is lane N on position N*bitcount. Add support for nontrivial order, with map stored in device tree property mux-lane-order. This is needed for Armada 37xx. As far as I know, there is no driver for Armada 37xx comphy in the kernel. When such a driver comes, this will need to be rewritten to support the device tree bindings from the kernel. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
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由 zachary 提交于
This commit is based on commit d9899826 by zachary <zhangzg@marvell.com> from u-boot-marvell, see github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/d9899826 - According to design specification, the transmitter should be set to high impedence mode during electrical idle. Thus transmitter should detect RX at high impedence mode also, and delay is needed to accommodate high impedence off latency. Otherwise the USB3 will have detection issue that most of the time the USB3 device can not be detected at all, or be detected as USB2 device sometimes. Modified registers: RD005C302h (R181h) (0051h) Lane Configuration 1 Bit 6: set to 1 to let Tx detect Rx at HiZ mode Bit [3:4]: set to 2 to be delayed by 2 clock cycles Bit 0: set to 1 to set transmitter to high impedance mode during idle. - USB3 De-emphasize level of -3.5dB is mandatory, but USB3 MAC selects 0x2 (emphasize disabled) in the MAC_PHY_TXDEEMPH [1:0], while it is supposed to select 0x1(3.5dB emphasize). Thus need to override what comes from the MAC(by setting register 0x1c2 bit2 to 0x1) and to configure the overridded values of MAC_PHY_TXDEEMPH [1:0] to 0x1(bit15 of register 0x181 and bit0 of register 0x180). - According to USB3 application note, need to update below comphy registers: Set max speed generation to USB3.0 5Gbps(set RD005C04Ah bit[11:10] to 1) Set capacitor value to 0xF(set RF005C224 bit[3:0] to 0xF) Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
According to specification, CFG_PM_RXDLOZ_WAIT should be set to 0x7 when reference clock is at 25 MHz. The specification (at least the version I have) does not mentoin the setting for 40 MHz reference clock, but Marvell's U-Boot sets 0xC in that case. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
When USB3 is on comphy lane 2 on the Armada 37xx, the registers have to be accessed indirectly via SATA indirect access. This is the case of the Turris Mox board from CZ.NIC. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
Create a special function for indirect register setting, reg_set_indirect, and use it instead of the two calls to reg_set. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
In U-Boot it is usually written this way. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
The timeout is set to PLL_LOCK_TIMEOUT in every call to comphy_poll_reg. Remove this parameter from the function. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
Currently there is for each register special functional macro, ie: LANE_CFG1_ADDR(u) GLOB_CLK_SRC_LO_ADDR(u) ... where can be either PCIE or USB3. Change this to one function PHY_ADDR(unit, addr). The code becomes: phy_addr(PCIE, LANE_CFG1) phy_addr(PCIE, GLOB_CLK_SRC_LO) ... Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
The macro phy_write16 is not used by the rest of the code, phy_read16 is not used at all. We also change the macro SGMIIPHY_ADDR to a static inline function. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
All the calls to reg_set and friends have to cast the first argument to void __iomem *. Lets change the return type of the MVEBU_REG macro instead. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
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- 13 5月, 2018 1 次提交
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由 Marek Vasut 提交于
Drop all the extra content from the MMC core, so that tiny MMC support is really tiny, no fancy anything. That means the tiny MMC support does only 1-bit transfers at default speed settings. Moreover, this patch drops duplicate instance of struct mmc mmc_static, which wasted about 360 bytes. Furthermore, since MMC tiny supports only one controller at all times, get rid of mallocating the ext csd backup and replace it with static array. All in all, this patch saves ~4 kiB of bloat from the MMC core, which on platforms with severe limitations can be beneficial. Signed-off-by: NMarek Vasut <marek.vasut@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> [trini: Fixup checkpatch.pl style warnings] Signed-off-by: NTom Rini <trini@konsulko.com>
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- 12 5月, 2018 2 次提交
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由 Tom Rini 提交于
Correct the SPDX tag format. Fixes: 3b52847a ("Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze") Signed-off-by: NTom Rini <trini@konsulko.com>
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- 11 5月, 2018 14 次提交
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git://www.denx.de/git/u-boot-microblaze由 Tom Rini 提交于
Xilinx changes for v2018.07 microblaze: - Align defconfig zynq: - Rework fpga initialization and cpuinfo handling zynqmp: - Add ZynqMP R5 support - Wire and enable watchdog on zcu100-revC - Setup MMU map for DDR at run time - Show board info based on DT and cleanup IDENT_STRING zynqmp tools: - Add read partition support - Add initial support for Xilinx bif format for boot.bin generation mmc: - Fix get_timer usage on 64bit cpus - Add support for SD3.0 UHS mode nand-zynq: - Add support for 16bit buswidth - Use address cycles from onfi params scsi: - convert ceva sata to UCLASS_AHCI timer: - Add Cadence TTC for ZynqMP r5 watchdog: - Minor cadence driver cleanup
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This patch enables UHS support for ZynqMP zcu102 rev 1.0 board. Signed-off-by: NSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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This patch adds support of SD3.0 for ZynqMP. Signed-off-by: NSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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This patch reads the capabilities register1 and update the host caps accordingly for mmc layer usage. This patch mainly reads for UHS capabilities inorder to support SD3.0. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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This patch adds support to invoke any platform specific tuning and delay routines if available. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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This patch adds new hooks for any platform specific tuning and tap delays programing. These are needed for supporting SD3.0. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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This patch upadted sdhci_send_command to handle execute tuning command. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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This patch adds support to disable clock if clk_disable was set and then enable or set clock if the clock was changed or clock was disabled when clock needs to be enabled. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Vipul Kumar 提交于
This patch changed the datatype of variable "start" from uint to ulong to work properly on 64-bit machines as well. Also the return type of get_timer() function is ulong. Signed-off-by: NVipul Kumar <vipul.kumar@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot. This patch is adding minimal support to get U-Boot boot. U-Boot on R5 runs out of DDR with default configuration that's why DDR needs to be partitioned if there is something else running on arm64. Console is done via Cadence uart driver and the first Cadence Triple Timer Counter is used for time. This configuration with uart1 was tested on zcu100-revC. U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200) Model: Xilinx ZynqMP R5 DRAM: 512 MiB WARNING: Caches not enabled MMC: In: serial@ff010000 Out: serial@ff010000 Err: serial@ff010000 Net: Net Initialization Skipped No ethernet found. ZynqMP r5> There are two ways how to run this on ZynqMP. 1. Run from ZynqMP arm64 tftpb 20000000 u-boot-r5.elf setenv autostart no && bootelf -p 20000000 cpu 4 disable && cpu 4 release 10000000 lockstep or cpu 4 disable && cpu 4 release 10000000 split 2. Load via jtag when directly to R5 Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Alexander Graf 提交于
The officially described way to generate boot.bin files for ZynqMP is to describe the contents of the target binary using a file of the "bif" format. This file then links to other files that all get packed into a bootable image. This patch adds support to read such a .bif file and generate a respective ZynqMP boot.bin file that can include the normal image and pmu files, but also supports image partitions now. This makes it a handy replacement for the proprietary "bootgen" utility that is currently used to generate boot.bin files with FSBL. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Alexander Graf 提交于
The zynqmpimage.c and the new zynqmpbif.c files are all maintained by Xilinx for the Zynq platforms. Let's match them accordingly in the MAINTAINERS file. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Alexander Graf 提交于
We will add support for ZynqMP bif input files later, so let's move all structure definitions into a header file that can be used by that one as well. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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