Per a request from Andre Przywara and agreed with by Peter Hoyes, the
vexpress aemv8r support wasn't quite ready to be merged, but the
discussion had moved off list.  We should keep the first patch in the
series for now, but revert the rest.  This reverts the following
commits:

e0bd6f31 doc: Add documentation for the Arm vexpress board configs
30e5a449 arm: Use armv8_switch_to_el1 env to switch to EL1
b53bbca6 vexpress64: Add BASER_FVP vexpress board variant
2f5b7b74 armv8: Add ARMv8 MPU configuration logic
37a757e2 armv8: Ensure EL1&0 VMSA is enabled
Signed-off-by: NTom Rini <trini@konsulko.com>

The prototype of psci_features() duplicated. Remove extra declaration.

Fixed: e21e3ffd ("psci: Fix warnings when compiling with W=1")
Reported-by: NMichael Scott <mike@foundries.io>
Signed-off-by: NOleksandr Suvorov <oleksandr.suvorov@foundries.io>

On Armv8-R, the EL1&0 memory system architecture is configurable as a
VMSA or PMSA, and resets to an "architecturally unknown" value.

Add code to armv8_switch_to_el1_m which detects whether the MSA at
EL1&0 is configurable using the id_aa64mmfr0_el1 register MSA fields.
If it is we must ensure the VMSA is enabled so that a rich OS can boot.

The MSA and MSA_FRAC fields are described in the Armv8-R architecture
profile supplement (section G1.3.7):
https://developer.arm.com/documentation/ddi0600/latest/Signed-off-by: NPeter Hoyes <Peter.Hoyes@arm.com>

The use of ARMv8.3 pointer authentication (PAuth) is governed by fields
in HCR_EL2, which trigger a 'trap to EL2' if not enabled. The reset
value of these fields is 'architecturally unknown' so we must ensure
that the fields are enabled (to disable the traps) if we are entering
the kernel at EL1.

The APK field disables PAuth instruction traps and the API field
disables PAuth register traps

Add code to disable the traps in armv8_switch_to_el1_m. Prior to doing
so, it checks fields in the ID_AA64ISAR1_EL1 register to ensure pointer
authentication is supported by the hardware.

The runtime checks require a second temporary register, so add this to
the EL1 transition macro signature and update 2 call sites.
Signed-off-by: NPeter Hoyes <Peter.Hoyes@arm.com>

CNTFRQ_EL0 is only writable from the highest supported exception
level on the platform. For Armv8-A, this is typically EL3, but
technically EL2 and EL3 are optional so it may need to be
initialized at EL2 or EL1. For Armv8-R, the highest exception
level is always EL2.

This patch moves the initialization outside of the switch_el
block and uses a new macro branch_if_not_highest_el which
dynamically detects whether it is at the highest supported
exception level.

Linux's docs state that CNTFRQ_EL0 should be initialized by the
bootloader. If not set, the the U-Boot prompt countdown hangs.
Signed-off-by: NPeter Hoyes <Peter.Hoyes@arm.com>

Remove the unused function set_dacr/get_dacr

Serie-cc: Ard Biesheuvel <ardb@kernel.org>
Serie-cc: R Sricharan <r.sricharan@ti.com>
Signed-off-by: NPatrick Delaunay <patrick.delaunay@foss.st.com>

Align TTB_SECT define value with previous value.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@foss.st.com>

The normal memory (other that DCACHE_OFF) should be executable by default,
only the device memory (DCACHE_OFF) used for peripheral access should have
the bit execute never (TTB_SECT_XN_MASK).
Signed-off-by: NPatrick Delaunay <patrick.delaunay@foss.st.com>

Add a return value to noncached_init and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.
Signed-off-by: NOvidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The LPAE versions of DCACHE_WRITEBACK and DCACHE_WRITETHROUGH are currently
defined as no-allocate for both reads and writes, which deviates from the
non-LPAE definition, and mostly defeats the purpose of enabling the caches
in the first place.

So align LPAE with !LPAE, and enable allocate-on-read for both. And while
at it, add some clarification about the meaning of the chosen values.
Signed-off-by: NArd Biesheuvel <ardb@kernel.org>
Reviewed-by: NAndre Przywara <andre.przywara@arm.com>

Provide function for setting arbitrary virtual-physical MMU mapping
and cache settings for the given region.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Update the comments in include/asm/system.h to the common style.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Compiling with clang on ARMv8 shows errors like:

./arch/arm/include/asm/system.h:162:32: note: use constraint modifier "w"
                asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
                                             ^~
                                             %w0

These errors are due to using an incorrect size for the variables used
for writing to and reading from special registers which have 64 bits on
ARMv8.

Mask off reserved bits when reading the exception level.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

arch/arm/include/asm/system.h declares psci_arch_init(), but it is
surrounded by #ifdef CONFIG_ARMV8_PSCI.

psci_arch_init() is called for CONFIG_ARMV7_PSCI too. Add the missing
function declaration.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

It is bad practice to include common.h in other header files since it can
bring in any number of superfluous definitions. It implies that some C
files don't include it and thus may be missing CONFIG options that are set
up by that file. The C files should include these themselves.

Update some header files in arch/arm to drop this.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add the new flags DCACHE_DEFAULT_OPTION to define the default
option to use according the compilation flags
CONFIG_SYS_ARM_CACHE_*.

This new compilation flag allows to simplify dram_bank_mmu_setup()
and can be used as third parameter (option=dcache option to select)
of mmu_set_region_dcache_behaviour function.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Current U-Boot has only support for psci reset.
Adding support for arm psci reset2 allows passing of reset level
and other platform sepcific parameters like strap settings
to lowlevel psci implementation.
Signed-off-by: NRajesh Ravi <rajesh.ravi@broadcom.com>
Signed-off-by: NVladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>

This patch solves the following warnings:
arch/arm/mach-stm32mp/psci.c:

warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes]
warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes]
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Allow EL3 to handle all the External Abort and SError interrupt
exception occur in all exception levels.
Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com>

Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under
armv7 folder. This led to a misconception of creating separate folders
for armv7m and armv7r. There is no reason to create separate folder for
other armv7 based architectures when it can co-exist with few Kconfig
symbols.

As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later
separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and
can co exist in the same folder.
Reviewed-by: NTom Rini <trini@konsulko.com>
Tested-by: NMichal Simek <michal.simek@xilinx.com>
Suggested-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

The save_boot_params_ret() prototype (for those of us, that have a
valid SP on entry and can implement save_boot_params() in C), was
previously only defined for !defined(CONFIG_ARM64).

This moves the declaration to a common block to ensure the prototype
is available to everyone that might need it.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: NAndy Yan <andy.yan@rock-chips.com>

Add jump_to_image_linux() for arm64. Add "noreturn" flag to
armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon
boot.
Signed-off-by: NYork Sun <york.sun@nxp.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NŁukasz Majewski <lukma@denx.de>
Tested-by: NŁukasz Majewski <lukma@denx.de>

At present there is not operation to invalidate a cache range. This seems
to be needed to fill out the cache operations. Add an implementation based
on the flush operation.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Function mmu_change_region_attr() is added to change existing mapping
with updated PXN, UXN and memory type. This is a break-before-make
process during which the mapping becomes fault (invalid) before final
attributres are set.
Signed-off-by: NYork Sun <york.sun@nxp.com>

For 64-bit kernel, there is a warning about x1-x3 nonzero in violation
of boot protocol. To fix this issue, input argument 4 is added for
armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will
be set to the right value, such as zero.
Signed-off-by: NAlison Wang <alison.wang@nxp.com>
Reviewed-by: NAlexander Graf <agraf@suse.de>
Tested-by: NRyan Harkin <ryan.harkin@linaro.org>
Tested-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right
place, this patch does all the setup steps.
Signed-off-by: NHongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

As PSCI and secure monitor firmware framework are enabled, this patch is
to support loading 32-bit OS in such case. The default target exception
level returned to U-Boot is EL2, so the corresponding work to switch to
AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware
together.
Signed-off-by: NAlison Wang <alison.wang@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

To support loading a 32-bit OS, the execution state will change from
AArch64 to AArch32 when jumping to kernel.

The architecture information will be got through checking FIT image,
then U-Boot will load 32-bit OS or 64-bit OS automatically.
Signed-off-by: NEbony Zhu <ebony.zhu@nxp.com>
Signed-off-by: NAlison Wang <alison.wang@nxp.com>
Signed-off-by: NChenhui Zhao <chenhui.zhao@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

While we setup the mmu initially we mark set_section_dcache with
DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
4GB XN. In case of LPAE mode  XN(Execute-never) bit is not set with
DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
keeps all the regions execute okay and this leads to random speculative
fetches in random memory regions which was eventually caught by kernel
omap-l3-noc driver.

Fix this to mark the regions as XN by default.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Reviewed-by: NAlexander Graf <agraf@suse.de>
Reviewed-by: NTom Rini <trini@konsulko.com>

SoC-specific logic may be required for all forms of cache-wide
operations; invalidate and flush of both dcache and icache (note that
only 3 of the 4 possible combinations make sense, since the icache never
contains dirty lines). This patch adds an optional hook for all
implemented cache-wide operations, and renames the one existing hook to
better represent exactly which operation it is implementing. A dummy
no-op implementation of each hook is provided.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Using PSCI you can not only reset the system, you can also shut it down!
This patch exposes a function to do exactly that to whatever code wants
to make use of it.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>

All systems that are running on armv8 are running bare metal with firmware
that implements PSCI running in EL3. That means we don't really need to expose
the hypercall variants of them.

This patch leaves the code in, but makes the code explicit enough to have the
compiler optimize it out. With this we don't need to worry about hvc vs smc
calling convention when calling psci helper functions.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>

On some of the SoCs one cannot enable hypervisor mode directly from the
u-boot because the ROM code puts the chip to supervisor mode after it
jumps to boot loader. Hence introduce a weak function which can be
overridden based on the SoC type and switch to hypervisor mode in a
custom way.

Cc: beagleboard-x15@googlegroups.com
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

As part of testing booting Linux kernels on Rockchip devices, it was
discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for
some cases incomplete isb definitions.  This was causing a failure to
boot of the Linux kernel.

In order to solve this problem as well as cover any corner cases that we
may also have had a number of changes are made in order to consolidate
things.  First, <asm/barriers.h> now becomes the source of isb/dsb/dmb
definitions.  This however introduces another complexity.  Due to
needing to build SPL for 32bit tegra with -march=armv4 we need to borrow
the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete
form.  Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add
a comment about it.  Now that we can always know what the target CPU is
capable off we can get always do the correct thing for the barrier.  The
final part of this is that need to be consistent everywhere and call
isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the
function names in others.
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Tested-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NZiyuan Xu <xzy.xu@rock-chips.com>
Acked-by: NSandy Patterson <apatterson@sightlogix.com>
Reported-by: NZiyuan Xu <xzy.xu@rock-chips.com>
Reported-by: NSandy Patterson <apatterson@sightlogix.com>
Signed-off-by: NTom Rini <trini@konsulko.com>

Add a psci_system_reset() which calls the SYSTEM_RESET function of
PSCI 0.2 and can be used by boards that support it to implement
reset_cpu().
Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

We currently always modify the SVC versions of registers and only support
the short descriptor PTE format.

Some boards however (like the RPi2) run in HYP mode. There, we need to modify
the HYP version of system registers and HYP mode only supports the long
descriptor PTE format.

So this patch introduces support for both long descriptor PTEs and HYP mode
registers.
Signed-off-by: NAlexander Graf <agraf@suse.de>

We want to be able to reuse device drivers from 32bit code, so let's add
definitions for all the dcache options that 32bit code has.

While at it, fix up the DCACHE_OFF configuration. That was setting the bits
to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless
bits and make the index explicit.
Signed-off-by: NAlexander Graf <agraf@suse.de>

By now the code to only have a single page table level with 64k page
size and 42 bit address space is no longer used by any board in tree,
so we can safely remove it.

To clean up code, move the layerscape mmu code to the new defines,
removing redundant field definitions.
Signed-off-by: NAlexander Graf <agraf@suse.de>

The idea to generate our pages tables from an array of memory ranges
is very sound. However, instead of hard coding the code to create up
to 2 levels of 64k granule page tables, we really should just create
normal 4k page tables that allow us to set caching attributes on 2M
or 4k level later on.

So this patch moves the full_va mapping code to 4k page size and
makes it fully flexible to dynamically create as many levels as
necessary for a map (including dynamic 1G/2M pages). It also adds
support to dynamically split a large map into smaller ones when
some code wants to set dcache attributes.

With all this in place, there is very little reason to create your
own page tables in board specific files.
Signed-off-by: NAlexander Graf <agraf@suse.de>

Restore the old behavior of the MMU section entries configuration,
which is without the S-bit.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Simon Glass <sjg@chromium.org>