1. 19 5月, 2021 4 次提交
  2. 18 5月, 2021 18 次提交
  3. 17 5月, 2021 9 次提交
    • T
      Merge https://source.denx.de/u-boot/custodians/u-boot-marvell · feddbdb5
      Tom Rini 提交于
      - Add base support for Marvell OcteonTX2 CN9130 DB (mostly done
        by Kostya)
      - Sync Armada 8k MMU setup with Marvell version (misc Marvell
        authors)
      - spi: kirkwood: Some fixes especially for baudrate generation
        (misc Marvell authors)
      - mvebu: x530: Reduce SPL image size (Stefan)
      - Rename "rx_training" to "mvebu_comphy_rx_training" (Stefan)
      feddbdb5
    • B
      riscv: Group assembly optimized implementation of memory routines into a submenu · 89419279
      Bin Meng 提交于
      Currently all assembly optimized implementation of memory routines
      show up at the top level of the RISC-V architecture Kconfig menu.
      Let's group them together into a submenu.
      Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
      89419279
    • B
      riscv: Fix memmove and optimise memcpy when misalign · 703b84ec
      Bin Meng 提交于
      At present U-Boot SPL fails to boot on SiFive Unleashed board, due
      to a load address misaligned exception happens when loading the FIT
      image in spl_load_simple_fit(). The exception happens in memmove()
      which is called by fdt_splice_().
      
      Commit 8f0dc4cf introduces an assembly version of memmove but
      it does take misalignment into account (it checks if length is a
      multiple of machine word size but pointers need also be aligned).
      As a result it will generate misaligned load/store for the majority
      of cases and causes significant performance regression on hardware
      that traps misaligned load/store and emulate them using firmware.
      
      The current behaviour of memcpy is that it checks if both src and
      dest pointers are co-aligned (aka congruent modular SZ_REG). If
      aligned, it will copy data word-by-word after first aligning
      pointers to word boundary. If src and dst are not co-aligned,
      however, byte-wise copy will be performed.
      
      This patch was taken from the Linux kernel patch [1], which has not
      been applied at the time being. It fixes the memmove and optimises
      memcpy for misaligned cases. It will first align destination pointer
      to word-boundary regardless whether src and dest are co-aligned or
      not. If they indeed are, then wordwise copy is performed. If they
      are not co-aligned, then it will load two adjacent words from src
      and use shifts to assemble a full machine word. Some additional
      assembly level micro-optimisation is also performed to ensure more
      instructions can be compressed (e.g. prefer a0 to t6).
      
      With this patch, U-Boot boots again on SiFive Unleashed board.
      
      [1] https://patchwork.kernel.org/project/linux-riscv/patch/20210216225555.4976-1-gary@garyguo.net/
      
      Fixes: 8f0dc4cf ("riscv: assembler versions of memcpy, memmove, memset")
      Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
      703b84ec
    • S
      riscv: Fix arch_fixup_fdt always failing without /chosen · e90cb0db
      Sean Anderson 提交于
      If /chosen was missing, chosen_offset would never get updated with the new
      /chosen node. This would cause fdt_setprop_u32 to fail. This patch fixes
      this by setting chosen_offset. In addition, log any errors from setting
      boot-hartid as well.
      
      Fixes: 5370478d ("riscv: Add boot hartid to device tree")
      Signed-off-by: NSean Anderson <seanga2@gmail.com>
      Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
      Reviewed-by: NRick Chen <rick@andestech.com>
      Reviewed-by: NAtish Patra <atish.patra@wdc.com>
      e90cb0db
    • B
      riscv: Split SiFive CLINT support between SPL and U-Boot proper · a6d7e8c9
      Bin Meng 提交于
      At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to
      control the enabling of SiFive CLINT support in both SPL (M-mode)
      and U-Boot proper (S-mode). So for a typical SPL config that the
      SiFive CLINT driver is enabled in both SPL and U-Boot proper, that
      means the S-mode U-Boot tries to access the memory-mapped CLINT
      registers directly, instead of the normal 'rdtime' instruction.
      
      This was not a problem before, as the hardware does not forbid the
      access from S-mode. However this becomes an issue now with OpenSBI
      commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain")
      that the SiFive CLINT register space is protected by PMP for M-mode
      access only. U-Boot proper does not boot any more with the latest
      OpenSBI, that access exceptions are fired forever from U-Boot when
      trying to read the timer value via the SiFive CLINT driver in U-Boot.
      
      To solve this, we need to split current SiFive CLINT support between
      SPL and U-Boot proper, using 2 separate Kconfig options.
      Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
      Reviewed-by: NSean Anderson <seanga2@gmail.com>
      a6d7e8c9
    • B
      riscv: ax25-ae350: doc: Fix minor format issues · 2b039940
      Bin Meng 提交于
      This fixes two minor format issues of the ax25-ae350 reST file.
      Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
      Reviewed-by: NRick Chen <rick@andestech.com>
      2b039940
    • T
      7e1d0a8f
    • K
      usb: dwc3-generic: Disable host driver definition if gadget only · a5f9be1e
      Kunihiko Hayashi 提交于
      Even if only USB gadget is defined, dwc3 generic driver enables
      a definition and probe/remove functions for host driver.
      
      This enables the definition if USB_HOST is enabled only.
      Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
      a5f9be1e
    • A
      usb: musb-new: Extend and move Allwinner quirk into Kconfig · 1027f28b
      Andre Przywara 提交于
      All newer Allwinner SoCs (since about 2013) miss the CONFIGDATA register
      in their MUSB implementation, so they need a quirk to hardcode this.
      
      Currently this quirk depends on listing the SoCs affected in musb_reg.h,
      which means that this list needs to grow with every new chip.
      
      Move the quirk feature into Kconfig, next to PIO_ONLY, and change the
      default to y (for Allwinner builds), while listing the early
      implementations as exceptions.
      
      This fixes USB peripheral operation on some newer SoCs, which were not
      explicitly listed before.
      
      Tested on H6, H616, R40 (which were broken before), and also on the H5
      and A20, for regressions.
      Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
      1027f28b
  4. 16 5月, 2021 9 次提交