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体验新版 GitCode,发现更多精彩内容 >>
提交
fd2f5658
编写于
6月 06, 2011
作者:
E
Eric Benard
提交者:
Albert ARIBAUD
6月 21, 2011
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电子邮件补丁
差异文件
include/asm/arch-at91: update several .h files to ATMEL_xxx name scheme
Signed-off-by:
N
Eric Bénard
<
eric@eukrea.com
>
上级
d0a94620
变更
5
隐藏空白更改
内联
并排
Showing
5 changed file
with
28 addition
and
28 deletion
+28
-28
arch/arm/include/asm/arch-at91/at91_matrix.h
arch/arm/include/asm/arch-at91/at91_matrix.h
+5
-5
arch/arm/include/asm/arch-at91/at91_rstc.h
arch/arm/include/asm/arch-at91/at91_rstc.h
+1
-1
arch/arm/include/asm/arch-at91/at91_wdt.h
arch/arm/include/asm/arch-at91/at91_wdt.h
+1
-1
arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
+15
-15
arch/arm/include/asm/arch-at91/at91sam9_smc.h
arch/arm/include/asm/arch-at91/at91sam9_smc.h
+6
-6
未找到文件。
arch/arm/include/asm/arch-at91/at91_matrix.h
浏览文件 @
fd2f5658
...
...
@@ -26,18 +26,18 @@
#ifdef __ASSEMBLY__
#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
#define AT91_ASM_MATRIX_CSA0 (AT
91_MATRIX_BASE
+ 0x11C)
#define AT91_ASM_MATRIX_CSA0 (AT
MEL_BASE_MATRIX
+ 0x11C)
#elif defined(CONFIG_AT91SAM9261)
#define AT91_ASM_MATRIX_CSA0 (AT
91_MATRIX_BASE
+ 0x30)
#define AT91_ASM_MATRIX_CSA0 (AT
MEL_BASE_MATRIX
+ 0x30)
#elif defined(CONFIG_AT91SAM9263)
#define AT91_ASM_MATRIX_CSA0 (AT
91_MATRIX_BASE
+ 0x120)
#define AT91_ASM_MATRIX_CSA0 (AT
MEL_BASE_MATRIX
+ 0x120)
#elif defined(CONFIG_AT91SAM9G45)
#define AT91_ASM_MATRIX_CSA0 (AT
91_MATRIX_BASE
+ 0x128)
#define AT91_ASM_MATRIX_CSA0 (AT
MEL_BASE_MATRIX
+ 0x128)
#else
#error AT91_ASM_MATRIX_CSA0 is not definied for current CPU
#endif
#define AT91_ASM_MATRIX_MCFG AT
91_MATRIX_BASE
#define AT91_ASM_MATRIX_MCFG AT
MEL_BASE_MATRIX
#else
#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
...
...
arch/arm/include/asm/arch-at91/at91_rstc.h
浏览文件 @
fd2f5658
...
...
@@ -16,7 +16,7 @@
#ifndef AT91_RSTC_H
#define AT91_RSTC_H
#define AT91_ASM_RSTC_MR (AT
91_RSTC_BASE
+ 0x08)
#define AT91_ASM_RSTC_MR (AT
MEL_BASE_RSTC
+ 0x08)
#ifndef __ASSEMBLY__
...
...
arch/arm/include/asm/arch-at91/at91_wdt.h
浏览文件 @
fd2f5658
...
...
@@ -19,7 +19,7 @@
#ifdef __ASSEMBLY__
#define AT91_ASM_WDT_MR (AT
91_WDT_BASE
+ 0x04)
#define AT91_ASM_WDT_MR (AT
MEL_BASE_WDT
+ 0x04)
#else
...
...
arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
浏览文件 @
fd2f5658
...
...
@@ -19,19 +19,19 @@
#ifdef __ASSEMBLY__
#ifndef AT
91_SDRAMC_BASE
#define AT
91_SDRAMC_BASE
AT91_SDRAMC0_BASE
#ifndef AT
MEL_BASE_SDRAMC
#define AT
MEL_BASE_SDRAMC
AT91_SDRAMC0_BASE
#endif
#define AT91_ASM_SDRAMC_MR AT
91_SDRAMC_BASE
#define AT91_ASM_SDRAMC_TR (AT
91_SDRAMC_BASE
+ 0x04)
#define AT91_ASM_SDRAMC_CR (AT
91_SDRAMC_BASE
+ 0x08)
#define AT91_ASM_SDRAMC_MDR (AT
91_SDRAMC_BASE
+ 0x24)
#define AT91_ASM_SDRAMC_MR AT
MEL_BASE_SDRAMC
#define AT91_ASM_SDRAMC_TR (AT
MEL_BASE_SDRAMC
+ 0x04)
#define AT91_ASM_SDRAMC_CR (AT
MEL_BASE_SDRAMC
+ 0x08)
#define AT91_ASM_SDRAMC_MDR (AT
MEL_BASE_SDRAMC
+ 0x24)
#endif
/* SDRAM Controller (SDRAMC) registers */
#define AT91_SDRAMC_MR (AT
91
_SDRAMC + 0x00)
/* SDRAM Controller Mode Register */
#define AT91_SDRAMC_MR (AT
MEL_BASE
_SDRAMC + 0x00)
/* SDRAM Controller Mode Register */
#define AT91_SDRAMC_MODE (0xf << 0)
/* Command Mode */
#define AT91_SDRAMC_MODE_NORMAL 0
#define AT91_SDRAMC_MODE_NOP 1
...
...
@@ -41,10 +41,10 @@
#define AT91_SDRAMC_MODE_EXT_LMR 5
#define AT91_SDRAMC_MODE_DEEP 6
#define AT91_SDRAMC_TR (AT
91
_SDRAMC + 0x04)
/* SDRAM Controller Refresh Timer Register */
#define AT91_SDRAMC_TR (AT
MEL_BASE
_SDRAMC + 0x04)
/* SDRAM Controller Refresh Timer Register */
#define AT91_SDRAMC_COUNT (0xfff << 0)
/* Refresh Timer Counter */
#define AT91_SDRAMC_CR (AT
91
_SDRAMC + 0x08)
/* SDRAM Controller Configuration Register */
#define AT91_SDRAMC_CR (AT
MEL_BASE
_SDRAMC + 0x08)
/* SDRAM Controller Configuration Register */
#define AT91_SDRAMC_NC (3 << 0)
/* Number of Column Bits */
#define AT91_SDRAMC_NC_8 (0 << 0)
#define AT91_SDRAMC_NC_9 (1 << 0)
...
...
@@ -71,7 +71,7 @@
#define AT91_SDRAMC_TRAS (0xf << 24)
/* Active to Precharge Delay */
#define AT91_SDRAMC_TXSR (0xf << 28)
/* Exit Self Refresh to Active Delay */
#define AT91_SDRAMC_LPR (AT
91
_SDRAMC + 0x10)
/* SDRAM Controller Low Power Register */
#define AT91_SDRAMC_LPR (AT
MEL_BASE
_SDRAMC + 0x10)
/* SDRAM Controller Low Power Register */
#define AT91_SDRAMC_LPCB (3 << 0)
/* Low-power Configurations */
#define AT91_SDRAMC_LPCB_DISABLE 0
#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
...
...
@@ -85,13 +85,13 @@
#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
#define AT91_SDRAMC_IER (AT
91
_SDRAMC + 0x14)
/* SDRAM Controller Interrupt Enable Register */
#define AT91_SDRAMC_IDR (AT
91
_SDRAMC + 0x18)
/* SDRAM Controller Interrupt Disable Register */
#define AT91_SDRAMC_IMR (AT
91
_SDRAMC + 0x1C)
/* SDRAM Controller Interrupt Mask Register */
#define AT91_SDRAMC_ISR (AT
91
_SDRAMC + 0x20)
/* SDRAM Controller Interrupt Status Register */
#define AT91_SDRAMC_IER (AT
MEL_BASE
_SDRAMC + 0x14)
/* SDRAM Controller Interrupt Enable Register */
#define AT91_SDRAMC_IDR (AT
MEL_BASE
_SDRAMC + 0x18)
/* SDRAM Controller Interrupt Disable Register */
#define AT91_SDRAMC_IMR (AT
MEL_BASE
_SDRAMC + 0x1C)
/* SDRAM Controller Interrupt Mask Register */
#define AT91_SDRAMC_ISR (AT
MEL_BASE
_SDRAMC + 0x20)
/* SDRAM Controller Interrupt Status Register */
#define AT91_SDRAMC_RES (1 << 0)
/* Refresh Error Status */
#define AT91_SDRAMC_MDR (AT
91
_SDRAMC + 0x24)
/* SDRAM Memory Device Register */
#define AT91_SDRAMC_MDR (AT
MEL_BASE
_SDRAMC + 0x24)
/* SDRAM Memory Device Register */
#define AT91_SDRAMC_MD (3 << 0)
/* Memory Device Type */
#define AT91_SDRAMC_MD_SDRAM 0
#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
...
...
arch/arm/include/asm/arch-at91/at91sam9_smc.h
浏览文件 @
fd2f5658
...
...
@@ -18,14 +18,14 @@
#ifdef __ASSEMBLY__
#ifndef AT
91_SMC_BASE
#define AT
91_SMC_BASE AT91_SMC0_BASE
#ifndef AT
MEL_BASE_SMC
#define AT
MEL_BASE_SMC ATMEL_BASE_SMC0
#endif
#define AT91_ASM_SMC_SETUP0 AT
91_SMC_BASE
#define AT91_ASM_SMC_PULSE0 (AT
91_SMC_BASE
+ 0x04)
#define AT91_ASM_SMC_CYCLE0 (AT
91_SMC_BASE
+ 0x08)
#define AT91_ASM_SMC_MODE0 (AT
91_SMC_BASE
+ 0x0C)
#define AT91_ASM_SMC_SETUP0 AT
MEL_BASE_SMC
#define AT91_ASM_SMC_PULSE0 (AT
MEL_BASE_SMC
+ 0x04)
#define AT91_ASM_SMC_CYCLE0 (AT
MEL_BASE_SMC
+ 0x08)
#define AT91_ASM_SMC_MODE0 (AT
MEL_BASE_SMC
+ 0x0C)
#else
...
...
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