powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers
The write recovery time of both registers should match. Since mode register doesn't support cycles of 9,11,13,15, we should use next higher number for both registers. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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