Merge branch '2020-01-10-master-imports'

- Android image support enhancements
- Assorted ARM fixes and enhancements
- m68k update

Makefile

@@ -672,11 +672,12 @@ endif
 endif
 
 KBUILD_CFLAGS += $(call cc-option,-Wno-format-nonliteral)
+KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member)
+
 ifeq ($(cc-name),clang)
 KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)
 KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier)
 KBUILD_CFLAGS += $(call cc-disable-warning, gnu)
-KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member)
 KBUILD_CFLAGS += $(call cc-option, -fcatch-undefined-behavior)
 endif
 

arch/arm/Kconfig

@@ -61,6 +61,16 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE
 endif
 endif
 
+config GIC_V3_ITS
+	bool "ARM GICV3 ITS"
+	help
+	  ARM GICV3 Interrupt translation service (ITS).
+	  Basic support for programming locality specific peripheral
+	  interrupts (LPI) configuration tables and enable LPI tables.
+	  LPI configuration table can be used by u-boot or Linux.
+	  ARM GICV3 has limitation, once the LPI table is enabled, LPI
+	  configuration table can not be re-programmed, unless GICV3 reset.
+
 config STATIC_RELA
 	bool
 	default y if ARM64 && !POSITION_INDEPENDENT

arch/arm/cpu/armv8/fwcall.c

@@ -98,6 +98,22 @@ void __noreturn psci_system_reset(void)
 		;
 }
 
+void __noreturn psci_system_reset2(u32 reset_level, u32 cookie)
+{
+	struct pt_regs regs;
+
+	regs.regs[0] = ARM_PSCI_0_2_FN64_SYSTEM_RESET2;
+	regs.regs[1] = PSCI_RESET2_TYPE_VENDOR | reset_level;
+	regs.regs[2] = cookie;
+	if (use_smc_for_psci)
+		smc_call(&regs);
+	else
+		hvc_call(&regs);
+
+	while (1)
+		;
+}
+
 void __noreturn psci_system_off(void)
 {
 	struct pt_regs regs;

arch/arm/include/asm/gic-v3.h

+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom.
+ */
+
+#ifndef __GIC_V3_H__
+#define __GIC_V3_H__
+
+#define GICR_CTLR_ENABLE_LPIS		BIT(0)
+#define GICR_CTLR_RWP			BIT(3)
+
+#define GICR_TYPER_CPU_NUMBER(r)	(((r) >> 8) & 0xffff)
+
+#define GICR_WAKER_PROCESSORSLEEP	BIT(1)
+#define GICR_WAKER_CHILDRENASLEEP	BIT(2)
+
+#define GIC_BASER_CACHE_NCNB		0ULL
+#define GIC_BASER_CACHE_SAMEASINNER	0ULL
+#define GIC_BASER_CACHE_NC		1ULL
+#define GIC_BASER_CACHE_RAWT		2ULL
+#define GIC_BASER_CACHE_RAWB		3ULL
+#define GIC_BASER_CACHE_WAWT		4ULL
+#define GIC_BASER_CACHE_WAWB		5ULL
+#define GIC_BASER_CACHE_RAWAWT		6ULL
+#define GIC_BASER_CACHE_RAWAWB		7ULL
+#define GIC_BASER_CACHE_MASK		7ULL
+#define GIC_BASER_NONSHAREABLE		0ULL
+#define GIC_BASER_INNERSHAREABLE	1ULL
+#define GIC_BASER_OUTERSHAREABLE	2ULL
+#define GIC_BASER_SHAREABILITY_MASK	3ULL
+
+#define GIC_BASER_CACHEABILITY(reg, inner_outer, type)	\
+	(GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)
+
+#define GIC_BASER_SHAREABILITY(reg, type)	\
+	(GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
+
+/* encode a size field of width @w containing @n - 1 units */
+#define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) &\
+			     GENMASK_ULL(((w) - 1), 0))
+
+#define GICR_PROPBASER_SHAREABILITY_SHIFT		(10)
+#define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT		(7)
+#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT		(56)
+#define GICR_PROPBASER_SHAREABILITY_MASK	\
+	GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK)
+#define GICR_PROPBASER_INNER_CACHEABILITY_MASK	\
+	GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK)
+#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK	\
+	GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK)
+#define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK
+
+#define GICR_PROPBASER_INNERSHAREABLE	\
+	GIC_BASER_SHAREABILITY(GICR_PROPBASER, INNERSHAREABLE)
+
+#define GICR_PROPBASER_NCNB	\
+	GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, NCNB)
+#define GICR_PROPBASER_NC	\
+	GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, NC)
+#define GICR_PROPBASER_RAWT	\
+	GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWT)
+#define GICR_PROPBASER_RAWB	\
+	GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWB)
+#define GICR_PROPBASER_WAWT	\
+	GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WAWT)
+#define GICR_PROPBASER_WAWB	\
+	GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WAWB)
+#define GICR_PROPBASER_RAWAWT	\
+	GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWAWT)
+#define GICR_PROPBASER_RAWAWB	\
+	GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RAWAWB)
+
+#define GICR_PROPBASER_IDBITS_MASK	(0x1f)
+#define GICR_PROPBASER_ADDRESS(x)	((x) & GENMASK_ULL(51, 12))
+#define GICR_PENDBASER_ADDRESS(x)	((x) & GENMASK_ULL(51, 16))
+
+#define GICR_PENDBASER_SHAREABILITY_SHIFT		(10)
+#define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT		(7)
+#define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT		(56)
+#define GICR_PENDBASER_SHAREABILITY_MASK	\
+	GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK)
+#define GICR_PENDBASER_INNER_CACHEABILITY_MASK	\
+	GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK)
+#define GICR_PENDBASER_OUTER_CACHEABILITY_MASK	\
+	GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK)
+#define GICR_PENDBASER_CACHEABILITY_MASK	\
+	GICR_PENDBASER_INNER_CACHEABILITY_MASK
+
+#define GICR_PENDBASER_INNERSHAREABLE	\
+	GIC_BASER_SHAREABILITY(GICR_PENDBASER, INNERSHAREABLE)
+
+#define GICR_PENDBASER_NCNB	\
+	GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, NCNB)
+#define GICR_PENDBASER_NC	\
+	GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, NC)
+#define GICR_PENDBASER_RAWT	\
+	GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RAWT)
+#define GICR_PENDBASER_RAWB	\
+	GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RAWB)
+#define GICR_PENDBASER_WAWT	\
+	GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WAWT)
+#define GICR_PENDBASER_WAWB	\
+	GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WAWB)
+#define GICR_PENDBASER_RAWAWT	\
+	GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RAWAWT)
+#define GICR_PENDBASER_RAWAWB	\
+	GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RAWAWB)
+
+#define GICR_PENDBASER_PTZ	BIT_ULL(62)
+
+#define ITS_MAX_LPI_NRBITS	16 /* 64K LPIs */
+
+#define GICD_TYPER_ID_BITS(typer)	((((typer) >> 19) & 0x1f) + 1)
+#define GICD_TYPER_NUM_LPIS(typer)	((((typer) >> 11) & 0x1f) + 1)
+#define GICD_TYPER_IRQS(typer)		((((typer) & 0x1f) + 1) * 32)
+
+/* Message based interrupts support */
+#define GICD_TYPER_MBIS		BIT(16)
+/* LPI support */
+#define GICD_TYPER_LPIS		BIT(17)
+#define GICD_TYPER_RSS		BIT(26)
+
+#define GIC_REDISTRIBUTOR_OFFSET 0x20000
+
+#ifdef CONFIG_GIC_V3_ITS
+int gic_lpi_tables_init(u64 base, u32 max_redist);
+#else
+int gic_lpi_tables_init(u64 base, u32 max_redist)
+{
+	return 0;
+}
+#endif /* CONFIG_GIC_V3_ITS */
+
+#endif /* __GIC_V3_H__ */

arch/arm/include/asm/psci.h

@@ -64,6 +64,7 @@
 #define ARM_PSCI_0_2_FN64_AFFINITY_INFO		ARM_PSCI_0_2_FN64(4)
 #define ARM_PSCI_0_2_FN64_MIGRATE		ARM_PSCI_0_2_FN64(5)
 #define ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU	ARM_PSCI_0_2_FN64(7)
+#define ARM_PSCI_0_2_FN64_SYSTEM_RESET2		ARM_PSCI_0_2_FN64(18)
 
 /* PSCI 1.0 interface */
 #define ARM_PSCI_1_0_FN_PSCI_FEATURES		ARM_PSCI_0_2_FN(10)
@@ -90,6 +91,9 @@
 #define PSCI_AFFINITY_LEVEL_OFF		1
 #define PSCI_AFFINITY_LEVEL_ON_PENDING	2
 
+#define PSCI_RESET2_TYPE_VENDOR_SHIFT	31
+#define PSCI_RESET2_TYPE_VENDOR		BIT(PSCI_RESET2_TYPE_VENDOR_SHIFT)
+
 #ifndef __ASSEMBLY__
 #include <asm/types.h>
 

arch/arm/include/asm/system.h

@@ -254,6 +254,7 @@ void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs);
 void smc_call(struct pt_regs *args);
 
 void __noreturn psci_system_reset(void);
+void __noreturn psci_system_reset2(u32 reset_level, u32 cookie);
 void __noreturn psci_system_off(void);
 
 #ifdef CONFIG_ARMV8_PSCI

arch/arm/lib/Makefile

@@ -52,6 +52,7 @@ obj-$(CONFIG_FSL_LAYERSCAPE) += ccn504.o
 ifneq ($(CONFIG_GICV2)$(CONFIG_GICV3),)
 obj-y	+= gic_64.o
 endif
+obj-$(CONFIG_GIC_V3_ITS)	+= gic-v3-its.o
 obj-y	+= interrupts_64.o
 else
 obj-y	+= interrupts.o

arch/arm/lib/gic-v3-its.c

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Broadcom.
+ */
+#include <common.h>
+#include <asm/gic.h>
+#include <asm/gic-v3.h>
+#include <asm/io.h>
+
+static u32 lpi_id_bits;
+
+#define LPI_NRBITS		lpi_id_bits
+#define LPI_PROPBASE_SZ		ALIGN(BIT(LPI_NRBITS), SZ_64K)
+#define LPI_PENDBASE_SZ		ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
+
+/*
+ * Program the GIC LPI configuration tables for all
+ * the re-distributors and enable the LPI table
+ * base: Configuration table address
+ * num_redist: number of redistributors
+ */
+int gic_lpi_tables_init(u64 base, u32 num_redist)
+{
+	u32 gicd_typer;
+	u64 val;
+	u64 tmp;
+	int i;
+	u64 redist_lpi_base;
+	u64 pend_base = GICR_BASE + GICR_PENDBASER;
+
+	gicd_typer = readl(GICD_BASE + GICD_TYPER);
+
+	/* GIC support for Locality specific peripheral interrupts (LPI's) */
+	if (!(gicd_typer & GICD_TYPER_LPIS)) {
+		pr_err("GIC implementation does not support LPI's\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Check for LPI is disabled for all the redistributors.
+	 * Once the LPI table is enabled, can not program the
+	 * LPI configuration tables again, unless the GIC is reset.
+	 */
+	for (i = 0; i < num_redist; i++) {
+		u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
+
+		if ((readl((uintptr_t)(GICR_BASE + offset))) &
+		    GICR_CTLR_ENABLE_LPIS) {
+			pr_err("Re-Distributor %d LPI is already enabled\n",
+			       i);
+			return -EINVAL;
+		}
+	}
+
+	/* lpi_id_bits to get LPI_PENDBASE_SZ and LPi_PROPBASE_SZ */
+	lpi_id_bits = min_t(u32, GICD_TYPER_ID_BITS(gicd_typer),
+			    ITS_MAX_LPI_NRBITS);
+
+	/* Set PropBase */
+	val = (base |
+	       GICR_PROPBASER_INNERSHAREABLE |
+	       GICR_PROPBASER_RAWAWB |
+	       ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
+
+	writeq(val, (GICR_BASE + GICR_PROPBASER));
+	tmp = readl(GICR_BASE + GICR_PROPBASER);
+	if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
+		if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
+			val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
+				GICR_PROPBASER_CACHEABILITY_MASK);
+			val |= GICR_PROPBASER_NC;
+			writeq(val, (GICR_BASE + GICR_PROPBASER));
+		}
+	}
+
+	redist_lpi_base = base + LPI_PROPBASE_SZ;
+
+	for (i = 0; i < num_redist; i++) {
+		u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
+
+		val = ((redist_lpi_base + (i * LPI_PENDBASE_SZ)) |
+			GICR_PENDBASER_INNERSHAREABLE |
+			GICR_PENDBASER_RAWAWB);
+
+		writeq(val, (uintptr_t)(pend_base + offset));
+		tmp = readq((uintptr_t)(pend_base + offset));
+		if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
+			val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
+				 GICR_PENDBASER_CACHEABILITY_MASK);
+			val |= GICR_PENDBASER_NC;
+			writeq(val, (uintptr_t)(pend_base + offset));
+		}
+
+		/* Enable LPI for the redistributor */
+		writel(GICR_CTLR_ENABLE_LPIS, (uintptr_t)(GICR_BASE + offset));
+	}
+
+	return 0;
+}
+

arch/m68k/cpu/mcf523x/cpu_init.c

@@ -157,7 +157,7 @@ void uart_port_conf(int port)
 }
 
 #if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
 {
 	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 

arch/m68k/cpu/mcf52x2/cpu_init.c

@@ -158,7 +158,7 @@ void uart_port_conf(int port)
 }
 
 #if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
 {
 	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
@@ -305,7 +305,7 @@ void uart_port_conf(int port)
 }
 
 #if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
 {
 	if (setclear) {
 		/* Enable Ethernet pins */
@@ -426,7 +426,7 @@ void uart_port_conf(int port)
 }
 
 #if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
 {
 	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
@@ -509,14 +509,17 @@ void uart_port_conf(int port)
 }
 
 #if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
 {
-	struct fec_info_s *info = (struct fec_info_s *) dev->priv;
 	gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+	u32 fec0_base;
+
+	if (fec_get_base_addr(0, &fec0_base))
+		return -1;
 
 	if (setclear) {
 		/* Enable Ethernet pins */
-		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+		if (info->iobase == fec0_base) {
 			setbits_be16(&gpio->par_feci2c, 0x0f00);
 			setbits_8(&gpio->par_fec0hl, 0xc0);
 		} else {
@@ -524,7 +527,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 			setbits_8(&gpio->par_fec1hl, 0xc0);
 		}
 	} else {
-		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+		if (info->iobase == fec0_base) {
 			clrbits_be16(&gpio->par_feci2c, 0x0f00);
 			clrbits_8(&gpio->par_fec0hl, 0xc0);
 		} else {
@@ -644,7 +647,7 @@ void uart_port_conf(int port)
 }
 
 #if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
 {
 	if (setclear) {
 		MCFGPIO_PASPAR |= 0x0F00;

arch/m68k/cpu/mcf532x/cpu.c

@@ -146,7 +146,6 @@ int watchdog_init(void)
  * create a board-specific function called:
  * 	int board_eth_init(bd_t *bis)
  */
-
 int cpu_eth_init(bd_t *bis)
 {
 	return mcffec_initialize(bis);

arch/m68k/cpu/mcf532x/cpu_init.c

@@ -14,7 +14,7 @@
 #include <asm/immap.h>
 #include <asm/io.h>
 
-#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_MCFFEC)
 #include <config.h>
 #include <net.h>
 #include <asm/fec.h>
@@ -94,6 +94,7 @@ void cpu_init_f(void)
 int cpu_init_r(void)
 {
 #ifdef CONFIG_MCFFEC
+	u32 fec_mii_base0, fec_mii_base1;
 	ccm_t *ccm = (ccm_t *) MMAP_CCM;
 #endif
 #ifdef CONFIG_MCFRTC
@@ -105,7 +106,10 @@ int cpu_init_r(void)
 
 #endif
 #ifdef CONFIG_MCFFEC
-	if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
+	fec_get_mii_base(0, &fec_mii_base0);
+	fec_get_mii_base(1, &fec_mii_base1);
+
+	if (fec_mii_base0 != fec_mii_base1)
 		setbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
 	else
 		clrbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
@@ -168,13 +172,16 @@ void uart_port_conf(int port)
 }
 
 #if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
 {
 	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	struct fec_info_s *info = (struct fec_info_s *)dev->priv;
+	u32 fec0_base;
+
+	if (fec_get_base_addr(0, &fec0_base))
+		return -1;
 
 	if (setclear) {
-		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+		if (info->iobase == fec0_base) {
 			setbits_8(&gpio->par_fec,
 				GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
 			setbits_8(&gpio->par_feci2c,
@@ -186,7 +193,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 				GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1);
 		}
 	} else {
-		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+		if (info->iobase == fec0_base) {
 			clrbits_8(&gpio->par_fec,
 				GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
 			clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII0_UNMASK);
@@ -329,7 +336,7 @@ void uart_port_conf(int port)
 }
 
 #if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
 {
 	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 

arch/m68k/cpu/mcf5445x/cpu_init.c

@@ -402,15 +402,18 @@ void uart_port_conf(int port)
 }
 
 #if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
 {
 	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-#ifdef CONFIG_MCF5445x
-	struct fec_info_s *info = (struct fec_info_s *)dev->priv;
+	u32 fec0_base;
+
+	if (fec_get_base_addr(0, &fec0_base))
+		return -1;
 
+#ifdef CONFIG_MCF5445x
 	if (setclear) {
 #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
-		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+		if (info->iobase == fec0_base)
 			setbits_be16(&gpio->par_feci2c,
 				GPIO_PAR_FECI2C_MDC0_MDC0 |
 				GPIO_PAR_FECI2C_MDIO0_MDIO0);
@@ -423,7 +426,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 			GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
 #endif
 
-		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+		if (info->iobase == fec0_base)
 			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
 		else
 			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
@@ -431,7 +434,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 		clrbits_be16(&gpio->par_feci2c,
 			GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
 
-		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+		if (info->iobase == fec0_base) {
 #ifdef CONFIG_SYS_FEC_FULL_MII
 			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
 #else
@@ -463,4 +466,3 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 	return 0;
 }
 #endif
-

arch/m68k/cpu/mcf547x_8x/cpu_init.c

@@ -17,6 +17,7 @@
 #if defined(CONFIG_CMD_NET)
 #include <config.h>
 #include <net.h>
+#include <asm/fec.h>
 #include <asm/fsl_mcdmafec.h>
 #endif
 
@@ -124,18 +125,21 @@ void uart_port_conf(int port)
 }
 
 #if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
 {
 	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
+	u32 fec0_base;
+
+	if (fec_get_base_addr(0, &fec0_base))
+		return -1;
 
 	if (setclear) {
-		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+		if (info->iobase == fec0_base)
 			setbits_be16(&gpio->par_feci2cirq, 0xf000);
 		else
 			setbits_be16(&gpio->par_feci2cirq, 0x0fc0);
 	} else {
-		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+		if (info->iobase == fec0_base)
 			clrbits_be16(&gpio->par_feci2cirq, 0xf000);
 		else
 			clrbits_be16(&gpio->par_feci2cirq, 0x0fc0);

arch/m68k/dts/M5208EVBE.dts

@@ -20,3 +20,6 @@
 	status = "okay";
 };
 
+&fec0 {
+	status = "okay";
+};

arch/m68k/dts/M5235EVB.dts

@@ -20,3 +20,6 @@
 	status = "okay";
 };
 
+&fec0 {
+	status = "okay";
+};

arch/m68k/dts/M5235EVB_Flash32.dts

@@ -20,3 +20,6 @@
 	status = "okay";
 };
 
+&fec0 {
+	status = "okay";
+};

arch/m68k/dts/M5272C3.dts

@@ -20,3 +20,6 @@
 	status = "okay";
 };
 
+&fec0 {
+	status = "okay";
+};

arch/m68k/dts/M5275EVB.dts

@@ -20,3 +20,10 @@
 	status = "okay";
 };
 
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+};

arch/m68k/dts/M5282EVB.dts

@@ -20,3 +20,6 @@
 	status = "okay";
 };
 
+&fec0 {
+	status = "okay";
+};

arch/m68k/dts/M53017EVB.dts

@@ -20,3 +20,10 @@
 	status = "okay";
 };
 
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+};

arch/m68k/dts/M5329AFEE.dts

@@ -20,3 +20,6 @@
 	status = "okay";
 };
 
+&fec0 {
+	status = "okay";
+};

arch/m68k/dts/M5329BFEE.dts

@@ -20,3 +20,6 @@
 	status = "okay";
 };
 
+&fec0 {
+	status = "okay";
+};

arch/m68k/dts/M5373EVB.dts

@@ -20,3 +20,6 @@
 	status = "okay";
 };
 
+&fec0 {
+	status = "okay";
+};

arch/m68k/dts/M54418TWR.dts

@@ -23,3 +23,12 @@
 &dspi0 {
 	status = "okay";
 };
+
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M54418TWR_nand_mii.dts

@@ -23,3 +23,12 @@
 &dspi0 {
 	status = "okay";
 };
+
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M54418TWR_nand_rmii.dts

@@ -23,3 +23,12 @@
 &dspi0 {
 	status = "okay";
 };
+
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts

@@ -23,3 +23,12 @@
 &dspi0 {
 	status = "okay";
 };
+
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M54418TWR_serial_mii.dts

@@ -23,3 +23,12 @@
 &dspi0 {
 	status = "okay";
 };
+
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M54418TWR_serial_rmii.dts

@@ -23,3 +23,12 @@
 &dspi0 {
 	status = "okay";
 };
+
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M54451EVB.dts

@@ -23,3 +23,11 @@
 &dspi0 {
 	status = "okay";
 };
+
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+};

arch/m68k/dts/M54451EVB_stmicro.dts

@@ -23,3 +23,11 @@
 &dspi0 {
 	status = "okay";
 };
+
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+};

arch/m68k/dts/M54455EVB.dts

@@ -23,3 +23,12 @@
 &dspi0 {
 	status = "okay";
 };
+
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M54455EVB_a66.dts

@@ -23,3 +23,12 @@
 &dspi0 {
 	status = "okay";
 };
+
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M54455EVB_i66.dts

@@ -23,3 +23,12 @@
 &dspi0 {
 	status = "okay";
 };
+
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M54455EVB_intel.dts

@@ -24,3 +24,11 @@
 	status = "okay";
 };
 
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M54455EVB_stm33.dts

@@ -23,3 +23,12 @@
 &dspi0 {
 	status = "okay";
 };
+
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M5475AFE.dts

@@ -11,3 +11,11 @@
 	compatible = "fsl,M5475AFE";
 };
 
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M5475BFE.dts

@@ -11,3 +11,11 @@
 	compatible = "fsl,M5475BFE";
 };
 
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M5475CFE.dts

@@ -11,3 +11,11 @@
 	compatible = "fsl,M5475CFE";
 };
 
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M5475DFE.dts

@@ -11,3 +11,11 @@
 	compatible = "fsl,M5475DFE";
 };
 
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M5475EFE.dts

@@ -11,3 +11,11 @@
 	compatible = "fsl,M5475EFE";
 };
 
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M5475FFE.dts

@@ -11,3 +11,11 @@
 	compatible = "fsl,M5475FFE";
 };
 
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M5475GFE.dts

@@ -11,3 +11,11 @@
 	compatible = "fsl,M5475GFE";
 };
 
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M5485AFE.dts

@@ -15,3 +15,11 @@
 	};
 };
 
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M5485BFE.dts

@@ -15,3 +15,11 @@
 	};
 };
 
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M5485CFE.dts

@@ -15,3 +15,11 @@
 	};
 };
 
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M5485DFE.dts

@@ -15,3 +15,11 @@
 	};
 };
 
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M5485EFE.dts

@@ -15,3 +15,11 @@
 	};
 };
 
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M5485FFE.dts

@@ -15,3 +15,11 @@
 	};
 };
 
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M5485GFE.dts

@@ -15,3 +15,11 @@
 	};
 };
 
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/M5485HFE.dts

@@ -15,3 +15,11 @@
 	};
 };
 
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/dts/cobra5272.dts

@@ -20,3 +20,6 @@
 	status = "okay";
 };
 
+&fec0 {
+	status = "okay";
+};

arch/m68k/dts/eb_cpu5282.dts

@@ -20,3 +20,6 @@
 	status = "okay";
 };
 
+&fec0 {
+	status = "okay";
+};

arch/m68k/dts/eb_cpu5282_internal.dts

@@ -20,3 +20,6 @@
 	status = "okay";
 };
 
+&fec0 {
+	status = "okay";
+};

arch/m68k/dts/mcf5208.dtsi

@@ -8,6 +8,7 @@
 
 	aliases {
 		serial0 = &uart0;
+		fec0 = &fec0;
 	};
 
 	soc {
@@ -32,5 +33,14 @@
 			reg = <0xfc068000 0x40>;
 			status = "disabled";
 		};
+
+		fec0: ethernet@fc030000 {
+			compatible = "fsl,mcf-fec";
+			reg = <0xfc030000 0x400>;
+			mii-base = <0>;
+			max-speed = <100>;
+			timeout-loop = <50000>;
+			status = "disabled";
+		};
 	};
 };

arch/m68k/dts/mcf523x.dtsi

@@ -8,6 +8,7 @@
 
 	aliases {
 		serial0 = &uart0;
+		fec0 = &fec0;
 	};
 
 	soc {
@@ -39,6 +40,17 @@
 				reg = <0x280 0x40>;
 				status = "disabled";
 			};
+
+			fec0: ethernet@1000 {
+				compatible = "fsl,mcf-fec";
+				#address-cells=<2>;
+				#size-cells=<1>;
+				reg = <0x1000 0x400>;
+				mii-base = <0>;
+				max-speed = <100>;
+				timeout-loop = <50000>;
+				status = "disabled";
+			};
 		};
 	};
 };

arch/m68k/dts/mcf5271.dtsi

@@ -8,6 +8,7 @@
 
 	aliases {
 		serial0 = &uart0;
+		fec0 = &fec0;
 	};
 
 	soc {
@@ -39,6 +40,15 @@
 				reg = <0x280 0x40>;
 				status = "disabled";
 			};
+
+			fec0: ethernet@1000 {
+				compatible = "fsl,mcf-fec";
+				reg = <0x1000 0x400>;
+				mii-base = <0>;
+				max-speed = <100>;
+				timeout-loop = <50000>;
+				status = "disabled";
+			};
 		};
 	};
 };

arch/m68k/dts/mcf5272.dtsi

@@ -8,6 +8,7 @@
 
 	aliases {
 		serial0 = &uart0;
+		fec0 = &fec0;
 	};
 
 	soc {
@@ -33,6 +34,15 @@
 				reg = <0x140 0x40>;
 				status = "disabled";
 			};
+
+			fec0: ethernet@840 {
+				compatible = "fsl,mcf-fec";
+				reg = <0x840 0x400>;
+				mii-base = <0>;
+				max-speed = <100>;
+				timeout-loop = <50000>;
+				status = "disabled";
+			};
 		};
 	};
 };

arch/m68k/dts/mcf5275.dtsi

 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ * Copyright (C) 2019 Angelo Dureghello <angelo@sysam.it>
  */
 
 / {
@@ -8,6 +8,8 @@
 
 	aliases {
 		serial0 = &uart0;
+		fec0 = &fec0;
+		fec1 = &fec1;
 	};
 
 	soc {
@@ -39,6 +41,24 @@
 				reg = <0x280 0x40>;
 				status = "disabled";
 			};
+
+			fec0: ethernet@1000 {
+				compatible = "fsl,mcf-fec";
+				reg = <0x1000 0x800>;
+				max-speed = <100>;
+				phy-addr = <(-1)>;
+				timeout-loop = <50000>;
+				status = "disabled";
+			};
+
+			fec1: ethernet@1800 {
+				compatible = "fsl,mcf-fec";
+				reg = <0x1800 0x800>;
+				mii-base = <0>;
+				max-speed = <100>;
+				timeout-loop = <50000>;
+				status = "disabled";
+			};
 		};
 	};
 };

arch/m68k/dts/mcf5282.dtsi

@@ -8,6 +8,7 @@
 
 	aliases {
 		serial0 = &uart0;
+		fec0 = &fec0;
 	};
 
 	soc {
@@ -39,6 +40,15 @@
 				reg = <0x280 0x40>;
 				status = "disabled";
 			};
+
+			fec0: ethernet@1000 {
+				compatible = "fsl,mcf-fec";
+				reg = <0x1000 0x800>;
+				mii-base = <0>;
+				max-speed = <100>;
+				timeout-loop = <50000>;
+				status = "disabled";
+			};
 		};
 	};
 };

arch/m68k/dts/mcf5301x.dtsi

@@ -9,6 +9,8 @@
 	aliases {
 		serial0 = &uart0;
 		spi0 = &dspi0;
+		fec0 = &fec0;
+		fec1 = &fec1;
 	};
 
 	soc {
@@ -44,5 +46,24 @@
 			spi-mode = <0>;
 			status = "disabled";
 		};
+
+		fec0: ethernet@fc030000 {
+			compatible = "fsl,mcf-fec";
+			reg = <0xfc030000 0x200>;
+			mii-base = <0>;
+			max-speed = <100>;
+			phy-addr = <(-1)>;
+			timeout-loop = <50000>;
+			status = "disabled";
+		};
+
+		fec1: ethernet@fc034000 {
+			compatible = "fsl,mcf-fec";
+			reg = <0xfc034000 0x800>;
+			mii-base = <1>;
+			max-speed = <100>;
+			timeout-loop = <50000>;
+			status = "disabled";
+		};
 	};
 };

arch/m68k/dts/mcf5329.dtsi

@@ -8,6 +8,7 @@
 
 	aliases {
 		serial0 = &uart0;
+		fec0 = &fec0;
 	};
 
 	soc {
@@ -32,5 +33,14 @@
 			reg = <0xfc068000 0x40>;
 			status = "disabled";
 		};
+
+		fec0: ethernet@fc030000 {
+			compatible = "fsl,mcf-fec";
+			reg = <0xfc030000 0x800>;
+			mii-base = <0>;
+			max-speed = <100>;
+			timeout-loop = <50000>;
+			status = "disabled";
+		};
 	};
 };

arch/m68k/dts/mcf537x.dtsi

@@ -8,6 +8,7 @@
 
 	aliases {
 		serial0 = &uart0;
+		fec0 = &fec0;
 	};
 
 	soc {
@@ -32,5 +33,14 @@
 			reg = <0xfc068000 0x40>;
 			status = "disabled";
 		};
+
+		fec0: ethernet@fc030000 {
+			compatible = "fsl,mcf-fec";
+			reg = <0xfc030000 0x400>;
+			mii-base = <0>;
+			max-speed = <100>;
+			timeout-loop = <50000>;
+			status = "disabled";
+		};
 	};
 };

arch/m68k/dts/mcf5441x.dtsi

@@ -9,6 +9,8 @@
 	aliases {
 		serial0 = &uart0;
 		spi0 = &dspi0;
+		fec0 = &fec0;
+		fec1 = &fec1;
 	};
 
 	soc {
@@ -83,5 +85,23 @@
 			spi-mode = <0>;
 			status = "disabled";
 		};
+
+		fec0: ethernet@fc0d4000 {
+			compatible = "fsl,mcf-fec";
+			reg = <0xfc0d4000 0x4000>;
+			mii-base = <0>;
+			max-speed = <100>;
+			timeout-loop = <50000>;
+			status = "disabled";
+		};
+
+		fec1: ethernet@fc0d8000 {
+			compatible = "fsl,mcf-fec";
+			reg = <0xfc0d8000 0x4000>;
+			mii-base = <1>;
+			max-speed = <100>;
+			timeout-loop = <50000>;
+			status = "disabled";
+		};
 	};
 };

arch/m68k/dts/mcf5445x.dtsi

@@ -9,6 +9,8 @@
 	aliases {
 		serial0 = &uart0;
 		spi0 = &dspi0;
+		fec0 = &fec0;
+		fec1 = &fec1;
 	};
 
 	soc {
@@ -44,5 +46,23 @@
 			spi-mode = <0>;
 			status = "disabled";
 		};
+
+		fec0: ethernet@fc030000 {
+			compatible = "fsl,mcf-fec";
+			reg = <0xfc030000 0x4000>;
+			mii-base = <0>;
+			max-speed = <100>;
+			timeout-loop = <50000>;
+			status = "disabled";
+		};
+
+		fec1: ethernet@fc034000 {
+			compatible = "fsl,mcf-fec";
+			reg = <0xfc034000 0x4000>;
+			mii-base = <1>;
+			max-speed = <100>;
+			timeout-loop = <50000>;
+			status = "disabled";
+		};
 	};
 };

arch/m68k/dts/mcf54xx.dtsi

@@ -11,6 +11,8 @@
 		 * no UARTS.
 		 */
 		spi0 = &dspi0;
+		fec0 = &fec0;
+		fec1 = &fec1;
 	};
 
 	soc {
@@ -35,6 +37,36 @@
 				spi-mode = <0>;
 				status = "disabled";
 			};
+
+			fec0: ethernet@9000 {
+				compatible = "fsl,mcf-dma-fec";
+				reg = <0x9000 0x800>;
+				mii-base = <0>;
+				max-speed = <100>;
+				timeout-loop = <50000>;
+				rx-task = <0>;
+				tx-task = <1>;
+				rx-piority = <6>;
+				tx-piority = <7>;
+				rx-init = <16>;
+				tx-init = <17>;
+				status = "disabled";
+			};
+
+			fec1: ethernet@9800 {
+				compatible = "fsl,mcf-dma-fec";
+				reg = <0x9800 0x800>;
+				mii-base = <1>;
+				max-speed = <100>;
+				timeout-loop = <50000>;
+				rx-task = <2>;
+				tx-task = <3>;
+				rx-piority = <6>;
+				tx-piority = <7>;
+				rx-init = <30>;
+				tx-init = <31>;
+				status = "disabled";
+			};
 		};
 	};
 };

arch/m68k/dts/stmark2.dts

@@ -32,3 +32,12 @@
 		reg = <1>;
 	};
 };
+
+&fec0 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+	mii-base = <0>;
+};

arch/m68k/include/asm/fec.h

@@ -95,11 +95,12 @@ struct fec_info_s {
 	int phyname_init;
 	cbd_t *rxbd;		/* Rx BD */
 	cbd_t *txbd;		/* Tx BD */
-	uint rxIdx;
-	uint txIdx;
+	uint rx_idx;
+	uint tx_idx;
 	char *txbuf;
 	int initialized;
-	struct fec_info_s *next;
+	int to_loop;
+	struct mii_dev *bus;
 };
 
 #ifdef CONFIG_MCFFEC
@@ -336,12 +337,22 @@ typedef struct fec {
 #define	FEC_RESET_DELAY			100
 #define FEC_RX_TOUT			100
 
-int fecpin_setclear(struct eth_device *dev, int setclear);
+#ifdef CONFIG_MCF547x_8x
+typedef struct fec_info_dma fec_info_t;
+#define FEC_T fecdma_t
+#else
+typedef struct fec_info_s fec_info_t;
+#define FEC_T fec_t
+#endif
+
+int fecpin_setclear(fec_info_t *info, int setclear);
+int mii_discover_phy(fec_info_t *info);
+int fec_get_base_addr(int fec_idx, u32 *fec_iobase);
+int fec_get_mii_base(int fec_idx, u32 *mii_base);
 
 #ifdef CONFIG_SYS_DISCOVER_PHY
 void __mii_init(void);
 uint mii_send(uint mii_cmd);
-int mii_discover_phy(struct eth_device *dev);
 int mcffec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg);
 int mcffec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
 			u16 value);

arch/m68k/include/asm/fsl_mcdmafec.h

@@ -72,20 +72,21 @@ struct fec_info_dma {
 	int phyname_init;
 	cbd_t *rxbd;		/* Rx BD */
 	cbd_t *txbd;		/* Tx BD */
-	uint rxIdx;
-	uint txIdx;
+	uint rx_idx;
+	uint tx_idx;
 	char *txbuf;
 	int initialized;
 	struct fec_info_dma *next;
-
-	u16 rxTask;		/* DMA receive Task Number */
-	u16 txTask;		/* DMA Transmit Task Number */
-	u16 rxPri;		/* DMA Receive Priority */
-	u16 txPri;		/* DMA Transmit Priority */
-	u16 rxInit;		/* DMA Receive Initiator */
-	u16 txInit;		/* DMA Transmit Initiator */
-	u16 usedTbdIdx;		/* next transmit BD to clean */
-	u16 cleanTbdNum;	/* the number of available transmit BDs */
+	u16 rx_task;		/* DMA receive Task Number */
+	u16 tx_task;		/* DMA Transmit Task Number */
+	u16 rx_pri;		/* DMA Receive Priority */
+	u16 tx_pri;		/* DMA Transmit Priority */
+	u16 rx_init;		/* DMA Receive Initiator */
+	u16 tx_init;		/* DMA Transmit Initiator */
+	u16 used_tbd_idx;	/* next transmit BD to clean */
+	u16 clean_tbd_num;	/* the number of available transmit BDs */
+	int to_loop;
+	struct mii_dev *bus;
 };
 
 /* Bit definitions and macros for IEVENT */

arch/m68k/include/asm/immap.h

@@ -28,12 +28,6 @@
 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-#ifdef CONFIG_MCFPIT
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
-#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
-#define CONFIG_SYS_PIT_PRESCALE	(6)
-#endif
-
 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
 #define CONFIG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M520x */
@@ -62,12 +56,6 @@
 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-#ifdef CONFIG_MCFPIT
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
-#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
-#define CONFIG_SYS_PIT_PRESCALE	(6)
-#endif
-
 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
 #define CONFIG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M52277 */
@@ -91,12 +79,6 @@
 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-#ifdef CONFIG_MCFPIT
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
-#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
-#define CONFIG_SYS_PIT_PRESCALE	(6)
-#endif
-
 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
 #define CONFIG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M5235 */
@@ -285,12 +267,6 @@
 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-#ifdef CONFIG_MCFPIT
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
-#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
-#define CONFIG_SYS_PIT_PRESCALE	(6)
-#endif
-
 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
 #define CONFIG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M5301x */
@@ -315,12 +291,6 @@
 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-#ifdef CONFIG_MCFPIT
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
-#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
-#define CONFIG_SYS_PIT_PRESCALE	(6)
-#endif
-
 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
 #define CONFIG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M5329 && CONFIG_M5373 */
@@ -355,12 +325,6 @@
 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-#ifdef CONFIG_MCFPIT
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
-#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
-#define CONFIG_SYS_PIT_PRESCALE	(6)
-#endif
-
 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
 #define CONFIG_SYS_NUM_IRQS		(192)
 
@@ -391,12 +355,6 @@
 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-#ifdef CONFIG_MCFPIT
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
-#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
-#define CONFIG_SYS_PIT_PRESCALE	(6)
-#endif
-
 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
 #define CONFIG_SYS_NUM_IRQS		(128)
 

arch/m68k/lib/Makefile

@@ -12,3 +12,4 @@ obj-y	+= cache.o
 obj-y	+= interrupts.o
 obj-y	+= time.o
 obj-y	+= traps.o
+obj-y   += fec.o

arch/m68k/lib/fec.c

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com>
+ */
+
+#include <common.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_MCFFEC) || defined(CONFIG_FSLDMAFEC)
+static int fec_get_node(int fec_idx)
+{
+	char fec_alias[5] = {"fec"};
+	const char *path;
+	int node;
+
+	if (fec_idx > 1) {
+		puts("Invalid MII base index");
+		return -ENOENT;
+	}
+
+	fec_alias[3] = fec_idx + '0';
+
+	path = fdt_get_alias(gd->fdt_blob, fec_alias);
+	if (!path) {
+		puts("Invalid MII path");
+		return -ENOENT;
+	}
+
+	node = fdt_path_offset(gd->fdt_blob, path);
+	if (node < 0)
+		return -ENOENT;
+
+	return node;
+}
+
+int fec_get_fdt_prop(int fec_idx, const char *prop, u32 *value)
+{
+	int node;
+	const u32 *val;
+
+	node = fec_get_node(fec_idx);
+	if (node < 0)
+		return node;
+
+	val = fdt_getprop(gd->fdt_blob, node, prop, NULL);
+	if (!val)
+		return -ENOENT;
+
+	*value = fdt32_to_cpu(*val);
+
+	return 0;
+}
+
+int fec_get_base_addr(int fec_idx, u32 *fec_iobase)
+{
+	int node;
+	fdt_size_t size;
+	fdt_addr_t addr;
+
+	node = fec_get_node(fec_idx);
+	if (node < 0)
+		return node;
+
+	addr = fdtdec_get_addr_size(gd->fdt_blob, node, "reg", &size);
+
+	*fec_iobase = (u32)addr;
+
+	return 0;
+}
+
+int fec_get_mii_base(int fec_idx, u32 *mii_base)
+{
+	return fec_get_fdt_prop(fec_idx, "mii-base", mii_base);
+}
+
+#endif //CONFIG_MCFFEC || CONFIG_FSLDMAFEC

arch/m68k/lib/time.c

@@ -110,69 +110,6 @@ ulong get_timer(ulong base)
 
 #endif				/* CONFIG_MCFTMR */
 
-#if defined(CONFIG_MCFPIT)
-#if !defined(CONFIG_SYS_PIT_BASE)
-#	error	"CONFIG_SYS_PIT_BASE not defined!"
-#endif
-
-static unsigned short lastinc;
-
-void __udelay(unsigned long usec)
-{
-	volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_UDELAY_BASE);
-	uint tmp;
-
-	while (usec > 0) {
-		if (usec > 65000)
-			tmp = 65000;
-		else
-			tmp = usec;
-		usec = usec - tmp;
-
-		/* Set up TIMER 3 as timebase clock */
-		timerp->pcsr = PIT_PCSR_OVW;
-		timerp->pmr = 0;
-		/* set period to 1 us */
-		timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN;
-
-		timerp->pmr = tmp;
-		while (timerp->pcntr > 0) ;
-	}
-}
-
-void timer_init(void)
-{
-	volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE);
-	timestamp = 0;
-
-	/* Set up TIMER 4 as poll clock */
-	timerp->pcsr = PIT_PCSR_OVW;
-	timerp->pmr = lastinc = 0;
-	timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN;
-
-	return 0;
-}
-
-ulong get_timer(ulong base)
-{
-	unsigned short now, diff;
-	volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE);
-
-	now = timerp->pcntr;
-	diff = -(now - lastinc);
-
-	timestamp += diff;
-	lastinc = now;
-	return timestamp - base;
-}
-
-void wait_ticks(unsigned long ticks)
-{
-	u32 start = get_timer(0);
-	while (get_timer(start) < ticks) ;
-}
-#endif				/* CONFIG_MCFPIT */
-
 /*
  * This function is derived from PowerPC code (read timebase as long long).
  * On M68K it just returns the timer value.

board/freescale/m52277evb/README

@@ -79,7 +79,6 @@ RTC_DEBUG		-- define to show RTC debug message
 CONFIG_CMD_DATE		-- enable to use date feature in U-Boot
 
 CONFIG_MCFTMR		-- define to use DMA timer
-CONFIG_MCFPIT		-- define to use PIT timer
 
 CONFIG_SYS_I2C_FSL	-- define to use FSL common I2C driver
 CONFIG_SYS_I2C_SOFT	-- define for I2C bit-banged

board/freescale/m53017evb/README

@@ -88,7 +88,6 @@ CONFIG_SYS_FEC0_MIIBASE		-- Set FEC0 MII base register
 MCFFEC_TOUT_LOOP		-- set FEC timeout loop
 
 CONFIG_MCFTMR			-- define to use DMA timer
-CONFIG_MCFPIT			-- define to use PIT timer
 
 CONFIG_SYS_I2C_FSL		-- define to use FSL common I2C driver
 CONFIG_SYS_I2C_SOFT		-- define for I2C bit-banged

board/freescale/m5373evb/README

@@ -87,7 +87,6 @@ CONFIG_SYS_FEC0_MIIBASE	-- Set FEC0 MII base register
 MCFFEC_TOUT_LOOP	-- set FEC timeout loop
 
 CONFIG_MCFTMR		-- define to use DMA timer
-CONFIG_MCFPIT		-- define to use PIT timer
 
 CONFIG_SYS_I2C_FSL	-- define to use FSL common I2C driver
 CONFIG_SYS_I2C_SOFT	-- define for I2C bit-banged

board/freescale/m54455evb/README

@@ -110,7 +110,6 @@ CONFIG_SYS_ATA_STRIDE		-- define for Interval between registers
 _IO_BASE		-- define for IO base address
 
 CONFIG_MCFTMR		-- define to use DMA timer
-CONFIG_MCFPIT		-- define to use PIT timer
 
 CONFIG_SYS_FSL_I2C	-- define to use FSL common I2C driver
 CONFIG_SYS_I2C_SOFT	-- define for I2C bit-banged

board/keymile/Kconfig

@@ -76,7 +76,7 @@ config KM_COMMON_ETH_INIT
 	  Use the Ethernet initialization implemented in common code, which
 	  detects if a Piggy board is present.
 
-config PIGGY_MAC_ADRESS_OFFSET
+config PIGGY_MAC_ADDRESS_OFFSET
 	int "Piggy Address Offset"
 	default 0
 	help

board/keymile/common/common.h

@@ -121,7 +121,7 @@ struct bfticu_iomap {
 };
 
 int ethernet_present(void);
-int ivm_read_eeprom(unsigned char *buf, int len);
+int ivm_read_eeprom(unsigned char *buf, int len, int mac_address_offset);
 int ivm_analyze_eeprom(unsigned char *buf, int len);
 
 int trigger_fpga_config(void);

board/keymile/common/ivm.c

@@ -297,7 +297,7 @@ int ivm_analyze_eeprom(unsigned char *buf, int len)
 	return 0;
 }
 
-static int ivm_populate_env(unsigned char *buf, int len)
+static int ivm_populate_env(unsigned char *buf, int len, int mac_address_offset)
 {
 	unsigned char	*page2;
 	unsigned char	valbuf[MAC_STR_SZ];
@@ -309,23 +309,23 @@ static int ivm_populate_env(unsigned char *buf, int len)
 
 #ifndef CONFIG_KMTEGR1
 	/* if an offset is defined, add it */
-	process_mac(valbuf, page2, CONFIG_PIGGY_MAC_ADRESS_OFFSET, true);
+	process_mac(valbuf, page2, mac_address_offset, true);
 	env_set((char *)"ethaddr", (char *)valbuf);
 #else
 /* KMTEGR1 has a special setup. eth0 has no connection to the outside and
  * gets an locally administred MAC address, eth1 is the debug interface and
  * gets the official MAC address from the IVM
  */
-	process_mac(valbuf, page2, CONFIG_PIGGY_MAC_ADRESS_OFFSET, false);
+	process_mac(valbuf, page2, mac_address_offset, false);
 	env_set((char *)"ethaddr", (char *)valbuf);
-	process_mac(valbuf, page2, CONFIG_PIGGY_MAC_ADRESS_OFFSET, true);
+	process_mac(valbuf, page2, mac_address_offset, true);
 	env_set((char *)"eth1addr", (char *)valbuf);
 #endif
 
 	return 0;
 }
 
-int ivm_read_eeprom(unsigned char *buf, int len)
+int ivm_read_eeprom(unsigned char *buf, int len, int mac_address_offset)
 {
 	int ret;
 
@@ -339,5 +339,5 @@ int ivm_read_eeprom(unsigned char *buf, int len)
 		return -2;
 	}
 
-	return ivm_populate_env(buf, len);
+	return ivm_populate_env(buf, len, mac_address_offset);
 }

board/keymile/km83xx/km83xx.c

@@ -186,7 +186,8 @@ int board_early_init_r(void)
 
 int misc_init_r(void)
 {
-	ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+	ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+			CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
 	return 0;
 }
 

board/keymile/km_arm/MAINTAINERS

@@ -10,4 +10,3 @@ F:	configs/kmcoge5un_defconfig
 F:	configs/kmnusa_defconfig
 F:	configs/kmsugp1_defconfig
 F:	configs/kmsuv31_defconfig
-F:	configs/mgcoge3un_defconfig

board/keymile/km_arm/km_arm.c

@@ -122,26 +122,6 @@ static const u32 kwmpp_config[] = {
 
 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
 
-#if defined(CONFIG_KM_MGCOGE3UN)
-/*
- * Wait for startup OK from mgcoge3ne
- */
-static int startup_allowed(void)
-{
-	unsigned char buf;
-
-	/*
-	 * Read CIRQ16 bit (bit 0)
-	 */
-	if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
-		printf("%s: Error reading Boco\n", __func__);
-	else
-		if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
-			return 1;
-	return 0;
-}
-#endif
-
 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
 /*
  * All boards with PIGGY4 connected via a simple switch have ethernet always
@@ -199,40 +179,8 @@ static void set_bootcount_addr(void)
 
 int misc_init_r(void)
 {
-#if defined(CONFIG_KM_MGCOGE3UN)
-	char *wait_for_ne;
-	u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
-	wait_for_ne = env_get("waitforne");
-
-	if ((wait_for_ne != NULL) && (dip_switch == 0)) {
-		if (strcmp(wait_for_ne, "true") == 0) {
-			int cnt = 0;
-			int abort = 0;
-			puts("NE go: ");
-			while (startup_allowed() == 0) {
-				if (tstc()) {
-					(void) getc(); /* consume input */
-					abort = 1;
-					break;
-				}
-				udelay(200000);
-				cnt++;
-				if (cnt == 5)
-					puts("wait\b\b\b\b");
-				if (cnt == 10) {
-					cnt = 0;
-					puts("    \b\b\b\b");
-				}
-			}
-			if (abort == 1)
-				printf("\nAbort waiting for ne\n");
-			else
-				puts("OK\n");
-		}
-	}
-#endif
-
-	ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+	ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+			CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
 
 	initialize_unit_leds();
 	set_km_env();
@@ -293,7 +241,7 @@ int board_init(void)
 
 int board_late_init(void)
 {
-#if (defined(CONFIG_KM_COGE5UN) | defined(CONFIG_KM_MGCOGE3UN))
+#if defined(CONFIG_KM_COGE5UN)
 	u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
 
 	/* if pin 1 do full erase */

board/keymile/kmp204x/kmp204x.c

@@ -196,7 +196,8 @@ int misc_init_r(void)
 		}
 	}
 
-	ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+	ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+			CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
 	return 0;
 }
 

cmd/Kconfig

@@ -364,8 +364,8 @@ config CMD_BOOTMENU
 	help
 	  Add an ANSI terminal boot menu command.
 
-config CMD_DTIMG
-	bool "dtimg"
+config CMD_ADTIMG
+	bool "adtimg"
 	help
 	  Android DTB/DTBO image manipulation commands. Read dtb/dtbo files from
 	  image into RAM, dump image structure information, etc. Those dtb/dtbo

cmd/Makefile

@@ -47,7 +47,7 @@ obj-$(CONFIG_CMD_SOUND) += sound.o
 ifdef CONFIG_POST
 obj-$(CONFIG_CMD_DIAG) += diag.o
 endif
-obj-$(CONFIG_CMD_DTIMG) += dtimg.o
+obj-$(CONFIG_CMD_ADTIMG) += adtimg.o
 obj-$(CONFIG_CMD_ECHO) += echo.o
 obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o
 obj-$(CONFIG_CMD_EEPROM) += eeprom.o

cmd/adtimg.c

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018 Linaro Ltd.
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ * Eugeniu Rosca <rosca.eugeniu@gmail.com>
+ */
+
+#include <env.h>
+#include <image-android-dt.h>
+#include <common.h>
+
+#define OPT_INDEX	"--index"
+
+/*
+ * Current/working DTB/DTBO Android image address.
+ * Similar to 'working_fdt' variable in 'fdt' command.
+ */
+static ulong working_img;
+
+static int do_adtimg_addr(cmd_tbl_t *cmdtp, int flag, int argc,
+			  char * const argv[])
+{
+	char *endp;
+	ulong hdr_addr;
+
+	if (argc != 2)
+		return CMD_RET_USAGE;
+
+	hdr_addr = simple_strtoul(argv[1], &endp, 16);
+	if (*endp != '\0') {
+		printf("Error: Wrong image address '%s'\n", argv[1]);
+		return CMD_RET_FAILURE;
+	}
+
+	/*
+	 * Allow users to set an address prior to copying the DTB/DTBO
+	 * image to that same address, i.e. skip header verification.
+	 */
+
+	working_img = hdr_addr;
+	return CMD_RET_SUCCESS;
+}
+
+static int adtimg_check_working_img(void)
+{
+	if (!working_img) {
+		printf("Error: Please, call 'adtimg addr <addr>'. Aborting!\n");
+		return CMD_RET_FAILURE;
+	}
+
+	if (!android_dt_check_header(working_img)) {
+		printf("Error: Invalid image header at 0x%lx\n", working_img);
+		return CMD_RET_FAILURE;
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_adtimg_dump(cmd_tbl_t *cmdtp, int flag, int argc,
+			  char * const argv[])
+{
+	if (argc != 1)
+		return CMD_RET_USAGE;
+
+	if (adtimg_check_working_img() != CMD_RET_SUCCESS)
+		return CMD_RET_FAILURE;
+
+	android_dt_print_contents(working_img);
+
+	return CMD_RET_SUCCESS;
+}
+
+static int adtimg_getopt_u32(char * const opt, char * const name, u32 *optval)
+{
+	char *endp, *str;
+	u32 val;
+
+	if (!opt || !name || !optval)
+		return CMD_RET_FAILURE;
+
+	str = strchr(opt, '=');
+	if (!str) {
+		printf("Error: Option '%s' not followed by '='\n", name);
+		return CMD_RET_FAILURE;
+	}
+
+	if (*++str == '\0') {
+		printf("Error: Option '%s=' not followed by value\n", name);
+		return CMD_RET_FAILURE;
+	}
+
+	val = simple_strtoul(str, &endp, 0);
+	if (*endp != '\0') {
+		printf("Error: Wrong integer value '%s=%s'\n", name, str);
+		return CMD_RET_FAILURE;
+	}
+
+	*optval = val;
+	return CMD_RET_SUCCESS;
+}
+
+static int adtimg_getopt_index(int argc, char * const argv[], u32 *index,
+			       char **avar, char **svar)
+{
+	int ret;
+
+	if (!argv || !avar || !svar)
+		return CMD_RET_FAILURE;
+
+	if (argc > 3) {
+		printf("Error: Unexpected argument '%s'\n", argv[3]);
+		return CMD_RET_FAILURE;
+	}
+
+	ret = adtimg_getopt_u32(argv[0], OPT_INDEX, index);
+	if (ret != CMD_RET_SUCCESS)
+		return ret;
+
+	if (argc > 1)
+		*avar = argv[1];
+	if (argc > 2)
+		*svar = argv[2];
+
+	return CMD_RET_SUCCESS;
+}
+
+static int adtimg_get_dt_by_index(int argc, char * const argv[])
+{
+	ulong addr;
+	u32 index, size;
+	int ret;
+	char *avar = NULL, *svar = NULL;
+
+	ret = adtimg_getopt_index(argc, argv, &index, &avar, &svar);
+	if (ret != CMD_RET_SUCCESS)
+		return ret;
+
+	if (!android_dt_get_fdt_by_index(working_img, index, &addr, &size))
+		return CMD_RET_FAILURE;
+
+	if (avar && svar) {
+		ret = env_set_hex(avar, addr);
+		if (ret) {
+			printf("Error: Can't set '%s' to 0x%lx\n", avar, addr);
+			return CMD_RET_FAILURE;
+		}
+		ret = env_set_hex(svar, size);
+		if (ret) {
+			printf("Error: Can't set '%s' to 0x%x\n", svar, size);
+			return CMD_RET_FAILURE;
+		}
+	} else if (avar) {
+		ret = env_set_hex(avar, addr);
+		if (ret) {
+			printf("Error: Can't set '%s' to 0x%lx\n", avar, addr);
+			return CMD_RET_FAILURE;
+		}
+		printf("0x%x (%d)\n", size, size);
+	} else {
+		printf("0x%lx, 0x%x (%d)\n", addr, size, size);
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+static int adtimg_get_dt(int argc, char * const argv[])
+{
+	if (argc < 2) {
+		printf("Error: No options passed to '%s'\n", argv[0]);
+		return CMD_RET_FAILURE;
+	}
+
+	/* Strip off leading 'dt' command argument */
+	argc--;
+	argv++;
+
+	if (!strncmp(argv[0], OPT_INDEX, sizeof(OPT_INDEX) - 1))
+		return adtimg_get_dt_by_index(argc, argv);
+
+	printf("Error: Option '%s' not supported\n", argv[0]);
+	return CMD_RET_FAILURE;
+}
+
+static int do_adtimg_get(cmd_tbl_t *cmdtp, int flag, int argc,
+			 char * const argv[])
+{
+	if (argc < 2) {
+		printf("Error: No arguments passed to '%s'\n", argv[0]);
+		return CMD_RET_FAILURE;
+	}
+
+	if (adtimg_check_working_img() != CMD_RET_SUCCESS)
+		return CMD_RET_FAILURE;
+
+	/* Strip off leading 'get' command argument */
+	argc--;
+	argv++;
+
+	if (!strcmp(argv[0], "dt"))
+		return adtimg_get_dt(argc, argv);
+
+	printf("Error: Wrong argument '%s'\n", argv[0]);
+	return CMD_RET_FAILURE;
+}
+
+static cmd_tbl_t cmd_adtimg_sub[] = {
+	U_BOOT_CMD_MKENT(addr, CONFIG_SYS_MAXARGS, 1, do_adtimg_addr, "", ""),
+	U_BOOT_CMD_MKENT(dump, CONFIG_SYS_MAXARGS, 1, do_adtimg_dump, "", ""),
+	U_BOOT_CMD_MKENT(get, CONFIG_SYS_MAXARGS, 1, do_adtimg_get, "", ""),
+};
+
+static int do_adtimg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	cmd_tbl_t *cp;
+
+	cp = find_cmd_tbl(argv[1], cmd_adtimg_sub, ARRAY_SIZE(cmd_adtimg_sub));
+
+	/* Strip off leading 'adtimg' command argument */
+	argc--;
+	argv++;
+
+	if (!cp || argc > cp->maxargs)
+		return CMD_RET_USAGE;
+	if (flag == CMD_FLAG_REPEAT && !cmd_is_repeatable(cp))
+		return CMD_RET_SUCCESS;
+
+	return cp->cmd(cmdtp, flag, argc, argv);
+}
+
+U_BOOT_CMD(
+	adtimg, CONFIG_SYS_MAXARGS, 0, do_adtimg,
+	"manipulate dtb/dtbo Android image",
+	"addr <addr> - Set image location to <addr>\n"
+	"adtimg dump        - Print out image contents\n"
+	"adtimg get dt --index=<index> [avar [svar]]         - Get DT address/size by index\n"
+	"\n"
+	"Legend:\n"
+	"  - <addr>: DTB/DTBO image address (hex) in RAM\n"
+	"  - <index>: index (hex/dec) of desired DT in the image\n"
+	"  - <avar>: variable name to contain DT address (hex)\n"
+	"  - <svar>: variable name to contain DT size (hex)"
+);

cmd/dtimg.c

-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2018 Linaro Ltd.
- * Sam Protsenko <semen.protsenko@linaro.org>
- */
-
-#include <env.h>
-#include <image-android-dt.h>
-#include <common.h>
-
-enum cmd_dtimg_info {
-	CMD_DTIMG_START = 0,
-	CMD_DTIMG_SIZE,
-};
-
-static int do_dtimg_dump(cmd_tbl_t *cmdtp, int flag, int argc,
-			 char * const argv[])
-{
-	char *endp;
-	ulong hdr_addr;
-
-	if (argc != 2)
-		return CMD_RET_USAGE;
-
-	hdr_addr = simple_strtoul(argv[1], &endp, 16);
-	if (*endp != '\0') {
-		printf("Error: Wrong image address\n");
-		return CMD_RET_FAILURE;
-	}
-
-	if (!android_dt_check_header(hdr_addr)) {
-		printf("Error: DT image header is incorrect\n");
-		return CMD_RET_FAILURE;
-	}
-
-	android_dt_print_contents(hdr_addr);
-
-	return CMD_RET_SUCCESS;
-}
-
-static int dtimg_get_fdt(int argc, char * const argv[], enum cmd_dtimg_info cmd)
-{
-	ulong hdr_addr;
-	u32 index;
-	char *endp;
-	ulong fdt_addr;
-	u32 fdt_size;
-	char buf[65];
-
-	if (argc != 4)
-		return CMD_RET_USAGE;
-
-	hdr_addr = simple_strtoul(argv[1], &endp, 16);
-	if (*endp != '\0') {
-		printf("Error: Wrong image address\n");
-		return CMD_RET_FAILURE;
-	}
-
-	if (!android_dt_check_header(hdr_addr)) {
-		printf("Error: DT image header is incorrect\n");
-		return CMD_RET_FAILURE;
-	}
-
-	index = simple_strtoul(argv[2], &endp, 0);
-	if (*endp != '\0') {
-		printf("Error: Wrong index\n");
-		return CMD_RET_FAILURE;
-	}
-
-	if (!android_dt_get_fdt_by_index(hdr_addr, index, &fdt_addr, &fdt_size))
-		return CMD_RET_FAILURE;
-
-	switch (cmd) {
-	case CMD_DTIMG_START:
-		snprintf(buf, sizeof(buf), "%lx", fdt_addr);
-		break;
-	case CMD_DTIMG_SIZE:
-		snprintf(buf, sizeof(buf), "%x", fdt_size);
-		break;
-	default:
-		printf("Error: Unknown cmd_dtimg_info value: %d\n", cmd);
-		return CMD_RET_FAILURE;
-	}
-
-	env_set(argv[3], buf);
-
-	return CMD_RET_SUCCESS;
-}
-
-static int do_dtimg_start(cmd_tbl_t *cmdtp, int flag, int argc,
-			  char * const argv[])
-{
-	return dtimg_get_fdt(argc, argv, CMD_DTIMG_START);
-}
-
-static int do_dtimg_size(cmd_tbl_t *cmdtp, int flag, int argc,
-			 char * const argv[])
-{
-	return dtimg_get_fdt(argc, argv, CMD_DTIMG_SIZE);
-}
-
-static cmd_tbl_t cmd_dtimg_sub[] = {
-	U_BOOT_CMD_MKENT(dump, 2, 0, do_dtimg_dump, "", ""),
-	U_BOOT_CMD_MKENT(start, 4, 0, do_dtimg_start, "", ""),
-	U_BOOT_CMD_MKENT(size, 4, 0, do_dtimg_size, "", ""),
-};
-
-static int do_dtimg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	cmd_tbl_t *cp;
-
-	cp = find_cmd_tbl(argv[1], cmd_dtimg_sub, ARRAY_SIZE(cmd_dtimg_sub));
-
-	/* Strip off leading 'dtimg' command argument */
-	argc--;
-	argv++;
-
-	if (!cp || argc > cp->maxargs)
-		return CMD_RET_USAGE;
-	if (flag == CMD_FLAG_REPEAT && !cmd_is_repeatable(cp))
-		return CMD_RET_SUCCESS;
-
-	return cp->cmd(cmdtp, flag, argc, argv);
-}
-
-U_BOOT_CMD(
-	dtimg, CONFIG_SYS_MAXARGS, 0, do_dtimg,
-	"manipulate dtb/dtbo Android image",
-	"dump <addr>\n"
-	"    - parse specified image and print its structure info\n"
-	"      <addr>: image address in RAM, in hex\n"
-	"dtimg start <addr> <index> <varname>\n"
-	"    - get address (hex) of FDT in the image, by index\n"
-	"      <addr>: image address in RAM, in hex\n"
-	"      <index>: index of desired FDT in the image\n"
-	"      <varname>: name of variable where to store address of FDT\n"
-	"dtimg size <addr> <index> <varname>\n"
-	"    - get size (hex, bytes) of FDT in the image, by index\n"
-	"      <addr>: image address in RAM, in hex\n"
-	"      <index>: index of desired FDT in the image\n"
-	"      <varname>: name of variable where to store size of FDT"
-);

cmd/eeprom.c

@@ -308,7 +308,7 @@ static int eeprom_execute_command(enum eeprom_action action, int i2c_bus,
 {
 	int rcode = 0;
 	const char *const fmt =
-		"\nEEPROM @0x%lX %s: addr %08lx  off %04lx  count %ld ... ";
+		"\nEEPROM @0x%lX %s: addr 0x%08lx  off 0x%04lx  count %ld ... ";
 #ifdef CONFIG_CMD_EEPROM_LAYOUT
 	struct eeprom_layout layout;
 #endif

common/Makefile

@@ -117,7 +117,7 @@ obj-$(CONFIG_IO_TRACE) += iotrace.o
 obj-y += memsize.o
 obj-y += stdio.o
 
-obj-$(CONFIG_CMD_DTIMG) += image-android-dt.o
+obj-$(CONFIG_CMD_ADTIMG) += image-android-dt.o
 
 ifdef CONFIG_CMD_EEPROM_LAYOUT
 obj-y += eeprom/eeprom_field.o eeprom/eeprom_layout.o

common/init/board_init.c

@@ -18,6 +18,19 @@ __weak void arch_setup_gd(struct global_data *gd_ptr)
 }
 #endif /* !CONFIG_X86 && !CONFIG_ARM */
 
+/**
+ * This function is called from board_init_f_init_reserve to set up
+ * gd->start_addr_sp for stack protection if not already set otherwise
+ */
+__weak void board_init_f_init_stack_protection_addr(ulong base)
+{
+#if CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE)
+	/* set up stack pointer for stack usage if not set yet */
+	if (!gd->start_addr_sp)
+		gd->start_addr_sp = base;
+#endif
+}
+
 /**
  * This function is called after the position of the initial stack is
  * determined in gd->start_addr_sp. Boards can override it to set up
@@ -129,6 +142,10 @@ void board_init_f_init_reserve(ulong base)
 #if !defined(CONFIG_ARM)
 	arch_setup_gd(gd_ptr);
 #endif
+
+	if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE))
+		board_init_f_init_stack_protection_addr(base);
+
 	/* next alloc will be higher by one GD plus 16-byte alignment */
 	base += roundup(sizeof(struct global_data), 16);
 

configs/M5208EVBE_defconfig

@@ -21,4 +21,6 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
 CONFIG_MII=y

configs/M5235EVB_Flash32_defconfig

@@ -26,4 +26,6 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
 CONFIG_MII=y

configs/M5235EVB_defconfig

@@ -26,4 +26,6 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
 CONFIG_MII=y

configs/M5272C3_defconfig

@@ -22,4 +22,6 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
 CONFIG_MII=y

configs/M5275EVB_defconfig

@@ -23,4 +23,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
 CONFIG_MII=y

configs/M5282EVB_defconfig

@@ -22,4 +22,6 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
 CONFIG_MII=y

configs/M53017EVB_defconfig

@@ -24,4 +24,6 @@ CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
 CONFIG_MII=y

configs/M5329AFEE_defconfig

@@ -25,5 +25,7 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_MCFFEC=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_MII=y