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体验新版 GitCode,发现更多精彩内容 >>
提交
ee58ea26
编写于
11月 02, 2006
作者:
W
Wolfgang Denk
提交者:
Wolfgang Denk
11月 02, 2006
浏览文件
操作
浏览文件
下载
差异文件
Merge with /home/tur/proj/uboot_linux_v38b/u-boot
上级
c5920044
25721b5c
变更
13
隐藏空白更改
内联
并排
Showing
13 changed file
with
198 addition
and
262 deletion
+198
-262
Makefile
Makefile
+1
-1
board/bc3450/bc3450.c
board/bc3450/bc3450.c
+2
-3
board/emk/top5200/top5200.c
board/emk/top5200/top5200.c
+2
-4
board/esd/cpci5200/cpci5200.c
board/esd/cpci5200/cpci5200.c
+3
-5
board/esd/pf5200/pf5200.c
board/esd/pf5200/pf5200.c
+5
-7
board/icecube/icecube.c
board/icecube/icecube.c
+3
-5
board/inka4x0/inka4x0.c
board/inka4x0/inka4x0.c
+5
-10
board/tqm5200/tqm5200.c
board/tqm5200/tqm5200.c
+3
-5
board/v38b/ethaddr.c
board/v38b/ethaddr.c
+25
-66
board/v38b/u-boot.lds
board/v38b/u-boot.lds
+3
-0
board/v38b/v38b.c
board/v38b/v38b.c
+56
-48
include/configs/v38b.h
include/configs/v38b.h
+82
-107
include/mpc5xxx.h
include/mpc5xxx.h
+8
-1
未找到文件。
Makefile
浏览文件 @
ee58ea26
...
...
@@ -412,7 +412,7 @@ icecube_5100_config: unconfig
@
$(MKCONFIG)
-a
IceCube ppc mpc5xxx icecube
v38b_config
:
unconfig
@
./mkconfig
-a
V38B
ppc mpc5xxx v38b
@
./mkconfig
-a
v38b
ppc mpc5xxx v38b
inka4x0_config
:
unconfig
@
$(MKCONFIG)
inka4x0 ppc mpc5xxx inka4x0
...
...
board/bc3450/bc3450.c
浏览文件 @
ee58ea26
...
...
@@ -295,7 +295,6 @@ void pci_init_board(void)
#endif
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
#define GPIO_PSC1_4 0x01000000UL
void
init_ide_reset
(
void
)
{
...
...
@@ -311,9 +310,9 @@ void ide_set_reset (int idereset)
debug
(
"ide_reset(%d)
\n
"
,
idereset
);
if
(
idereset
)
{
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
&=
~
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
&=
~
GPIO_PSC1_4
;
}
else
{
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
|=
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
|=
GPIO_PSC1_4
;
}
}
#endif
/* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
...
...
board/emk/top5200/top5200.c
浏览文件 @
ee58ea26
...
...
@@ -186,8 +186,6 @@ void pci_init_board(void)
*****************************************************************************/
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
#define GPIO_PSC1_4 0x01000000UL
void
init_ide_reset
(
void
)
{
debug
(
"init_ide_reset
\n
"
);
...
...
@@ -202,9 +200,9 @@ void ide_set_reset (int idereset)
debug
(
"ide_reset(%d)
\n
"
,
idereset
);
if
(
idereset
)
{
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
&=
~
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
&=
~
GPIO_PSC1_4
;
}
else
{
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
|=
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
|=
GPIO_PSC1_4
;
}
}
#endif
/* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
board/esd/cpci5200/cpci5200.c
浏览文件 @
ee58ea26
...
...
@@ -199,8 +199,6 @@ void pci_init_board(void
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
#define GPIO_PSC1_4 0x01000000UL
void
init_ide_reset
(
void
)
{
debug
(
"init_ide_reset
\n
"
);
...
...
@@ -215,9 +213,9 @@ void ide_set_reset(int idereset)
debug
(
"ide_reset(%d)
\n
"
,
idereset
);
if
(
idereset
)
{
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
&=
~
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
&=
~
GPIO_PSC1_4
;
}
else
{
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
|=
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
|=
GPIO_PSC1_4
;
}
}
#endif
/* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
...
...
@@ -242,7 +240,7 @@ void init_ata_reset(void)
debug
(
"init_ata_reset
\n
"
);
/* Configure GPIO_WU6 as GPIO output for ATA reset */
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
|=
GPIO_WU6
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
|=
GPIO_WU6
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_ENABLE
|=
GPIO_WU6
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DIR
|=
GPIO_WU6
;
__asm__
volatile
(
"sync"
);
...
...
board/esd/pf5200/pf5200.c
浏览文件 @
ee58ea26
...
...
@@ -199,8 +199,6 @@ void pci_init_board(void
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
#define GPIO_PSC1_4 0x01000000UL
void
init_ide_reset
(
void
)
{
debug
(
"init_ide_reset
\n
"
);
...
...
@@ -215,9 +213,9 @@ void ide_set_reset(int idereset)
debug
(
"ide_reset(%d)
\n
"
,
idereset
);
if
(
idereset
)
{
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
&=
~
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
&=
~
GPIO_PSC1_4
;
}
else
{
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
|=
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
|=
GPIO_PSC1_4
;
}
}
#endif
/* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
...
...
@@ -242,7 +240,7 @@ void init_power_switch(void)
debug
(
"init_power_switch
\n
"
);
/* Configure GPIO_WU6 as GPIO output for ATA reset */
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
|=
GPIO_WU6
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
|=
GPIO_WU6
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_ENABLE
|=
GPIO_WU6
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DIR
|=
GPIO_WU6
;
__asm__
volatile
(
"sync"
);
...
...
@@ -272,10 +270,10 @@ void power_set_reset(int power)
debug
(
"ide_set_reset(%d)
\n
"
,
power
);
if
(
power
)
{
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
&=
~
GPIO_WU6
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
&=
~
GPIO_WU6
;
*
(
vu_long
*
)
MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT
&=
~
GPIO_USB9
;
}
else
{
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
|=
GPIO_WU6
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
|=
GPIO_WU6
;
if
((
*
(
vu_long
*
)
MPC5XXX_INTERRUPT_GPIO_STATUS
&
GPIO_USB9S
)
==
0
)
{
*
(
vu_long
*
)
MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT
|=
...
...
board/icecube/icecube.c
浏览文件 @
ee58ea26
...
...
@@ -308,8 +308,6 @@ void pci_init_board(void)
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
#define GPIO_PSC1_4 0x01000000UL
void
init_ide_reset
(
void
)
{
debug
(
"init_ide_reset
\n
"
);
...
...
@@ -318,7 +316,7 @@ void init_ide_reset (void)
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_ENABLE
|=
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DIR
|=
GPIO_PSC1_4
;
/* Deassert reset */
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
|=
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
|=
GPIO_PSC1_4
;
}
void
ide_set_reset
(
int
idereset
)
...
...
@@ -326,11 +324,11 @@ void ide_set_reset (int idereset)
debug
(
"ide_reset(%d)
\n
"
,
idereset
);
if
(
idereset
)
{
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
&=
~
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
&=
~
GPIO_PSC1_4
;
/* Make a delay. MPC5200 spec says 25 usec min */
udelay
(
500000
);
}
else
{
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
|=
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
|=
GPIO_PSC1_4
;
}
}
#endif
/* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
board/inka4x0/inka4x0.c
浏览文件 @
ee58ea26
...
...
@@ -173,9 +173,6 @@ void flash_preinit(void)
*
(
vu_long
*
)
MPC5XXX_BOOTCS_CFG
&=
~
0x1
;
/* clear RO */
}
#define GPIO_WKUP_7 0x80000000UL
#define GPIO_PSC3_9 0x04000000UL
int
misc_init_f
(
void
)
{
uchar
tmp
[
10
];
...
...
@@ -218,13 +215,13 @@ int misc_init_f (void)
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DIR
|=
0xc4000000
;
/* Set LR mirror bit because it is low-active */
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
|=
GPIO_WKUP_7
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA_O
|=
GPIO_WKUP_7
;
/*
* Reset Coral-P graphics controller
*/
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_ENABLE
|=
GPIO_PSC3_9
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DIR
|=
GPIO_PSC3_9
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
|=
GPIO_PSC3_9
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
|=
GPIO_PSC3_9
;
return
0
;
}
...
...
@@ -241,8 +238,6 @@ void pci_init_board(void)
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
#define GPIO_PSC1_4 0x01000000UL
void
init_ide_reset
(
void
)
{
debug
(
"init_ide_reset
\n
"
);
...
...
@@ -251,7 +246,7 @@ void init_ide_reset (void)
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_ENABLE
|=
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DIR
|=
GPIO_PSC1_4
;
/* Deassert reset */
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
|=
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
|=
GPIO_PSC1_4
;
}
void
ide_set_reset
(
int
idereset
)
...
...
@@ -259,11 +254,11 @@ void ide_set_reset (int idereset)
debug
(
"ide_reset(%d)
\n
"
,
idereset
);
if
(
idereset
)
{
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
&=
~
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
&=
~
GPIO_PSC1_4
;
/* Make a delay. MPC5200 spec says 25 usec min */
udelay
(
500000
);
}
else
{
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
|=
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
|=
GPIO_PSC1_4
;
}
}
#endif
/* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
board/tqm5200/tqm5200.c
浏览文件 @
ee58ea26
...
...
@@ -341,9 +341,7 @@ void pci_init_board(void)
#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
#define SM501_GPIO_DATA_HIGH 0x00010004UL
#define SM501_GPIO_51 0x00080000UL
#else
#define GPIO_PSC1_4 0x01000000UL
#endif
#endif
/* CONFIG MINIFAP */
void
init_ide_reset
(
void
)
{
...
...
@@ -381,9 +379,9 @@ void ide_set_reset (int idereset)
}
#else
if
(
idereset
)
{
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
&=
~
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
&=
~
GPIO_PSC1_4
;
}
else
{
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
|=
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
|=
GPIO_PSC1_4
;
}
#endif
}
...
...
board/v38b/ethaddr.c
浏览文件 @
ee58ea26
/*
*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
...
...
@@ -25,48 +24,13 @@
#include <common.h>
#include <mpc5xxx.h>
#define GPIO_ENABLE (MPC5XXX_WU_GPIO)
/* Open Drain Emulation Register */
#define GPIO_ODR (MPC5XXX_WU_GPIO + 0x04)
/* Data Direction Register */
#define GPIO_DDR (MPC5XXX_WU_GPIO + 0x08)
/* Data Value Out Register */
#define GPIO_DVOR (MPC5XXX_WU_GPIO + 0x0C)
/* Interrupt Enable Register */
#define GPIO_IER (MPC5XXX_WU_GPIO + 0x10)
/* Individual Interrupt Enable Register */
#define GPIO_IIER (MPC5XXX_WU_GPIO + 0x14)
/* Interrupt Type Register */
#define GPIO_ITR (MPC5XXX_WU_GPIO + 0x18)
/* Master Enable Register */
#define GPIO_MER (MPC5XXX_WU_GPIO + 0x1C)
/* Data Input Value Register */
#define GPIO_DIVR (MPC5XXX_WU_GPIO + 0x20)
/* Status Register */
#define GPIO_SR (MPC5XXX_WU_GPIO + 0x24)
#define PSC6_0 0x10000000
#define WKUP_7 0x80000000
/* For NS4 A/B board define WKUP_7, for V38B board PSC_6 */
#define GPIO_PIN PSC6_0
/* For the V38B board the pin is GPIO_PSC_6 */
#define GPIO_PIN GPIO_PSC6_0
#define NO_ERROR 0
#define ERR_NO_NUMBER 1
#define ERR_BAD_NUMBER 2
typedef
volatile
unsigned
long
GPIO_REG
;
typedef
GPIO_REG
*
GPIO_REG_PTR
;
static
int
is_high
(
void
);
static
int
check_device
(
void
);
static
void
io_out
(
int
value
);
...
...
@@ -79,33 +43,34 @@ static void write_byte(unsigned char command);
void
read_2501_memory
(
unsigned
char
*
psernum
,
unsigned
char
*
perr
);
void
board_get_enetaddr
(
uchar
*
enetaddr
);
static
int
is_high
()
{
return
(
*
((
vu_long
*
)
GPIO_DIVR
)
&
GPIO_PIN
);
return
(
*
((
vu_long
*
)
MPC5XXX_WU_GPIO_DATA_I
)
&
GPIO_PIN
);
}
static
void
io_out
(
int
value
)
{
if
(
value
)
*
((
vu_long
*
)
GPIO_DVOR
)
|=
GPIO_PIN
;
*
((
vu_long
*
)
MPC5XXX_WU_GPIO_DATA_O
)
|=
GPIO_PIN
;
else
*
((
vu_long
*
)
GPIO_DVOR
)
&=
~
GPIO_PIN
;
*
((
vu_long
*
)
MPC5XXX_WU_GPIO_DATA_O
)
&=
~
GPIO_PIN
;
}
static
void
io_input
()
{
*
((
vu_long
*
)
GPIO_DD
R
)
&=
~
GPIO_PIN
;
*
((
vu_long
*
)
MPC5XXX_WU_GPIO_DI
R
)
&=
~
GPIO_PIN
;
udelay
(
3
);
/* allow input to settle */
}
static
void
io_output
()
{
*
((
vu_long
*
)
GPIO_DD
R
)
|=
GPIO_PIN
;
*
((
vu_long
*
)
MPC5XXX_WU_GPIO_DI
R
)
|=
GPIO_PIN
;
}
static
void
init_gpio
()
{
*
((
vu_long
*
)
GPIO_ENABLE
)
|=
GPIO_PIN
;
/* Enable appropriate pin */
*
((
vu_long
*
)
MPC5XXX_WU_
GPIO_ENABLE
)
|=
GPIO_PIN
;
/* Enable appropriate pin */
}
void
read_2501_memory
(
unsigned
char
*
psernum
,
unsigned
char
*
perr
)
...
...
@@ -117,8 +82,8 @@ void read_2501_memory(unsigned char *psernum, unsigned char *perr)
*
perr
=
0
;
crcval
=
0
;
for
(
i
=
0
;
i
<
NBYTES
;
i
++
)
for
(
i
=
0
;
i
<
NBYTES
;
i
++
)
buf
[
i
]
=
0
;
if
(
!
check_device
())
*
perr
=
ERR_NO_NUMBER
;
...
...
@@ -130,10 +95,10 @@ void read_2501_memory(unsigned char *psernum, unsigned char *perr)
write_byte
(
0x00
);
read_byte
(
&
crcval
);
/* Read CRC of address and command */
for
(
i
=
0
;
i
<
NBYTES
;
i
++
)
read_byte
(
&
buf
[
i
]
);
for
(
i
=
0
;
i
<
NBYTES
;
i
++
)
read_byte
(
&
buf
[
i
]
);
}
if
(
strncmp
((
const
char
*
)
&
buf
[
11
],
"MAREL IEEE 802.3"
,
16
))
{
if
(
strncmp
((
const
char
*
)
&
buf
[
11
],
"MAREL IEEE 802.3"
,
16
))
{
*
perr
=
ERR_BAD_NUMBER
;
psernum
[
0
]
=
0x00
;
psernum
[
1
]
=
0xE0
;
...
...
@@ -141,8 +106,7 @@ void read_2501_memory(unsigned char *psernum, unsigned char *perr)
psernum
[
3
]
=
0xFF
;
psernum
[
4
]
=
0xFF
;
psernum
[
5
]
=
0xFF
;
}
else
{
}
else
{
psernum
[
0
]
=
0x00
;
psernum
[
1
]
=
0xE0
;
psernum
[
2
]
=
0xEE
;
...
...
@@ -173,27 +137,23 @@ static void write_byte(unsigned char command)
{
char
i
;
for
(
i
=
0
;
i
<
8
;
i
++
)
{
for
(
i
=
0
;
i
<
8
;
i
++
)
{
/* 1 us to 15 us low pulse starts bit slot */
/* Start with high pulse for 3 us */
io_input
();
udelay
(
3
);
io_out
(
0
);
io_output
();
udelay
(
3
);
if
(
command
&
0x01
)
{
/* 60 us high for 1-bit */
io_input
();
udelay
(
60
);
}
else
{
}
else
/* 60 us low for 0-bit */
udelay
(
60
);
}
/* Leave pin as input */
io_input
();
...
...
@@ -201,11 +161,11 @@ static void write_byte(unsigned char command)
}
}
static
void
read_byte
(
unsigned
char
*
data
)
static
void
read_byte
(
unsigned
char
*
data
)
{
unsigned
char
i
,
rdat
=
0
;
for
(
i
=
0
;
i
<
8
;
i
++
)
{
for
(
i
=
0
;
i
<
8
;
i
++
)
{
/* read one bit from one-wire device */
/* 1 - 15 us low starts bit slot */
...
...
@@ -233,22 +193,21 @@ static void read_byte(unsigned char *data)
void
board_get_enetaddr
(
uchar
*
enetaddr
)
{
unsigned
char
sn
[
6
],
err
=
NO_ERROR
;
unsigned
char
sn
[
6
],
err
=
NO_ERROR
;
init_gpio
();
read_2501_memory
(
sn
,
&
err
);
if
(
err
==
NO_ERROR
)
{
sprintf
(
enetaddr
,
"%02x:%02x:%02x:%02x:%02x:%02x"
,
sprintf
(
(
char
*
)
enetaddr
,
"%02x:%02x:%02x:%02x:%02x:%02x"
,
sn
[
0
],
sn
[
1
],
sn
[
2
],
sn
[
3
],
sn
[
4
],
sn
[
5
]);
printf
(
"MAC address: %s
\n
"
,
enetaddr
);
setenv
(
"ethaddr"
,
enetaddr
);
}
else
{
sprintf
(
enetaddr
,
"00:01:02:03:04:05"
);
setenv
(
"ethaddr"
,
(
char
*
)
enetaddr
);
}
else
{
sprintf
((
char
*
)
enetaddr
,
"00:01:02:03:04:05"
);
printf
(
"Error reading MAC address.
\n
"
);
printf
(
"Setting default to %s
\n
"
,
enetaddr
);
setenv
(
"ethaddr"
,
enetaddr
);
setenv
(
"ethaddr"
,
(
char
*
)
enetaddr
);
}
}
board/v38b/u-boot.lds
浏览文件 @
ee58ea26
...
...
@@ -61,6 +61,7 @@ SECTIONS
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
...
...
@@ -93,11 +94,13 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
...
...
board/v38b/v38b.c
浏览文件 @
ee58ea26
...
...
@@ -28,43 +28,44 @@
#include <mpc5xxx.h>
#include <asm/processor.h>
#ifndef CFG_RAMBOOT
static
void
sdram_start
(
int
hi_addr
)
{
long
hi_addr_bit
=
hi_addr
?
0x01000000
:
0
;
/* unlock mode register */
*
(
vu_long
*
)
MPC5XXX_SDRAM_CTRL
=
SDRAM_CONTROL
|
0x80000000
|
hi_addr_bit
;
*
(
vu_long
*
)
MPC5XXX_SDRAM_CTRL
=
SDRAM_CONTROL
|
0x80000000
|
hi_addr_bit
;
__asm__
volatile
(
"sync"
);
/* precharge all banks */
*
(
vu_long
*
)
MPC5XXX_SDRAM_CTRL
=
SDRAM_CONTROL
|
0x80000002
|
hi_addr_bit
;
*
(
vu_long
*
)
MPC5XXX_SDRAM_CTRL
=
SDRAM_CONTROL
|
0x80000002
|
hi_addr_bit
;
__asm__
volatile
(
"sync"
);
#if SDRAM_DDR
/* set mode register: extended mode */
*
(
vu_long
*
)
MPC5XXX_SDRAM_MODE
=
SDRAM_EMODE
;
*
(
vu_long
*
)
MPC5XXX_SDRAM_MODE
=
SDRAM_EMODE
;
__asm__
volatile
(
"sync"
);
/* set mode register: reset DLL */
*
(
vu_long
*
)
MPC5XXX_SDRAM_MODE
=
SDRAM_MODE
|
0x04000000
;
*
(
vu_long
*
)
MPC5XXX_SDRAM_MODE
=
SDRAM_MODE
|
0x04000000
;
__asm__
volatile
(
"sync"
);
#endif
/* SDRAM_DDR */
/* precharge all banks */
*
(
vu_long
*
)
MPC5XXX_SDRAM_CTRL
=
SDRAM_CONTROL
|
0x80000002
|
hi_addr_bit
;
*
(
vu_long
*
)
MPC5XXX_SDRAM_CTRL
=
SDRAM_CONTROL
|
0x80000002
|
hi_addr_bit
;
__asm__
volatile
(
"sync"
);
/* auto refresh */
*
(
vu_long
*
)
MPC5XXX_SDRAM_CTRL
=
SDRAM_CONTROL
|
0x80000004
|
hi_addr_bit
;
*
(
vu_long
*
)
MPC5XXX_SDRAM_CTRL
=
SDRAM_CONTROL
|
0x80000004
|
hi_addr_bit
;
__asm__
volatile
(
"sync"
);
/* set mode register */
*
(
vu_long
*
)
MPC5XXX_SDRAM_MODE
=
SDRAM_MODE
;
*
(
vu_long
*
)
MPC5XXX_SDRAM_MODE
=
SDRAM_MODE
;
__asm__
volatile
(
"sync"
);
/* normal operation */
*
(
vu_long
*
)
MPC5XXX_SDRAM_CTRL
=
SDRAM_CONTROL
|
hi_addr_bit
;
*
(
vu_long
*
)
MPC5XXX_SDRAM_CTRL
=
SDRAM_CONTROL
|
hi_addr_bit
;
__asm__
volatile
(
"sync"
);
}
#endif
/* !CFG_RAMBOOT */
...
...
@@ -80,18 +81,18 @@ long int initdram(int board_type)
ulong
test1
,
test2
;
/* setup SDRAM chip selects */
*
(
vu_long
*
)
MPC5XXX_SDRAM_CS0CFG
=
0x0000001e
;
/* 2G at 0x0 */
*
(
vu_long
*
)
MPC5XXX_SDRAM_CS1CFG
=
0x80000000
;
/* disabled */
*
(
vu_long
*
)
MPC5XXX_SDRAM_CS0CFG
=
0x0000001e
;
/* 2G at 0x0 */
*
(
vu_long
*
)
MPC5XXX_SDRAM_CS1CFG
=
0x80000000
;
/* disabled */
__asm__
volatile
(
"sync"
);
/* setup config registers */
*
(
vu_long
*
)
MPC5XXX_SDRAM_CONFIG1
=
SDRAM_CONFIG1
;
*
(
vu_long
*
)
MPC5XXX_SDRAM_CONFIG2
=
SDRAM_CONFIG2
;
*
(
vu_long
*
)
MPC5XXX_SDRAM_CONFIG1
=
SDRAM_CONFIG1
;
*
(
vu_long
*
)
MPC5XXX_SDRAM_CONFIG2
=
SDRAM_CONFIG2
;
__asm__
volatile
(
"sync"
);
#if SDRAM_DDR
/* set tap delay */
*
(
vu_long
*
)
MPC5XXX_CDM_PORCFG
=
SDRAM_TAPDELAY
;
*
(
vu_long
*
)
MPC5XXX_CDM_PORCFG
=
SDRAM_TAPDELAY
;
__asm__
volatile
(
"sync"
);
#endif
/* SDRAM_DDR */
...
...
@@ -112,20 +113,20 @@ long int initdram(int board_type)
/* set SDRAM CS0 size according to the amount of RAM found */
if
(
dramsize
>
0
)
*
(
vu_long
*
)
MPC5XXX_SDRAM_CS0CFG
=
0x13
+
__builtin_ffs
(
dramsize
>>
20
)
-
1
;
*
(
vu_long
*
)
MPC5XXX_SDRAM_CS0CFG
=
0x13
+
__builtin_ffs
(
dramsize
>>
20
)
-
1
;
else
*
(
vu_long
*
)
MPC5XXX_SDRAM_CS0CFG
=
0
;
/* disabled */
*
(
vu_long
*
)
MPC5XXX_SDRAM_CS0CFG
=
0
;
/* disabled */
/* let SDRAM CS1 start right after CS0 */
*
(
vu_long
*
)
MPC5XXX_SDRAM_CS1CFG
=
dramsize
+
0x0000001e
;
/* 2G */
*
(
vu_long
*
)
MPC5XXX_SDRAM_CS1CFG
=
dramsize
+
0x0000001e
;
/* 2G */
/* find RAM size using SDRAM CS1 only */
if
(
!
dramsize
)
sdram_start
(
0
);
test2
=
test1
=
get_ram_size
((
long
*
)(
CFG_SDRAM_BASE
+
dramsize
),
0x80000000
);
test2
=
test1
=
get_ram_size
((
long
*
)
(
CFG_SDRAM_BASE
+
dramsize
),
0x80000000
);
if
(
!
dramsize
)
{
sdram_start
(
1
);
test2
=
get_ram_size
((
long
*
)(
CFG_SDRAM_BASE
+
dramsize
),
0x80000000
);
test2
=
get_ram_size
((
long
*
)
(
CFG_SDRAM_BASE
+
dramsize
),
0x80000000
);
}
if
(
test1
>
test2
)
{
sdram_start
(
0
);
...
...
@@ -139,22 +140,22 @@ long int initdram(int board_type)
/* set SDRAM CS1 size according to the amount of RAM found */
if
(
dramsize2
>
0
)
*
(
vu_long
*
)
MPC5XXX_SDRAM_CS1CFG
=
dramsize
*
(
vu_long
*
)
MPC5XXX_SDRAM_CS1CFG
=
dramsize
|
(
0x13
+
__builtin_ffs
(
dramsize2
>>
20
)
-
1
);
else
*
(
vu_long
*
)
MPC5XXX_SDRAM_CS1CFG
=
dramsize
;
/* disabled */
*
(
vu_long
*
)
MPC5XXX_SDRAM_CS1CFG
=
dramsize
;
/* disabled */
#else
/* CFG_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
dramsize
=
*
(
vu_long
*
)
MPC5XXX_SDRAM_CS0CFG
&
0xFF
;
dramsize
=
*
(
vu_long
*
)
MPC5XXX_SDRAM_CS0CFG
&
0xFF
;
if
(
dramsize
>=
0x13
)
dramsize
=
(
1
<<
(
dramsize
-
0x13
))
<<
20
;
else
dramsize
=
0
;
/* retrieve size of memory connected to SDRAM CS1 */
dramsize2
=
*
(
vu_long
*
)
MPC5XXX_SDRAM_CS1CFG
&
0xFF
;
dramsize2
=
*
(
vu_long
*
)
MPC5XXX_SDRAM_CS1CFG
&
0xFF
;
if
(
dramsize2
>=
0x13
)
dramsize2
=
(
1
<<
(
dramsize2
-
0x13
))
<<
20
;
else
...
...
@@ -176,7 +177,7 @@ long int initdram(int board_type)
if
((
SVR_MJREV
(
svr
)
>=
2
)
&&
(
PVR_MAJ
(
pvr
)
==
1
)
&&
(
PVR_MIN
(
pvr
)
==
4
))
{
*
(
vu_long
*
)
MPC5XXX_SDRAM_SDELAY
=
0x04
;
*
(
vu_long
*
)
MPC5XXX_SDRAM_SDELAY
=
0x04
;
__asm__
volatile
(
"sync"
);
}
...
...
@@ -194,27 +195,42 @@ int checkboard (void)
int
board_early_init_r
(
void
)
{
/*
* Now, when we are in RAM, enable flash write access for detection process.
* Note that CS_BOOT cannot be cleared when executing in flash.
* Now, when we are in RAM, enable flash write access for the
* detection process. Note that CS_BOOT cannot be cleared when
* executing in flash.
*/
*
(
vu_long
*
)
MPC5XXX_BOOTCS_CFG
&=
~
0x1
;
/* clear RO */
#ifdef CONFIG_HW_WATCHDOG
/*
* Enable and configure the direction (output) of PSC3_9 - watchdog
* reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's
* Manual.
*/
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_ENABLE
|=
GPIO_PSC3_9
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DIR
|=
GPIO_PSC3_9
;
#endif
/* CONFIG_HW_WATCHDOG */
/*
* Enable GPIO_WKUP_7 to "read the status of the actual power
* situation". Default direction is input, so no need to set it
* explicitly.
*/
*
(
vu_long
*
)
MPC5XXX_BOOTCS_CFG
&=
~
0x1
;
/* clear RO */
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_ENABLE
|=
GPIO_WKUP_7
;
return
0
;
}
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
#define GPIO_PSC1_4 0x01000000UL
void
init_ide_reset
(
void
)
{
debug
(
"init_ide_reset
\n
"
);
/* Configure PSC1_4 as GPIO output for ATA reset */
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_ENABLE
|=
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DIR
|=
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DIR
|=
GPIO_PSC1_4
;
/* Deassert reset */
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
|=
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
|=
GPIO_PSC1_4
;
}
...
...
@@ -223,30 +239,22 @@ void ide_set_reset(int idereset)
debug
(
"ide_reset(%d)
\n
"
,
idereset
);
if
(
idereset
)
{
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
&=
~
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
&=
~
GPIO_PSC1_4
;
/* Make a delay. MPC5200 spec says 25 usec min */
udelay
(
500000
);
}
else
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
|=
GPIO_PSC1_4
;
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA
_O
|=
GPIO_PSC1_4
;
}
#endif
/* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
void
led_d4_on
(
void
)
{
/* TIMER7 as GPIO output low */
*
(
vu_long
*
)
(
MPC5XXX_GPT
+
0x70
)
|=
0x24
;
}
void
led_d4_off
(
void
)
{
/* TIMER7 as GPIO output high */
*
(
vu_long
*
)
(
MPC5XXX_GPT
+
0x70
)
|=
0x34
;
}
#ifdef CONFIG_HW_WATCHDOG
void
hw_watchdog_reset
(
void
)
{
/* TODO fill this in */
/*
* MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog
* we need a positive or negative transition on WDI i.e., our PSC3_9.
*/
*
(
vu_long
*
)
MPC5XXX_WU_GPIO_DATA_O
^=
GPIO_PSC3_9
;
}
#endif
/* CONFIG_HW_WATCHDOG */
include/configs/
V38B
.h
→
include/configs/
v38b
.h
浏览文件 @
ee58ea26
/*
* (C) Copyright 2003-200
4
Wolfgang Denk, DENX Software Engineering,
* (C) Copyright 2003-200
6
Wolfgang Denk, DENX Software Engineering,
* wd@denx.de.
*
* See file CREDITS for list of people who contributed to this project.
...
...
@@ -11,7 +11,7 @@
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
...
...
@@ -22,51 +22,41 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#if 0
#define DEBUG 0xFFF
#endif
#if 0
#define DEBUG 0x01
#endif
/*
* High Level Configuration Options
* (easy to change)
*/
*/
#define CONFIG_MPC5xxx 1
/* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1
/* This is an MPC5200 CPU */
#define CONFIG_V38B 1
/* ...on V38B board */
#define CFG_MPC5XXX_CLKIN 33000000
/* ...running at 33.000000MHz */
#define CONFIG_MPC5xxx 1
/* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1
/* This is an MPC5200 CPU */
#define CONFIG_V38B 1
/* ... on V38B board */
#define CFG_MPC5XXX_CLKIN 33000000
/* ... running at 33.000000MHz */
#define CONFIG_RTC_PCF8563 1
/* has PCF8563 RTC */
#define CONFIG_MPC5200_DDR 1
/* has DDR SDRAM */
#define CONFIG_RTC_PCF8563 1
/* has PCF8563 RTC */
#define CONFIG_MPC5200_DDR 1
/* has DDR SDRAM */
#define CONFIG_HW_WATCHDOG 1
/* has watchdog */
#define CONFIG_HW_WATCHDOG 1
/* has watchdog */
#define CONFIG_NETCONSOLE 1
#define CONFIG_BOARD_EARLY_INIT_R 1
/* make flash read/write */
#define CFG_XLB_PIPELINING 1
/* gives better performance */
#define CONFIG_BOARD_EARLY_INIT_R 1
/* do board-specific init */
#define CFG_XLB_PIPELINING 1
/* gives better performance */
#define BOOTFLAG_COLD 0x01
/* Normal Power-On: Boot from FLASH
*/
#define BOOTFLAG_WARM 0x02
/* Software reboot
*/
#define BOOTFLAG_COLD 0x01
/* Normal Power-On: Boot from FLASH
*/
#define BOOTFLAG_WARM 0x02
/* Software reboot
*/
#define CFG_CACHELINE_SIZE 32
/* For MPC5xxx CPUs
*/
#define CFG_CACHELINE_SIZE 32
/* For MPC5xxx CPUs
*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5
/* log base 2 of the above value
*/
# define CFG_CACHELINE_SHIFT 5
/* log base 2 of the above value
*/
#endif
/*
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 1
/* console is on PSC1
*/
#define CONFIG_BAUDRATE 115200
/* ... at 115200 bps
*/
#define CONFIG_PSC_CONSOLE 1
/* console is on PSC1
*/
#define CONFIG_BAUDRATE 115200
/* ... at 115200 bps
*/
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/*
* DDR
*/
...
...
@@ -79,7 +69,6 @@
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000
/*
* PCI - no suport
*/
...
...
@@ -96,13 +85,13 @@
*/
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
#define CONFIG_
TIMESTAMP
/* Print image info with timestamp */
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_
USB_CONFIG 0x00001000
/*
* Supported commands
*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL
| \
#define CONFIG_COMMANDS (CONFIG_CMD_DFL
| \
CFG_CMD_FAT | \
CFG_CMD_I2C | \
CFG_CMD_IDE | \
...
...
@@ -112,53 +101,63 @@
CFG_CMD_IRQ | \
CFG_CMD_JFFS2 | \
CFG_CMD_MII | \
CFG_CMD_SDRAMi
| \
CFG_CMD_SDRAMi
| \
CFG_CMD_DATE | \
CFG_CMD_USB | \
CFG_CMD_FAT)
#define CONFIG_TIMESTAMP
/* Print image info with timestamp */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Boot low with 16 MB Flash
*/
#
define CFG_LOWBOOT 1
#
define CFG_LOWBOOT16
1
#define CFG_LOWBOOT 1
#
define CFG_LOWBOOT16
1
/*
* Autobooting
*/
#define CONFIG_BOOTDELAY 3
/* autoboot after 3 seconds */
#define CONFIG_PREBOOT "echo;"
\
#define CONFIG_PREBOOT "echo;"
\
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef
CONFIG_BOOTARGS
#undef
CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootcmd=run net_nfs\0" \
"bootdelay=3\0" \
"baudrate=115200\0" \
"preboot=echo;echo Type \"run flash_nfs\" to mount root " \
"filesystem over NFS; echo\0" \
"netdev=eth0\0" \
"devno=5\0" \
"hostname=V38B_$(devno)\0" \
"ipaddr=10.100.99.$(devno)\0" \
"netmask=255.255.0.0\0" \
"serverip=10.100.10.90\0" \
"gatewayip=10.100.254.254\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
"bootfile=mpc5200/uImage\0" \
"bootcmd=run net_nfs\0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):" \
"$(netmask):$(hostname):$(netdev):off panic=1\0" \
"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
"flash_self=run ramargs addip;bootm $(kernel_addr) " \
"$(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs " \
"addip;bootm\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
"hostname=v38b\0" \
"ethact=FEC ETHERNET\0" \
"rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \
"update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
"cp.b 200000 ff000000 $(filesize);" \
"prot on ff000000 ff03ffff\0" \
"load=tftp 200000 $(u-boot)\0" \
"netmask=255.255.0.0\0" \
"ipaddr=192.168.160.18\0" \
"serverip=192.168.1.1\0" \
"ethaddr=00:e0:ee:00:05:2e\0" \
"bootfile=/tftpboot/v38b/uImage\0" \
"u-boot=/tftpboot/v38b/u-boot.bin\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
...
...
@@ -169,13 +168,13 @@
*/
#undef CFG_IPBSPEED_133
/* define for 133MHz speed */
#endif
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1
/* I2C with hardware support */
#define CFG_I2C_MODULE 2
/* Select I2C module #1 or #2 */
#define CFG_I2C_SPEED 100000
/* 100 kHz */
#define CFG_I2C_SPEED 100000
/* 100 kHz */
#define CFG_I2C_SLAVE 0x7F
/*
...
...
@@ -196,7 +195,7 @@
*/
#define CFG_FLASH_CFI 1
/* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1
/* Use the common driver */
#define CFG_FLASH_CFI_AMD_RESET
1
#define CFG_FLASH_CFI_AMD_RESET
1
#define CFG_FLASH_BASE 0xFF000000
#define CFG_MAX_FLASH_BANKS 1
/* max num of flash banks */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
...
...
@@ -224,19 +223,18 @@
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
/* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 128
/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_BASE
TEXT_BASE
#define CFG_MONITOR_BASE
TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
# define CFG_RAMBOOT 1
#endif
#define CFG_MONITOR_LEN (
192 << 10)
/* Reserve 192 kB for Monitor
*/
#define CFG_MALLOC_LEN (128 << 10)
/* Reserve 128
kB for malloc()
*/
#define CFG_BOOTMAPSZ (8 << 20)
/*
Initial Memory map for Linux
*/
#define CFG_MONITOR_LEN (
256 << 10)
/* Reserve 256kB for Monitor
*/
#define CFG_MALLOC_LEN (128 << 10)
/* Reserve 128
kB for malloc()
*/
#define CFG_BOOTMAPSZ (8 << 20)
/*
Linux initial memory map
*/
/*
* Ethernet configuration
...
...
@@ -253,19 +251,19 @@
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP
/* undef to save memory
*/
#define CFG_PROMPT "=> "
/* Monitor Command Prompt
*/
#define CFG_LONGHELP
/* undef to save memory */
#define CFG_PROMPT "=> "
/* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024
/* Console I/O Buffer Size
*/
#define CFG_CBSIZE 1024
/* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256
/* Console I/O Buffer Size
*/
#define CFG_CBSIZE 256
/* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
/* Print Buffer Size */
#define CFG_MAXARGS 16
/* max number of command args
*/
#define CFG_BARGSIZE CFG_CBSIZE
/* Boot Argument Buffer Size
*/
#define CFG_MAXARGS 16
/* max number of command args
*/
#define CFG_BARGSIZE CFG_CBSIZE
/* Boot Argument Buffer Size
*/
#define CFG_MEMTEST_START 0x00100000
/* memtest works on */
#define CFG_MEMTEST_END 0x00f00000
/* 1 ... 15 MB in DRAM
*/
#define CFG_MEMTEST_END 0x00f00000
/* 1 ... 15 MB in DRAM
*/
#define CFG_LOAD_ADDR 0x100000
/* default load address */
...
...
@@ -274,14 +272,8 @@
/*
* Various low-level settings
*/
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL HID0_ICE
#else
#define CFG_HID0_INIT 0
#define CFG_HID0_FINAL 0
#endif
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
...
...
@@ -294,55 +286,39 @@
#define CFG_RESET_ADDRESS 0xff000000
/*-----------------------------------------------------------------------
* USB stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_USB_CONFIG 0x00001000
/*-----------------------------------------------------------------------
* IDE/ATA stuff Supports IDE harddisk
*-----------------------------------------------------------------------
/*
* IDE/ATA (supports IDE harddisk)
*/
#undef CONFIG_IDE_8xx_PCCARD
/* Don't use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT
/* Direct IDE not supported */
#undef CONFIG_IDE_LED
/* LED for ide not supported */
#undef CONFIG_IDE_8xx_PCCARD
/* Don't use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT
/* Direct IDE not supported */
#undef CONFIG_IDE_LED
/* LED for ide not supported */
#define CONFIG_IDE_RESET
/* reset for ide supported */
#define CONFIG_IDE_RESET
/* reset for ide supported */
#define CONFIG_IDE_PREINIT
#define CFG_IDE_MAXBUS 1
/* max. 1 IDE bus
*/
#define CFG_IDE_MAXDEVICE 1
/* max. 1 drive per IDE bus
*/
#define CFG_IDE_MAXBUS 1
/* max. 1 IDE bus
*/
#define CFG_IDE_MAXDEVICE 1
/* max. 1 drive per IDE bus
*/
#define CFG_ATA_IDE0_OFFSET 0x0000
#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
/* Offset for data I/O */
#define CFG_ATA_DATA_OFFSET (0x0060)
/* Offset for normal register accesses */
#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
#define CFG_ATA_DATA_OFFSET (0x0060)
/* data I/O offset */
/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET (0x005C)
#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
/* normal register accesses offset */
/* Interval between registers */
#define CFG_ATA_STRIDE 4
#define CFG_ATA_ALT_OFFSET (0x005C)
/* alternate registers offset */
/* Status LED
*/
#define CFG_ATA_STRIDE 4
/* Interval between registers
*/
#define CONFIG_STATUS_LED
/* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED
/* version has board specific leds */
#define CFG_LED_BASE (0xf0000600 + 0x70)
/* Timer 7 GPIO */
/*
* Status LED
*/
#define CONFIG_STATUS_LED
/* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED
/* version has board specific leds */
#define CFG_LED_BASE MPC5XXX_GPT7_ENABLE
/* Timer 7 GPIO */
#ifndef __ASSEMBLY__
/* LEDs */
typedef
unsigned
int
led_id_t
;
#define __led_toggle(_msk) \
...
...
@@ -359,10 +335,9 @@ typedef unsigned int led_id_t;
} while(0)
#define __led_init(_msk, st) \
{ \
do
{ \
*((volatile long *) (CFG_LED_BASE)) |= 0x34; \
}
#endif
} while(0)
#endif
/* __ASSEMBLY__ */
#endif
/* __CONFIG_H */
include/mpc5xxx.h
浏览文件 @
ee58ea26
...
...
@@ -188,7 +188,14 @@
#define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000)
#define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004)
#define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008)
#define MPC5XXX_WU_GPIO_DATA (MPC5XXX_WU_GPIO + 0x000c)
#define MPC5XXX_WU_GPIO_DATA_O (MPC5XXX_WU_GPIO + 0x000c)
#define MPC5XXX_WU_GPIO_DATA_I (MPC5XXX_WU_GPIO + 0x0020)
/* GPIO pins */
#define GPIO_WKUP_7 0x80000000UL
#define GPIO_PSC6_0 0x10000000UL
#define GPIO_PSC3_9 0x04000000UL
#define GPIO_PSC1_4 0x01000000UL
/* PCI registers */
#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
...
...
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