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体验新版 GitCode,发现更多精彩内容 >>
提交
ea339205
编写于
11月 08, 2005
作者:
S
Stefan Roese
浏览文件
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浏览文件
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电子邮件补丁
差异文件
Updated PCI mapping for esd CPCI2DP board.
Add support for error LED. Patch by Matthias Fuchs, 07 Nov 2005
上级
527b5a51
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
18 addition
and
10 deletion
+18
-10
CHANGELOG
CHANGELOG
+4
-0
board/esd/cpci2dp/cpci2dp.c
board/esd/cpci2dp/cpci2dp.c
+9
-6
include/configs/CPCI2DP.h
include/configs/CPCI2DP.h
+5
-4
未找到文件。
CHANGELOG
浏览文件 @
ea339205
...
@@ -2,6 +2,10 @@
...
@@ -2,6 +2,10 @@
Changes for U-Boot 1.1.4:
Changes for U-Boot 1.1.4:
======================================================================
======================================================================
* Updated PCI mapping for esd CPCI2DP board.
Add support for error LED.
Patch by Matthias Fuchs, 07 Nov 2005
* Fix MPC85xx PCI support (pci_register_hose() before pci config access)
* Fix MPC85xx PCI support (pci_register_hose() before pci config access)
Patch by Stefan Roese, 07 Nov 2005
Patch by Stefan Roese, 07 Nov 2005
...
...
board/esd/cpci2dp/cpci2dp.c
浏览文件 @
ea339205
...
@@ -31,14 +31,17 @@ int board_early_init_f (void)
...
@@ -31,14 +31,17 @@ int board_early_init_f (void)
unsigned
long
cntrl0Reg
;
unsigned
long
cntrl0Reg
;
/*
/*
* Setup GPIO pins (CS4 as GPIO)
* Setup GPIO pins (CS4
+CS7
as GPIO)
*/
*/
cntrl0Reg
=
mfdcr
(
cntrl0
);
cntrl0Reg
=
mfdcr
(
cntrl0
);
mtdcr
(
cntrl0
,
cntrl0Reg
|
0x00800000
);
mtdcr
(
cntrl0
,
cntrl0Reg
|
0x00900000
);
out32
(
GPIO0_OR
,
CFG_INTA_FAKE
|
CFG_EEPROM_WP
);
/* set output pins to high */
/* set output pins to high */
out32
(
GPIO0_ODR
,
CFG_INTA_FAKE
);
/* INTA# is open drain */
out32
(
GPIO0_OR
,
CFG_INTA_FAKE
|
CFG_EEPROM_WP
|
CFG_PB_LED
);
out32
(
GPIO0_TCR
,
CFG_INTA_FAKE
|
CFG_EEPROM_WP
);
/* setup for output */
/* INTA# is open drain */
out32
(
GPIO0_ODR
,
CFG_INTA_FAKE
);
/* setup for output */
out32
(
GPIO0_TCR
,
CFG_INTA_FAKE
|
CFG_EEPROM_WP
);
/*
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
* IRQ 0-15 405GP internally generated; active high; level sensitive
...
...
include/configs/CPCI2DP.h
浏览文件 @
ea339205
...
@@ -146,9 +146,9 @@
...
@@ -146,9 +146,9 @@
#define CFG_PCI_PTM1LA 0x00000000
/* point to sdram */
#define CFG_PCI_PTM1LA 0x00000000
/* point to sdram */
#define CFG_PCI_PTM1MS 0xfc000001
/* 64MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1MS 0xfc000001
/* 64MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000
/* Host: use this pci address */
#define CFG_PCI_PTM1PCI 0x00000000
/* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xef
6
00000
/* point to internal regs + PB0/1 */
#define CFG_PCI_PTM2LA 0xef
0
00000
/* point to internal regs + PB0/1 */
#define CFG_PCI_PTM2MS 0xff000001
/* 16MB, enable */
#define CFG_PCI_PTM2MS 0xff000001
/* 16MB, enable */
#define CFG_PCI_PTM2PCI 0x0
4
000000
/* Host: use this pci address */
#define CFG_PCI_PTM2PCI 0x0
0
000000
/* Host: use this pci address */
/*-----------------------------------------------------------------------
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* Start addresses for the final memory configuration
...
@@ -237,11 +237,11 @@
...
@@ -237,11 +237,11 @@
/* Memory Bank 2 (PB0) initialization */
/* Memory Bank 2 (PB0) initialization */
#define CFG_EBC_PB2AP 0x03004580
/* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
#define CFG_EBC_PB2AP 0x03004580
/* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
#define CFG_EBC_PB2CR 0x
F0
018000
/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
#define CFG_EBC_PB2CR 0x
EF
018000
/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
/* Memory Bank 3 (PB1) initialization */
/* Memory Bank 3 (PB1) initialization */
#define CFG_EBC_PB3AP 0x03004580
/* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
#define CFG_EBC_PB3AP 0x03004580
/* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
#define CFG_EBC_PB3CR 0x
F0
118000
/* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
#define CFG_EBC_PB3CR 0x
EF
118000
/* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
/*-----------------------------------------------------------------------
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
* Definitions for initial stack pointer and data area (in data cache)
...
@@ -258,6 +258,7 @@
...
@@ -258,6 +258,7 @@
* GPIO definitions
* GPIO definitions
*/
*/
#define CFG_EEPROM_WP (0x80000000 >> 13)
/* GPIO13 */
#define CFG_EEPROM_WP (0x80000000 >> 13)
/* GPIO13 */
#define CFG_PB_LED (0x80000000 >> 16)
/* GPIO16 */
#define CFG_INTA_FAKE (0x80000000 >> 23)
/* GPIO23 */
#define CFG_INTA_FAKE (0x80000000 >> 23)
/* GPIO23 */
/*
/*
...
...
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