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体验新版 GitCode,发现更多精彩内容 >>
提交
e6ac28b6
编写于
1月 19, 2016
作者:
T
Tom Rini
浏览文件
操作
浏览文件
下载
差异文件
Merge branch 'master' of
git://git.denx.de/u-boot-video
上级
6071cd62
535cce0f
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
26 addition
and
26 deletion
+26
-26
drivers/video/da8xx-fb.c
drivers/video/da8xx-fb.c
+5
-5
drivers/video/exynos_dp.c
drivers/video/exynos_dp.c
+8
-8
drivers/video/exynos_dp_lowlevel.c
drivers/video/exynos_dp_lowlevel.c
+13
-13
未找到文件。
drivers/video/da8xx-fb.c
浏览文件 @
e6ac28b6
...
...
@@ -379,7 +379,7 @@ static void lcd_cfg_ac_bias(int period, int transitions_per_int)
{
u32
reg
;
/* Set the AC Bias Period and Number of Transi
sit
ons per Interrupt */
/* Set the AC Bias Period and Number of Transi
ti
ons per Interrupt */
reg
=
lcdc_read
(
&
da8xx_fb_reg_base
->
raster_timing_2
)
&
0xFFF00000
;
reg
|=
LCD_AC_BIAS_FREQUENCY
(
period
)
|
LCD_AC_BIAS_TRANSITIONS_PER_INT
(
transitions_per_int
);
...
...
@@ -487,7 +487,7 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
/* Pixels per line = (PPL + 1)*16 */
if
(
lcd_revision
==
LCD_VERSION_1
)
{
/*
* 0x3F in bits 4..9 gives max hori
s
ontal resolution = 1024
* 0x3F in bits 4..9 gives max hori
z
ontal resolution = 1024
* pixels
*/
width
&=
0x3f0
;
...
...
@@ -695,7 +695,7 @@ static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
lcd_cfg_vertical_sync
(
panel
->
vbp
,
panel
->
vsw
,
panel
->
vfp
);
lcd_cfg_horizontal_sync
(
panel
->
hbp
,
panel
->
hsw
,
panel
->
hfp
);
/* Configure for disply */
/* Configure for displ
a
y */
ret
=
lcd_cfg_display
(
cfg
);
if
(
ret
<
0
)
return
ret
;
...
...
@@ -761,7 +761,7 @@ static u32 lcdc_irq_handler_rev01(void)
lcdc_write
(
stat
,
&
da8xx_fb_reg_base
->
stat
);
/* Disable PL completion inerrupt */
/* Disable PL completion in
t
errupt */
reg_ras
=
lcdc_read
(
&
da8xx_fb_reg_base
->
raster_ctrl
);
reg_ras
&=
~
LCD_V1_PL_INT_ENA
;
lcdc_write
(
reg_ras
,
&
da8xx_fb_reg_base
->
raster_ctrl
);
...
...
@@ -810,7 +810,7 @@ static u32 lcdc_irq_handler_rev02(void)
lcdc_write
(
stat
,
&
da8xx_fb_reg_base
->
masked_stat
);
/* Disable PL completion inerrupt */
/* Disable PL completion in
t
errupt */
reg_int
=
lcdc_read
(
&
da8xx_fb_reg_base
->
int_ena_clr
)
|
(
LCD_V2_PL_INT_ENA
);
lcdc_write
(
reg_int
,
&
da8xx_fb_reg_base
->
int_ena_clr
);
...
...
drivers/video/exynos_dp.c
浏览文件 @
e6ac28b6
...
...
@@ -207,7 +207,7 @@ static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
return
-
EINVAL
;
}
/*
Refer VESA Display Port Stna
dard Ver1.1a Page 120 */
/*
Refer VESA Display Port Stan
dard Ver1.1a Page 120 */
if
(
edp_info
->
dpcd_rev
==
DP_DPCD_REV_11
)
{
temp
=
buf
[
DPCD_MAX_LANE_COUNT
]
&
0x1f
;
if
(
buf
[
DPCD_MAX_LANE_COUNT
]
&
0x80
)
...
...
@@ -270,7 +270,7 @@ static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info)
return
ret
;
}
/* Set link rate and count as you want to establish*/
/* Set link rate and count as you want to establish
*/
exynos_dp_set_link_bandwidth
(
edp_info
->
lane_bw
);
exynos_dp_set_lane_count
(
edp_info
->
lane_cnt
);
...
...
@@ -322,7 +322,7 @@ static unsigned int exynos_dp_training_pattern_dis(void)
ret
=
exynos_dp_write_byte_to_dpcd
(
DPCD_TRAINING_PATTERN_SET
,
DPCD_TRAINING_PATTERN_DISABLED
);
if
(
ret
!=
EXYNOS_DP_SUCCESS
)
{
printf
(
"DP requ
st_link_tranini
g_req failed
\n
"
);
printf
(
"DP requ
est_link_trainin
g_req failed
\n
"
);
return
-
EAGAIN
;
}
...
...
@@ -412,7 +412,7 @@ static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num,
unsigned
int
dpcd_addr
;
unsigned
char
shift_val
[
DP_LANE_CNT_4
]
=
{
0
,
4
,
0
,
4
};
/*
lane_num value is used as arr
y index, so this range 0 ~ 3 */
/*
lane_num value is used as arra
y index, so this range 0 ~ 3 */
dpcd_addr
=
DPCD_ADJUST_REQUEST_LANE0_1
+
(
lane_num
/
2
);
ret
=
exynos_dp_read_byte_from_dpcd
(
dpcd_addr
,
&
buf
);
...
...
@@ -433,7 +433,7 @@ static int exynos_dp_equalizer_err_link(struct edp_device_info *edp_info)
ret
=
exynos_dp_training_pattern_dis
();
if
(
ret
!=
EXYNOS_DP_SUCCESS
)
{
printf
(
"DP training_patter_disable() failed
\n
"
);
printf
(
"DP training_patter
n
_disable() failed
\n
"
);
edp_info
->
lt_info
.
lt_status
=
DP_LT_FAIL
;
}
...
...
@@ -523,7 +523,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
ret
=
exynos_dp_write_bytes_to_dpcd
(
DPCD_TRAINING_PATTERN_SET
,
5
,
buf
);
if
(
ret
!=
EXYNOS_DP_SUCCESS
)
{
printf
(
"DP write traning pattern1 failed
\n
"
);
printf
(
"DP write tra
i
ning pattern1 failed
\n
"
);
edp_info
->
lt_info
.
lt_status
=
DP_LT_FAIL
;
return
ret
;
}
else
...
...
@@ -567,7 +567,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
ret
=
exynos_dp_write_bytes_to_dpcd
(
DPCD_TRAINING_LANE0_SET
,
4
,
lt_ctl_val
);
if
(
ret
!=
EXYNOS_DP_SUCCESS
)
{
printf
(
"DP write traning pattern2 failed
\n
"
);
printf
(
"DP write tra
i
ning pattern2 failed
\n
"
);
edp_info
->
lt_info
.
lt_status
=
DP_LT_FAIL
;
return
ret
;
}
...
...
@@ -738,7 +738,7 @@ static unsigned int exynos_dp_set_link_train(struct edp_device_info *edp_info)
ret
=
exynos_dp_sw_link_training
(
edp_info
);
if
(
ret
!=
EXYNOS_DP_SUCCESS
)
printf
(
"DP dp_sw_link_traning() failed
\n
"
);
printf
(
"DP dp_sw_link_tra
i
ning() failed
\n
"
);
return
ret
;
}
...
...
drivers/video/exynos_dp_lowlevel.c
浏览文件 @
e6ac28b6
...
...
@@ -44,7 +44,7 @@ static void exynos_dp_enable_video_input(unsigned int enable)
reg
=
readl
(
&
dp_regs
->
video_ctl1
);
reg
&=
~
VIDEO_EN_MASK
;
/* enable video input*/
/* enable video input
*/
if
(
enable
)
reg
|=
VIDEO_EN_MASK
;
...
...
@@ -55,13 +55,13 @@ static void exynos_dp_enable_video_input(unsigned int enable)
void
exynos_dp_enable_video_bist
(
unsigned
int
enable
)
{
/*
enable video bist
*/
/*
enable video bist
*/
unsigned
int
reg
;
reg
=
readl
(
&
dp_regs
->
video_ctl4
);
reg
&=
~
VIDEO_BIST_MASK
;
/*
enable video bist
*/
/*
enable video bist
*/
if
(
enable
)
reg
|=
VIDEO_BIST_MASK
;
...
...
@@ -112,7 +112,7 @@ static void exynos_dp_init_analog_param(void)
/*
* Set AUX TX terminal resistor to 102 ohm
* Set AUX channel amplitude control
*/
*/
reg
=
PD_RING_OSC
|
AUX_TERMINAL_CTRL_52_OHM
|
TX_CUR1_2X
|
TX_CUR_4_MA
;
writel
(
reg
,
&
dp_regs
->
pll_filter_ctl1
);
...
...
@@ -146,7 +146,7 @@ static void exynos_dp_init_interrupt(void)
*/
writel
(
INT_POL
,
&
dp_regs
->
int_ctl
);
/* Clear pending regisers */
/* Clear pending regis
t
ers */
writel
(
0xff
,
&
dp_regs
->
common_int_sta1
);
writel
(
0xff
,
&
dp_regs
->
common_int_sta2
);
writel
(
0xff
,
&
dp_regs
->
common_int_sta3
);
...
...
@@ -165,7 +165,7 @@ void exynos_dp_reset(void)
{
unsigned
int
reg_func_1
;
/*
dp tx sw reset
*/
/*
dp tx sw reset
*/
writel
(
RESET_DP_TX
,
&
dp_regs
->
tx_sw_reset
);
exynos_dp_enable_video_input
(
DP_DISABLE
);
...
...
@@ -287,7 +287,7 @@ int exynos_dp_init_analog_func(void)
unsigned
int
retry_cnt
=
10
;
unsigned
int
reg
;
/*Power On All Analog block */
/*
Power On All Analog block */
exynos_dp_set_analog_power_down
(
POWER_ALL
,
DP_DISABLE
);
reg
=
PLL_LOCK_CHG
;
...
...
@@ -297,14 +297,14 @@ int exynos_dp_init_analog_func(void)
reg
&=
~
(
F_PLL_LOCK
|
PLL_LOCK_CTRL
);
writel
(
reg
,
&
dp_regs
->
debug_ctl
);
/*
Assert DP PLL Reset
*/
/*
Assert DP PLL Reset
*/
reg
=
readl
(
&
dp_regs
->
pll_ctl
);
reg
|=
DP_PLL_RESET
;
writel
(
reg
,
&
dp_regs
->
pll_ctl
);
mdelay
(
1
);
/*
Deassert DP PLL Reset
*/
/*
Deassert DP PLL Reset
*/
reg
=
readl
(
&
dp_regs
->
pll_ctl
);
reg
&=
~
(
DP_PLL_RESET
);
writel
(
reg
,
&
dp_regs
->
pll_ctl
);
...
...
@@ -336,7 +336,7 @@ void exynos_dp_init_hpd(void)
{
unsigned
int
reg
;
/* Clear interrupts rel
eated to Hot Plug Dec
tect */
/* Clear interrupts rel
ated to Hot Plug De
tect */
reg
=
HOTPLUG_CHG
|
HPD_LOST
|
PLUG
;
writel
(
reg
,
&
dp_regs
->
common_int_sta4
);
...
...
@@ -366,7 +366,7 @@ void exynos_dp_init_aux(void)
{
unsigned
int
reg
;
/* Clear inerrupts related to AUX channel */
/* Clear in
t
errupts related to AUX channel */
reg
=
RPLY_RECEIV
|
AUX_ERR
;
writel
(
reg
,
&
dp_regs
->
int_sta
);
...
...
@@ -377,7 +377,7 @@ void exynos_dp_init_aux(void)
AUX_HW_RETRY_INTERVAL_600_MICROSECONDS
;
writel
(
reg
,
&
dp_regs
->
aux_hw_retry_ctl
);
/* Receive AUX Channel DEFER commands equal to DEF
F
ER_COUNT*64 */
/* Receive AUX Channel DEFER commands equal to DEFER_COUNT*64 */
reg
=
DEFER_CTRL_EN
|
DEFER_COUNT
(
1
);
writel
(
reg
,
&
dp_regs
->
aux_ch_defer_ctl
);
...
...
@@ -1040,7 +1040,7 @@ void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info)
reg
|=
(
video_info
->
h_sync_polarity
<<
H_S_POLARITY_CFG_SHIFT
);
writel
(
reg
,
&
dp_regs
->
video_ctl10
);
/*Set video mode to slave mode */
/*
Set video mode to slave mode */
reg
=
AUDIO_MODE_SPDIF_MODE
|
VIDEO_MODE_SLAVE_MODE
;
writel
(
reg
,
&
dp_regs
->
soc_general_ctl
);
}
...
...
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