Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx

Support of device tree model for T2080RDB, T4240RDB, T1024RDB,
T1042D4RDB, P1020RDB, P2020RDB, P2041RDB, P3041DS, P4080DS, P5040DS and
MPC8548CDS. Also support of  i2c dm model.

Makefile

@@ -1256,10 +1256,16 @@ MKIMAGEFLAGS_u-boot-spl.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
 MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
 		-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
 
+ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
+UBOOT_BIN := u-boot-with-dtb.bin
+else
+UBOOT_BIN := u-boot.bin
+endif
+
 u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
 		$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \
 			$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \
-		,u-boot.bin) FORCE
+		,$(UBOOT_BIN)) FORCE
 	$(call if_changed,mkimage)
 	$(BOARD_SIZE_CHECK)
 

arch/powerpc/dts/Makefile

 # SPDX-License-Identifier: GPL-2.0+
 
+dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb
+dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
+dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
+dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb
+dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb
+dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb
+dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb
+dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb
+dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
+dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
 dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
+dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb
+dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb
 dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
 dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb
 

arch/powerpc/dts/e500mc_power_isa.dtsi

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * e500mc Power ISA Device Tree Source (include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/ {
+	cpus {
+		power-isa-version = "2.06";
+		power-isa-b;		// Base
+		power-isa-e;		// Embedded
+		power-isa-atb;		// Alternate Time Base
+		power-isa-cs;		// Cache Specification
+		power-isa-ds;		// Decorated Storage
+		power-isa-e.ed;		// Embedded.Enhanced Debug
+		power-isa-e.pd;		// Embedded.External PID
+		power-isa-e.hv;		// Embedded.Hypervisor
+		power-isa-e.le;		// Embedded.Little-Endian
+		power-isa-e.pm;		// Embedded.Performance Monitor
+		power-isa-e.pc;		// Embedded.Processor Control
+		power-isa-ecl;		// Embedded Cache Locking
+		power-isa-exp;		// External Proxy
+		power-isa-fp;		// Floating Point
+		power-isa-fp.r;		// Floating Point.Record
+		power-isa-mmc;		// Memory Coherence
+		power-isa-scpm;		// Store Conditional Page Mobility
+		power-isa-wt;		// Wait
+		fsl,eref-deo;		// Data Cache Extended Operations
+		mmu-type = "power-embedded";
+	};
+};

arch/powerpc/dts/e500v2_power_isa.dtsi

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * e500v2 Power ISA Device Tree Source (include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/ {
+	cpus {
+		power-isa-version = "2.03";
+		power-isa-b;		// Base
+		power-isa-e;		// Embedded
+		power-isa-atb;		// Alternate Time Base
+		power-isa-cs;		// Cache Specification
+		power-isa-e.le;		// Embedded.Little-Endian
+		power-isa-e.pm;		// Embedded.Performance Monitor
+		power-isa-ecl;		// Embedded Cache Locking
+		power-isa-mmc;		// Memory Coherence
+		power-isa-sp;		// Signal Processing Engine
+		power-isa-sp.fd;	// SPE.Embedded Float Scalar Double
+		power-isa-sp.fs;	// SPE.Embedded Float Scalar Single
+		power-isa-sp.fv;	// SPE.Embedded Float Vector
+		mmu-type = "power-embedded";
+	};
+};

arch/powerpc/dts/e5500_power_isa.dtsi

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * e5500 Power ISA Device Tree Source (include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/ {
+	cpus {
+		power-isa-version = "2.06";
+		power-isa-b;		// Base
+		power-isa-e;		// Embedded
+		power-isa-atb;		// Alternate Time Base
+		power-isa-cs;		// Cache Specification
+		power-isa-ds;		// Decorated Storage
+		power-isa-e.ed;		// Embedded.Enhanced Debug
+		power-isa-e.pd;		// Embedded.External PID
+		power-isa-e.hv;		// Embedded.Hypervisor
+		power-isa-e.le;		// Embedded.Little-Endian
+		power-isa-e.pm;		// Embedded.Performance Monitor
+		power-isa-e.pc;		// Embedded.Processor Control
+		power-isa-ecl;		// Embedded Cache Locking
+		power-isa-exp;		// External Proxy
+		power-isa-fp;		// Floating Point
+		power-isa-fp.r;		// Floating Point.Record
+		power-isa-mmc;		// Memory Coherence
+		power-isa-scpm;		// Store Conditional Page Mobility
+		power-isa-wt;		// Wait
+		power-isa-64;		// 64-bit
+		fsl,eref-deo;		// Data Cache Extended Operations
+		mmu-type = "power-embedded";
+	};
+};

arch/powerpc/dts/mpc8548-post.dtsi

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8548 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "soc";
+	compatible = "fsl,mpc8548-immr", "simple-bus";
+	bus-frequency = <0x0>;
+
+	mpic: pic@40000 {
+		interrupt-controller;
+		#address-cells = <0>;
+		#interrupt-cells = <4>;
+		reg = <0x40000 0x40000>;
+		compatible = "fsl,mpic";
+		device_type = "open-pic";
+		big-endian;
+		single-cpu-affinity;
+		last-interrupt-source = <255>;
+	};
+};

arch/powerpc/dts/mpc8548.dtsi

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8548CDS Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,8548@0 {
+			device_type = "cpu";
+			reg = <0>;
+		};
+	};
+};

arch/powerpc/dts/mpc8548cds.dts

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8548CDS Device Tree Source
+ *
+ * Copyright 2006 - 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "mpc8548.dtsi"
+
+/ {
+	model = "fsl,MPC8548CDS";
+	compatible = "fsl,MPC8548CDS";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	soc: soc8548@e0000000 {
+		ranges = <0x0 0x0 0xe0000000 0x100000>;
+	};
+};
+
+/include/ "mpc8548-post.dtsi"

arch/powerpc/dts/mpc8548cds_36b.dts

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8548CDS (36-bit address map) Device Tree Source
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "mpc8548.dtsi"
+
+/ {
+	model = "fsl,MPC8548CDS";
+	compatible = "fsl,MPC8548CDS";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	soc: soc8548@fe0000000 {
+		ranges = <0x0 0xf 0xe0000000 0x100000>;
+	};
+};
+
+/include/ "mpc8548-post.dtsi"

arch/powerpc/dts/p1020-post.dtsi

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "soc";
+	compatible = "fsl,p1020-immr", "simple-bus";
+	bus-frequency = <0x0>;
+
+	mpic: pic@40000 {
+		interrupt-controller;
+		#address-cells = <0>;
+		#interrupt-cells = <4>;
+		reg = <0x40000 0x40000>;
+		compatible = "fsl,mpic";
+		device_type = "open-pic";
+		big-endian;
+		single-cpu-affinity;
+		last-interrupt-source = <255>;
+	};
+};

arch/powerpc/dts/p1020.dtsi

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,P1020@0 {
+			device_type = "cpu";
+			reg = <0>;
+		};
+		cpu1: PowerPC,P1020@1 {
+			device_type = "cpu";
+			reg = <1>;
+		};
+	};
+};

arch/powerpc/dts/p1020rdb-pc.dts

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020RDB-PC Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p1020.dtsi"
+
+/ {
+	model = "fsl,P1020RDB-PC";
+	compatible = "fsl,P1020RDB-PC";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+	};
+};
+
+/include/ "p1020-post.dtsi"

arch/powerpc/dts/p1020rdb-pc_36b.dts

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020RDB-PC (36-bit address map) Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p1020.dtsi"
+
+/ {
+	model = "fsl,P1020RDB-PC";
+	compatible = "fsl,P1020RDB-PC";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	soc: soc@fffe00000 {
+		ranges = <0x0 0xf 0xffe00000 0x100000>;
+	};
+};
+
+/include/ "p1020-post.dtsi"

arch/powerpc/dts/p1020rdb-pd.dts

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020RDB-PD Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p1020.dtsi"
+
+/ {
+	model = "fsl,P1020RDB-PD";
+	compatible = "fsl,P1020RDB-PD";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+	};
+};
+
+/include/ "p1020-post.dtsi"

arch/powerpc/dts/p2020-post.dtsi

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "soc";
+	compatible = "fsl,p2020-immr", "simple-bus";
+	bus-frequency = <0x0>;
+
+	mpic: pic@40000 {
+		interrupt-controller;
+		#address-cells = <0>;
+		#interrupt-cells = <4>;
+		reg = <0x40000 0x40000>;
+		compatible = "fsl,mpic";
+		device_type = "open-pic";
+		big-endian;
+		single-cpu-affinity;
+		last-interrupt-source = <255>;
+	};
+};

arch/powerpc/dts/p2020.dtsi

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,P2020@0 {
+			device_type = "cpu";
+			reg = <0>;
+		};
+		cpu1: PowerPC,P2020@1 {
+			device_type = "cpu";
+			reg = <1>;
+		};
+	};
+};

arch/powerpc/dts/p2020rdb-pc.dts

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020RDB-PC Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p2020.dtsi"
+
+/ {
+	model = "fsl,P2020RDB-PC";
+	compatible = "fsl,P2020RDB-PC";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+	};
+};
+
+/include/ "p2020-post.dtsi"

arch/powerpc/dts/p2020rdb-pc_36b.dts

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020RDB-PC (36-bit address map) Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p2020.dtsi"
+
+/ {
+	model = "fsl,P2020RDB-PC";
+	compatible = "fsl,P2020RDB-PC";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	soc: soc@fffe00000 {
+		ranges = <0x0 0xf 0xffe00000 0x100000>;
+	};
+};
+
+/include/ "p2020-post.dtsi"

arch/powerpc/dts/p2041.dtsi

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2041 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500mc_power_isa.dtsi"
+
+/ {
+	compatible = "fsl,P2041";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,e500mc@0 {
+			device_type = "cpu";
+			reg = <0>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu1: PowerPC,e500mc@1 {
+			device_type = "cpu";
+			reg = <1>;
+			fsl,portid-mapping = <0x40000000>;
+		};
+		cpu2: PowerPC,e500mc@2 {
+			device_type = "cpu";
+			reg = <2>;
+			fsl,portid-mapping = <0x20000000>;
+		};
+		cpu3: PowerPC,e500mc@3 {
+			device_type = "cpu";
+			reg = <3>;
+			fsl,portid-mapping = <0x10000000>;
+		};
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+
+		mpic: pic@40000 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <4>;
+			reg = <0x40000 0x40000>;
+			compatible = "fsl,mpic", "chrp,open-pic";
+			device_type = "open-pic";
+			clock-frequency = <0x0>;
+		};
+	};
+};

arch/powerpc/dts/p2041rdb.dts

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2041RDB Device Tree Source
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p2041.dtsi"
+
+/ {
+	model = "fsl,P2041RDB";
+	compatible = "fsl,P2041RDB";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+};

arch/powerpc/dts/p3041.dtsi

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P3041 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2010 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500mc_power_isa.dtsi"
+
+/ {
+	compatible = "fsl,P3041";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,e500mc@0 {
+			device_type = "cpu";
+			reg = <0>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu1: PowerPC,e500mc@1 {
+			device_type = "cpu";
+			reg = <1>;
+			fsl,portid-mapping = <0x40000000>;
+		};
+		cpu2: PowerPC,e500mc@2 {
+			device_type = "cpu";
+			reg = <2>;
+			fsl,portid-mapping = <0x20000000>;
+		};
+		cpu3: PowerPC,e500mc@3 {
+			device_type = "cpu";
+			reg = <3>;
+			fsl,portid-mapping = <0x10000000>;
+		};
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+
+		mpic: pic@40000 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <4>;
+			reg = <0x40000 0x40000>;
+			compatible = "fsl,mpic", "chrp,open-pic";
+			device_type = "open-pic";
+			clock-frequency = <0x0>;
+		};
+	};
+};

arch/powerpc/dts/p3041ds.dts

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P3041DS Device Tree Source
+ *
+ * Copyright 2010 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p3041.dtsi"
+
+/ {
+	model = "fsl,P3041DS";
+	compatible = "fsl,P3041DS";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+};

arch/powerpc/dts/p4080.dtsi

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P4080/P4040 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500mc_power_isa.dtsi"
+
+/ {
+	compatible = "fsl,P4080";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,e500mc@0 {
+			device_type = "cpu";
+			reg = <0>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu1: PowerPC,e500mc@1 {
+			device_type = "cpu";
+			reg = <1>;
+			fsl,portid-mapping = <0x40000000>;
+		};
+		cpu2: PowerPC,e500mc@2 {
+			device_type = "cpu";
+			reg = <2>;
+			fsl,portid-mapping = <0x20000000>;
+		};
+		cpu3: PowerPC,e500mc@3 {
+			device_type = "cpu";
+			reg = <3>;
+			fsl,portid-mapping = <0x10000000>;
+		};
+		cpu4: PowerPC,e500mc@4 {
+			device_type = "cpu";
+			reg = <4>;
+			fsl,portid-mapping = <0x08000000>;
+		};
+		cpu5: PowerPC,e500mc@5 {
+			device_type = "cpu";
+			reg = <5>;
+			fsl,portid-mapping = <0x04000000>;
+		};
+		cpu6: PowerPC,e500mc@6 {
+			device_type = "cpu";
+			reg = <6>;
+			fsl,portid-mapping = <0x02000000>;
+		};
+		cpu7: PowerPC,e500mc@7 {
+			device_type = "cpu";
+			reg = <7>;
+			fsl,portid-mapping = <0x01000000>;
+		};
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+
+		mpic: pic@40000 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <4>;
+			reg = <0x40000 0x40000>;
+			compatible = "fsl,mpic", "chrp,open-pic";
+			device_type = "open-pic";
+			clock-frequency = <0x0>;
+		};
+	};
+};

arch/powerpc/dts/p4080ds.dts

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P4080DS Device Tree Source
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p4080.dtsi"
+
+/ {
+	model = "fsl,P4080DS";
+	compatible = "fsl,P4080DS";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+};

arch/powerpc/dts/p5040.dtsi

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P5040 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e5500_power_isa.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,e5500@0 {
+			device_type = "cpu";
+			reg = <0>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu1: PowerPC,e5500@1 {
+			device_type = "cpu";
+			reg = <1>;
+			fsl,portid-mapping = <0x40000000>;
+		};
+		cpu2: PowerPC,e5500@2 {
+			device_type = "cpu";
+			reg = <2>;
+			fsl,portid-mapping = <0x20000000>;
+		};
+		cpu3: PowerPC,e5500@3 {
+			device_type = "cpu";
+			reg = <3>;
+			fsl,portid-mapping = <0x10000000>;
+		};
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+
+		mpic: pic@40000 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <4>;
+			reg = <0x40000 0x40000>;
+			compatible = "fsl,mpic", "chrp,open-pic";
+			device_type = "open-pic";
+			clock-frequency = <0x0>;
+		};
+	};
+};

arch/powerpc/dts/p5040ds.dts

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P5040DS Device Tree Source
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p5040.dtsi"
+
+/ {
+	model = "fsl,P5040DS";
+	compatible = "fsl,P5040DS";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+};

arch/powerpc/dts/t1024rdb.dts

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T1024RDB Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "t102x.dtsi"
+
+/ {
+	model = "fsl,T1024RDB";
+	compatible = "fsl,T1024RDB";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+};

arch/powerpc/dts/t102x.dtsi

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T102X Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e5500_power_isa.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,e5500@0 {
+			device_type = "cpu";
+			reg = <0>;
+			#cooling-cells = <2>;
+		};
+		cpu1: PowerPC,e5500@1 {
+			device_type = "cpu";
+			reg = <1>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+
+		mpic: pic@40000 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <4>;
+			reg = <0x40000 0x40000>;
+			compatible = "fsl,mpic", "chrp,open-pic";
+			device_type = "open-pic";
+			clock-frequency = <0x0>;
+		};
+	};
+};

arch/powerpc/dts/t1042d4rdb.dts

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T1042D4RDB Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "t104x.dtsi"
+
+/ {
+	model = "fsl,T1042D4RDB";
+	compatible = "fsl,T1042D4RDB";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+};

arch/powerpc/dts/t104x.dtsi

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T104X Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e5500_power_isa.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,e5500@0 {
+			device_type = "cpu";
+			reg = <0>;
+			#cooling-cells = <2>;
+		};
+		cpu1: PowerPC,e5500@1 {
+			device_type = "cpu";
+			reg = <1>;
+			#cooling-cells = <2>;
+		};
+		cpu2: PowerPC,e5500@2 {
+			device_type = "cpu";
+			reg = <2>;
+			#cooling-cells = <2>;
+		};
+		cpu3: PowerPC,e5500@3 {
+			device_type = "cpu";
+			reg = <3>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+
+		mpic: pic@40000 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <4>;
+			reg = <0x40000 0x40000>;
+			compatible = "fsl,mpic", "chrp,open-pic";
+			device_type = "open-pic";
+			clock-frequency = <0x0>;
+		};
+	};
+};

arch/powerpc/dts/t2080rdb.dts

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T2080RDB Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "t2080.dtsi"
+
+/ {
+	model = "fsl,T2080RDB";
+	compatible = "fsl,T2080RDB";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+};

arch/powerpc/dts/t4240.dtsi

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T4240 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e6500_power_isa.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,e6500@0 {
+			device_type = "cpu";
+			reg = <0 1>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu1: PowerPC,e6500@2 {
+			device_type = "cpu";
+			reg = <2 3>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu2: PowerPC,e6500@4 {
+			device_type = "cpu";
+			reg = <4 5>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu3: PowerPC,e6500@6 {
+			device_type = "cpu";
+			reg = <6 7>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu4: PowerPC,e6500@8 {
+			device_type = "cpu";
+			reg = <8 9>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu5: PowerPC,e6500@10 {
+			device_type = "cpu";
+			reg = <10 11>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu6: PowerPC,e6500@12 {
+			device_type = "cpu";
+			reg = <12 13>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu7: PowerPC,e6500@14 {
+			device_type = "cpu";
+			reg = <14 15>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu8: PowerPC,e6500@16 {
+			device_type = "cpu";
+			reg = <16 17>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu9: PowerPC,e6500@18 {
+			device_type = "cpu";
+			reg = <18 19>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu10: PowerPC,e6500@20 {
+			device_type = "cpu";
+			reg = <20 21>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu11: PowerPC,e6500@22 {
+			device_type = "cpu";
+			reg = <22 23>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+
+		mpic: pic@40000 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <4>;
+			reg = <0x40000 0x40000>;
+			compatible = "fsl,mpic";
+			device_type = "open-pic";
+			clock-frequency = <0x0>;
+		};
+	};
+};

arch/powerpc/dts/t4240rdb.dts

+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T4240RDB Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "t4240.dtsi"
+
+/ {
+	model = "fsl,T4240RDB";
+	compatible = "fsl,T4240RDB";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+};

arch/powerpc/dts/u-boot.dtsi

@@ -24,6 +24,9 @@
 #endif
 		};
 #ifdef CONFIG_MPC85XX_HAVE_RESET_VECTOR
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#endif
 		powerpc-mpc85xx-bootpg-resetvec {
 			offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
 		};

board/freescale/p1_p2_rdb_pc/README

@@ -45,3 +45,22 @@ enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below
 
 'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
 'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.
+
+Device tree support and how to enable it for different configs
+--------------------------------------------------------------
+Device tree support is available for p1020rdb and p2020rdb for below mentioned boot,
+1. NOR Boot
+2. NAND Boot
+3. SD Boot
+4. SPIFLASH Boot
+
+To enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+1. CONFIG_DEFAULT_DEVICE_TREE="p1020rdb" (Change default device tree name if required)
+2. CONFIG_OF_CONTROL
+3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
+   CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+
+If device tree support is enabled in defconfig,
+1. use 'u-boot-with-dtb.bin' for NOR boot.
+2. use 'u-boot-with-spl.bin' for other boot.

board/freescale/p2041rdb/README

@@ -85,6 +85,24 @@ Boot from SPI flash
 	SW1[1-5] = 10100
 	Note: 1 stands for 'on', 0 stands for 'off'
 
+Device tree support and how to enable it for different configs
+--------------------------------------------------------------
+Device tree support is available for p2041rdb for below mentioned boot,
+1. NOR Boot
+2. NAND Boot
+3. SD Boot
+4. SPIFLASH Boot
+
+To enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required)
+2. CONFIG_OF_CONTROL
+3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
+   CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+
+If device tree support is enabled in defconfig, use 'u-boot-with-dtb.bin'
+instead of u-boot.bin for all boot.
+
 CPLD command
 ============
 The CPLD is used to control the power sequence and some serdes lane

board/freescale/t102xrdb/README

@@ -251,6 +251,25 @@ Software configurations and board settings
    SW3[3] = '0' for eMMC (or 'switch emmc' by software)
 
 
+device tree support and how to enable it for different configs
+--------------------------------------------------------------
+device tree support is available for t1024rdb for below mentioned boot,
+1. nor boot
+2. nand boot
+3. sd boot
+4. spiflash boot
+
+to enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+1. config_default_device_tree="t1024rdb" (change default device tree name if required)
+2. config_of_control
+3. config_mpc85xx_have_reset_vector if reset vector is located at
+   config_reset_vector_address - 0xffc
+
+if device tree support is enabled in defconfig,
+1. use 'u-boot-with-dtb.bin' for nor boot.
+2. use 'u-boot-with-spl-pbl.bin' for other boot.
+
 2-stage NAND/SPI/SD boot loader
 -------------------------------
 PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.

board/freescale/t104xrdb/README

@@ -365,3 +365,22 @@ to
 2. SPI does not support flush so remove flush from pbl, make changes in
    tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
    with 0x091380c0
+
+Device tree support and how to enable it for different configs
+--------------------------------------------------------------
+Device tree support is available for t1042d4rdb for below mentioned boot,
+1. NOR Boot
+2. NAND Boot
+3. SD Boot
+4. SPIFLASH Boot
+
+To enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+1. CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" (Change default device tree name if required)
+2. CONFIG_OF_CONTROL
+3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
+   CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+
+If device tree support is enabled in defconfig,
+1. use 'u-boot-with-dtb.bin' for NOR boot.
+2. use 'u-boot-with-spl-pbl.bin' for other boot.

board/freescale/t208xrdb/README

@@ -262,3 +262,22 @@ How to update the ucode of Freescale FMAN
 
 For more details, please refer to T2080PCIe-RDB User Guide and access
 website www.freescale.com and Freescale QorIQ SDK Infocenter document.
+
+Device tree support and how to enable it for different configs
+--------------------------------------------------------------
+Device tree support is available for t2080rdb for below mentioned boot,
+1. NOR Boot
+2. NAND Boot
+3. SD Boot
+4. SPIFLASH Boot
+
+To enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+1. CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" (Change default device tree name if required)
+2. CONFIG_OF_CONTROL
+3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
+   CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+
+If device tree support is enabled in defconfig,
+1. use 'u-boot-with-dtb.bin' for NOR boot.
+2. use 'u-boot-with-spl-pbl.bin' for other boot.

configs/MPC8548CDS_36BIT_defconfig

 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF80000
 CONFIG_MPC85xx=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8548CDS=y
+CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b"
+CONFIG_OF_CONTROL=y
 CONFIG_PHYS_64BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y

configs/MPC8548CDS_defconfig

 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF80000
 CONFIG_MPC85xx=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8548CDS=y
+CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
+CONFIG_OF_CONTROL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=10

configs/MPC8548CDS_legacy_defconfig

 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF80000
 CONFIG_MPC85xx=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8548CDS=y
+CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
+CONFIG_OF_CONTROL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"

configs/P1020RDB-PC_36BIT_NAND_defconfig

@@ -42,6 +42,8 @@ CONFIG_MP=y
 # CONFIG_CMD_HASH is not set
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -63,4 +65,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P1020RDB-PC_36BIT_SDCARD_defconfig

@@ -38,6 +38,8 @@ CONFIG_MP=y
 # CONFIG_CMD_HASH is not set
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -58,4 +60,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig

@@ -39,6 +39,8 @@ CONFIG_MP=y
 # CONFIG_CMD_HASH is not set
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -59,4 +61,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P1020RDB-PC_36BIT_defconfig

@@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -26,6 +27,8 @@ CONFIG_MP=y
 # CONFIG_CMD_HASH is not set
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -46,4 +49,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P1020RDB-PC_NAND_defconfig

@@ -41,6 +41,8 @@ CONFIG_MP=y
 # CONFIG_CMD_HASH is not set
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -62,4 +64,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P1020RDB-PC_SDCARD_defconfig

@@ -37,6 +37,8 @@ CONFIG_MP=y
 # CONFIG_CMD_HASH is not set
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -57,4 +59,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P1020RDB-PC_SPIFLASH_defconfig

@@ -38,6 +38,8 @@ CONFIG_MP=y
 # CONFIG_CMD_HASH is not set
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -58,4 +60,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P1020RDB-PC_defconfig

@@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -25,6 +26,8 @@ CONFIG_MP=y
 # CONFIG_CMD_HASH is not set
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -45,4 +48,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P1020RDB-PD_NAND_defconfig

@@ -44,6 +44,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -66,4 +68,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P1020RDB-PD_SDCARD_defconfig

@@ -40,6 +40,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -61,4 +63,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P1020RDB-PD_SPIFLASH_defconfig

@@ -41,6 +41,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -62,4 +64,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P1020RDB-PD_defconfig

@@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P1020RDB_PD=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -28,6 +29,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -49,4 +52,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P2020RDB-PC_36BIT_NAND_defconfig

@@ -46,6 +46,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -68,4 +70,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P2020RDB-PC_36BIT_SDCARD_defconfig

@@ -42,6 +42,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -63,4 +65,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig

@@ -43,6 +43,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -64,4 +66,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P2020RDB-PC_36BIT_defconfig

@@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_PHYS_64BIT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -30,6 +31,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -51,4 +54,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P2020RDB-PC_NAND_defconfig

@@ -45,6 +45,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -67,4 +69,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P2020RDB-PC_SDCARD_defconfig

@@ -41,6 +41,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -62,4 +64,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P2020RDB-PC_SPIFLASH_defconfig

@@ -42,6 +42,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -63,4 +65,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P2020RDB-PC_defconfig

@@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_P2020RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -29,6 +30,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -50,4 +53,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P2041RDB_NAND_defconfig

@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -23,6 +24,8 @@ CONFIG_CMD_PING=y
 CONFIG_MP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -46,4 +49,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P2041RDB_SDCARD_defconfig

@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -23,6 +24,8 @@ CONFIG_CMD_PING=y
 CONFIG_MP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -45,4 +48,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P2041RDB_SPIFLASH_defconfig

@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -23,6 +24,8 @@ CONFIG_CMD_PING=y
 CONFIG_MP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -45,4 +48,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P2041RDB_defconfig

@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -22,6 +23,8 @@ CONFIG_CMD_PING=y
 CONFIG_MP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -44,4 +47,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P3041DS_NAND_defconfig

@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -23,6 +24,8 @@ CONFIG_CMD_PING=y
 CONFIG_MP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -46,4 +49,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P3041DS_SDCARD_defconfig

@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -23,6 +24,8 @@ CONFIG_CMD_PING=y
 CONFIG_MP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -45,4 +48,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P3041DS_SPIFLASH_defconfig

@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -23,6 +24,8 @@ CONFIG_CMD_PING=y
 CONFIG_MP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -45,4 +48,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P3041DS_defconfig

@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -22,6 +23,8 @@ CONFIG_CMD_PING=y
 CONFIG_MP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -44,4 +47,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P4080DS_SDCARD_defconfig

@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P4080DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -23,6 +24,8 @@ CONFIG_CMD_PING=y
 CONFIG_MP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -45,4 +48,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P4080DS_SPIFLASH_defconfig

@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P4080DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -23,6 +24,8 @@ CONFIG_CMD_PING=y
 CONFIG_MP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -45,4 +48,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P4080DS_defconfig

@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P4080DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -22,6 +23,8 @@ CONFIG_CMD_PING=y
 CONFIG_MP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -44,4 +47,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P5040DS_NAND_defconfig

@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -24,6 +25,8 @@ CONFIG_CMD_PING=y
 CONFIG_MP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -47,4 +50,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P5040DS_SDCARD_defconfig

@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -24,6 +25,8 @@ CONFIG_CMD_PING=y
 CONFIG_MP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -46,4 +49,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P5040DS_SPIFLASH_defconfig

@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -24,6 +25,8 @@ CONFIG_CMD_PING=y
 CONFIG_MP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -46,4 +49,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/P5040DS_defconfig

@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -23,6 +24,8 @@ CONFIG_CMD_PING=y
 CONFIG_MP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -45,4 +48,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/T1024RDB_NAND_defconfig

@@ -45,6 +45,8 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
@@ -70,4 +72,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/T1024RDB_SDCARD_defconfig

@@ -43,6 +43,8 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
@@ -67,4 +69,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/T1024RDB_SPIFLASH_defconfig

@@ -44,6 +44,8 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
@@ -68,4 +70,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/T1024RDB_defconfig

@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -29,6 +30,8 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
@@ -53,4 +56,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/T1042D4RDB_NAND_defconfig

@@ -44,6 +44,8 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -70,4 +72,3 @@ CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y
-CONFIG_OF_LIBFDT=y

configs/T1042D4RDB_SDCARD_defconfig

@@ -42,6 +42,8 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -67,4 +69,3 @@ CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y
-CONFIG_OF_LIBFDT=y

configs/T1042D4RDB_SPIFLASH_defconfig

@@ -43,6 +43,8 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -68,4 +70,3 @@ CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y
-CONFIG_OF_LIBFDT=y

configs/T1042D4RDB_defconfig

@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -28,6 +29,8 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -53,4 +56,3 @@ CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y
-CONFIG_OF_LIBFDT=y

configs/T2080RDB_NAND_defconfig

@@ -42,6 +42,8 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
 # CONFIG_CMD_IRQ is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -66,4 +68,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/T2080RDB_SDCARD_defconfig

@@ -40,6 +40,8 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
 # CONFIG_CMD_IRQ is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -63,4 +65,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/T2080RDB_SPIFLASH_defconfig

@@ -41,6 +41,8 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
 # CONFIG_CMD_IRQ is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -64,4 +66,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/T2080RDB_defconfig

@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -26,6 +27,8 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
 # CONFIG_CMD_IRQ is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -49,4 +52,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/T4240RDB_SDCARD_defconfig

@@ -35,6 +35,8 @@ CONFIG_CMD_PING=y
 CONFIG_MP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -57,4 +59,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

configs/T4240RDB_defconfig

@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -21,6 +22,8 @@ CONFIG_CMD_PING=y
 CONFIG_MP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
@@ -43,4 +46,3 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y

drivers/ddr/fsl/main.c

@@ -10,6 +10,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <i2c.h>
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr.h>
@@ -82,20 +83,82 @@ u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
 
 #endif
 
+#if defined(CONFIG_DM_I2C)
+#define DEV_TYPE struct udevice
+#else
+/* Local udevice */
+struct ludevice {
+	u8 chip;
+};
+
+#define DEV_TYPE struct ludevice
+
+#endif
+
 #define SPD_SPA0_ADDRESS	0x36
 #define SPD_SPA1_ADDRESS	0x37
 
-static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
+static int ddr_i2c_read(DEV_TYPE *dev, unsigned int addr,
+			int alen, uint8_t *buf, int len)
 {
 	int ret;
+
+#ifdef CONFIG_DM_I2C
+	ret = dm_i2c_read(dev, 0, buf, len);
+#else
+	ret = i2c_read(dev->chip, addr, alen, buf, len);
+#endif
+
+	return ret;
+}
+
 #ifdef CONFIG_SYS_FSL_DDR4
-	uint8_t dummy = 0;
+static int ddr_i2c_dummy_write(unsigned int chip_addr)
+{
+	uint8_t buf = 0;
+
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, chip_addr,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       CONFIG_SYS_SPD_BUS_NUM);
+		return ret;
+	}
+
+	return dm_i2c_write(dev, 0, &buf, 1);
+#else
+	return i2c_write(chip_addr, 0, 1, &buf, 1);
 #endif
 
-#ifndef CONFIG_DM_I2C
-	i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
+	return 0;
+}
 #endif
 
+static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
+{
+	int ret;
+	DEV_TYPE *dev;
+
+#if defined(CONFIG_DM_I2C)
+	ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, i2c_address,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       CONFIG_SYS_SPD_BUS_NUM);
+		return;
+	}
+#else /* Non DM I2C support - will be removed */
+	struct ludevice ldev = {
+		.chip = i2c_address,
+	};
+	dev = &ldev;
+
+	i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
+#endif
 
 #ifdef CONFIG_SYS_FSL_DDR4
 	/*
@@ -104,49 +167,19 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
 	 * To access the upper 256 bytes, we need to set EE page address to 1
 	 * See Jedec standar No. 21-C for detail
 	 */
-#ifndef CONFIG_DM_I2C
-	i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1);
-	ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256);
+	ddr_i2c_dummy_write(SPD_SPA0_ADDRESS);
+	ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd, 256);
 	if (!ret) {
-		i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1);
-		ret = i2c_read(i2c_address, 0, 1,
-			       (uchar *)((ulong)spd + 256),
-			       min(256,
-				   (int)sizeof(generic_spd_eeprom_t) - 256));
+		ddr_i2c_dummy_write(SPD_SPA1_ADDRESS);
+		ret = ddr_i2c_read(dev, 0, 1, (uchar *)((ulong)spd + 256),
+				   min(256,
+				       (int)sizeof(generic_spd_eeprom_t)
+				       - 256));
 	}
-#else
-	struct udevice *dev;
-	int read_len = min(256, (int)sizeof(generic_spd_eeprom_t) - 256);
 
-	ret = i2c_get_chip_for_busnum(0, SPD_SPA0_ADDRESS, 1, &dev);
-	if (!ret)
-		dm_i2c_write(dev, 0, &dummy, 1);
-	ret = i2c_get_chip_for_busnum(0, i2c_address, 1, &dev);
-	if (!ret) {
-		if (!dm_i2c_read(dev, 0, (uchar *)spd, 256)) {
-			if (!i2c_get_chip_for_busnum(0, SPD_SPA1_ADDRESS,
-						     1, &dev))
-				dm_i2c_write(dev, 0, &dummy, 1);
-			if (!i2c_get_chip_for_busnum(0, i2c_address, 1, &dev))
-				ret = dm_i2c_read(dev, 0,
-						  (uchar *)((ulong)spd + 256),
-						  read_len);
-		}
-	}
-#endif
-
-#else
-
-#ifndef CONFIG_DM_I2C
-	ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
-			sizeof(generic_spd_eeprom_t));
 #else
-	ret = i2c_get_chip_for_busnum(0, i2c_address, 1, &dev);
-	if (!ret)
-		ret = dm_i2c_read(dev, 0, (uchar *)spd,
-				  sizeof(generic_spd_eeprom_t));
-#endif
-
+	ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd,
+			   sizeof(generic_spd_eeprom_t));
 #endif
 
 	if (ret) {

include/configs/MPC8548CDS.h

@@ -289,7 +289,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */