ARM: non-sec: flush code cacheline aligned
Flush operations need to be cacheline aligned to take effect, make sure to flush always complete cachelines. This avoids messages such as: CACHE: Misaligned operation at range [00900000, 009004d9] Signed-off-by: NStefan Agner <stefan.agner@toradex.com> Tested-by: NFabio Estevam <fabio.estevam@nxp.com>
Showing
想要评论请 注册 或 登录