Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx

- mpc85xx, socrates: Add dts, enable DM support, fix warnings, disable
  video

MAINTAINERS

@@ -701,6 +701,11 @@ S:	Maintained
 F:	drivers/pci_endpoint/
 F:  include/pci_ep.h
 
+PCI MPC85xx
+M:	Heiko Schocher <hs@denx.de>
+S:	Maintained
+F:	drivers/pci/pci_mpc85xx.c
+
 POWER
 M:	Jaehoon Chung <jh80.chung@samsung.com>
 S:	Maintained

arch/powerpc/dts/Makefile

@@ -8,6 +8,7 @@ dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb
 dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb
 dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb
 dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb
+dtb-$(CONFIG_TARGET_SOCRATES) += socrates.dtb
 dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
 dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
 dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb

arch/powerpc/dts/socrates-u-boot.dtsi

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de
+ */
+/ {
+	binman {
+		filename = "u-boot-socrates.bin";
+		pad-byte = <0xff>;
+		// Place dtb one sector before u-boot-nodtb.bin
+		blob {
+			filename = "dts/dt.dtb";
+		};
+		u-boot-nodtb {
+			filename = "u-boot-nodtb.bin";
+			offset = <0x20000>;
+		};
+	};
+
+	chosen {
+		stdout-path = &serial0;
+	};
+
+	soc8544@e0000000 {
+		i2c@3000 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
+
+&pci0 {
+	clock-frequency = <33000000>;
+	ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+		  0x01000000 0x0 0xe2000000 0xe2000000 0x0 0x01000000>;
+};
+
+&serial0 {
+	u-boot,dm-pre-reloc;
+	clock-frequency = <333333330>;
+};

arch/powerpc/dts/socrates.dts

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree Source for the Socrates board (MPC8544).
+ *
+ * Copyright (c) 2008 Emcraft Systems.
+ * Sergei Poselenov, <sposelenov@emcraft.com>
+ *
+ */
+
+/dts-v1/;
+
+/ {
+	model = "abb,socrates";
+	compatible = "abb,socrates";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		serial0 = &serial0;
+		serial1 = &serial1;
+		pci0 = &pci0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,8544@0 {
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;	// L1, 32K
+			i-cache-size = <0x8000>;	// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			next-level-cache = <&L2>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x00000000>;	// Filled in by U-Boot
+	};
+
+	soc8544@e0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+
+		ranges = <0x00000000 0xe0000000 0x00100000>;
+		bus-frequency = <0>;		// Filled in by U-Boot
+		compatible = "fsl,mpc8544-immr", "simple-bus";
+
+		ecm-law@0 {
+			compatible = "fsl,ecm-law";
+			reg = <0x0 0x1000>;
+			fsl,num-laws = <10>;
+		};
+
+		ecm@1000 {
+			compatible = "fsl,mpc8544-ecm", "fsl,ecm";
+			reg = <0x1000 0x1000>;
+			interrupts = <17 2>;
+			interrupt-parent = <&mpic>;
+		};
+
+		memory-controller@2000 {
+			compatible = "fsl,mpc8544-memory-controller";
+			reg = <0x2000 0x1000>;
+			interrupt-parent = <&mpic>;
+			interrupts = <18 2>;
+		};
+
+		L2: l2-cache-controller@20000 {
+			compatible = "fsl,mpc8544-l2-cache-controller";
+			reg = <0x20000 0x1000>;
+			cache-line-size = <32>;
+			cache-size = <0x40000>;	// L2, 256K
+			interrupt-parent = <&mpic>;
+			interrupts = <16 2>;
+		};
+
+		i2c@3000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			compatible = "fsl,mpc8544-i2c", "fsl-i2c";
+			reg = <0x3000 0x100>;
+			interrupts = <43 2>;
+			interrupt-parent = <&mpic>;
+			fsl,preserve-clocking;
+
+			dtt@28 {
+				compatible = "winbond,w83782d";
+				reg = <0x28>;
+			};
+			rtc@32 {
+				compatible = "epson,rx8025";
+				reg = <0x32>;
+				interrupts = <7 1>;
+				interrupt-parent = <&mpic>;
+			};
+			dtt@4c {
+				compatible = "dallas,ds75";
+				reg = <0x4c>;
+			};
+			ts@4a {
+				compatible = "ti,tsc2003";
+				reg = <0x4a>;
+				interrupt-parent = <&mpic>;
+				interrupts = <8 1>;
+			};
+		};
+
+		i2c@3100 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <1>;
+			compatible = "fsl,mpc8544-i2c", "fsl-i2c";
+			reg = <0x3100 0x100>;
+			interrupts = <43 2>;
+			interrupt-parent = <&mpic>;
+			fsl,preserve-clocking;
+		};
+
+		enet0: ethernet@24000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			cell-index = <0>;
+			device_type = "network";
+			model = "eTSEC";
+			compatible = "gianfar";
+			reg = <0x24000 0x1000>;
+			ranges = <0x0 0x24000 0x1000>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <29 2 30 2 34 2>;
+			interrupt-parent = <&mpic>;
+			phy-handle = <&phy0>;
+			tbi-handle = <&tbi0>;
+			phy-connection-type = "rgmii-id";
+
+			mdio@520 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,gianfar-mdio";
+				reg = <0x520 0x20>;
+
+				phy0: ethernet-phy@0 {
+					interrupt-parent = <&mpic>;
+					interrupts = <0 1>;
+					reg = <0>;
+				};
+				phy1: ethernet-phy@1 {
+					interrupt-parent = <&mpic>;
+					interrupts = <0 1>;
+					reg = <1>;
+				};
+				tbi0: tbi-phy@11 {
+					reg = <0x11>;
+				};
+			};
+		};
+
+		enet1: ethernet@26000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			cell-index = <1>;
+			device_type = "network";
+			model = "eTSEC";
+			compatible = "gianfar";
+			reg = <0x26000 0x1000>;
+			ranges = <0x0 0x26000 0x1000>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <31 2 32 2 33 2>;
+			interrupt-parent = <&mpic>;
+			phy-handle = <&phy1>;
+			tbi-handle = <&tbi1>;
+			phy-connection-type = "rgmii-id";
+
+			mdio@520 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,gianfar-tbi";
+				reg = <0x520 0x20>;
+
+				tbi1: tbi-phy@11 {
+					reg = <0x11>;
+				};
+			};
+		};
+
+		serial0: serial@4500 {
+			cell-index = <0>;
+			device_type = "serial";
+			compatible = "fsl,ns16550", "ns16550";
+			reg = <0x4500 0x100>;
+			clock-frequency = <0>;
+			interrupts = <42 2>;
+			interrupt-parent = <&mpic>;
+		};
+
+		serial1: serial@4600 {
+			cell-index = <1>;
+			device_type = "serial";
+			compatible = "fsl,ns16550", "ns16550";
+			reg = <0x4600 0x100>;
+			clock-frequency = <0>;
+			interrupts = <42 2>;
+			interrupt-parent = <&mpic>;
+		};
+
+		global-utilities@e0000 {	//global utilities block
+			compatible = "fsl,mpc8548-guts";
+			reg = <0xe0000 0x1000>;
+			fsl,has-rstcr;
+		};
+
+		mpic: pic@40000 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			reg = <0x40000 0x40000>;
+			compatible = "chrp,open-pic";
+			device_type = "open-pic";
+		};
+	};
+
+
+	localbus {
+		compatible = "fsl,mpc8544-localbus",
+		             "fsl,pq3-localbus",
+			     "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		reg = <0xe0005000 0x40>;
+		interrupt-parent = <&mpic>;
+		interrupts = <19 2>;
+
+		ranges = <0 0 0xfc000000 0x04000000
+			  2 0 0xc8000000 0x04000000
+			  3 0 0xc0000000 0x00100000
+			>; /* Overwritten by U-Boot */
+
+		nor_flash@0,0 {
+			compatible = "amd,s29gl256n", "cfi-flash";
+			bank-width = <2>;
+			reg = <0x0 0x000000 0x4000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			partition@0 {
+				label = "kernel";
+				reg = <0x0 0x1e0000>;
+				read-only;
+			};
+			partition@1e0000 {
+				label = "dtb";
+				reg = <0x1e0000 0x20000>;
+			};
+			partition@200000 {
+				label = "root";
+				reg = <0x200000 0x200000>;
+			};
+			partition@400000 {
+				label = "user";
+				reg = <0x400000 0x3b80000>;
+			};
+			partition@3f80000 {
+				label = "env";
+				reg = <0x3f80000 0x40000>;
+				read-only;
+			};
+			partition@3fc0000 {
+				label = "u-boot";
+				reg = <0x3fc0000 0x40000>;
+				read-only;
+			};
+		};
+
+		display@2,0 {
+			compatible = "fujitsu,lime";
+			reg = <2 0x0 0x4000000>;
+			interrupt-parent = <&mpic>;
+			interrupts = <6 1>;
+		};
+
+		fpga_pic: fpga-pic@3,10 {
+			compatible = "abb,socrates-fpga-pic";
+			reg = <3 0x10 0x10>;
+			interrupt-controller;
+			/* IRQs 2, 10, 11, active low, level-sensitive */
+			interrupts = <2 1 10 1 11 1>;
+			interrupt-parent = <&mpic>;
+			#interrupt-cells = <3>;
+		};
+
+		spi@3,60 {
+			compatible = "abb,socrates-spi";
+			reg = <3 0x60 0x10>;
+			interrupts = <8 4 0>;	// number, type, routing
+			interrupt-parent = <&fpga_pic>;
+		};
+
+		nand@3,70 {
+			compatible = "abb,socrates-nand";
+			reg = <3 0x70 0x04>;
+			bank-width = <1>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			data@0 {
+				label = "data";
+				reg = <0x0 0x40000000>;
+			};
+		};
+
+		can@3,100 {
+			compatible = "philips,sja1000";
+			reg = <3 0x100 0x80>;
+			interrupts = <2 8 1>;	// number, type, routing
+			interrupt-parent = <&fpga_pic>;
+		};
+	};
+
+	pci0: pci@e0008000 {
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		compatible = "fsl,mpc8540-pci";
+		device_type = "pci";
+		reg = <0xe0008000 0x1000>;
+		clock-frequency = <66666666>;
+
+		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+		interrupt-map = <
+				/* IDSEL 0x11 */
+				 0x8800 0x0 0x0 1 &mpic 5 1
+				/* IDSEL 0x12 */
+				 0x9000 0x0 0x0 1 &mpic 4 1>;
+		interrupt-parent = <&mpic>;
+		interrupts = <24 2>;
+		bus-range = <0x0 0x0>;
+		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
+	};
+
+};

board/socrates/MAINTAINERS

 SOCRATES BOARD
-#M:	-
+M:	Heiko Schocher <hs@denx.de>
 S:	Maintained
 F:	board/socrates/
 F:	include/configs/socrates.h
 F:	configs/socrates_defconfig
+F:	arch/powerpc/dts/socrates.dts
+F:	arch/powerpc/dts/socrates-u-boot.dtsi

board/socrates/law.c

@@ -31,9 +31,7 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
 	SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
 #if defined(CONFIG_SYS_FPGA_BASE)
 	SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 #endif

board/socrates/socrates.c

@@ -50,7 +50,7 @@ int checkboard (void)
 	}
 	putc('\n');
 
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) || defined(CONFIG_DM_PCI)
 	/* Check the PCI_clk sel bit */
 	if (in_be32(&gur->porpllsr) & (1<<15)) {
 		src = "SYSCLK";
@@ -126,6 +126,10 @@ int misc_init_r (void)
 			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 	}
 
+#if defined(CONFIG_DM_PCI)
+	pci_init();
+#endif
+
 	return 0;
 }
 
@@ -168,40 +172,6 @@ void local_bus_init (void)
 	upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int));
 }
 
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc85xxads_config_table[] = {
-	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
-	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
-				     PCI_ENET0_MEMADDR,
-				     PCI_COMMAND_MEMORY |
-				     PCI_COMMAND_MASTER}},
-	{}
-};
-#endif
-
-
-static struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
-	config_table:pci_mpc85xxads_config_table,
-#endif
-};
-
-#endif /* CONFIG_PCI */
-
-
-void pci_init_board (void)
-{
-#ifdef CONFIG_PCI
-	pci_mpc85xx_init (&hose);
-#endif /* CONFIG_PCI */
-}
-
 #ifdef CONFIG_BOARD_EARLY_INIT_R
 int board_early_init_r (void)
 {
@@ -231,6 +201,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	val[i++] = gd->bd->bi_flashstart;
 	val[i++] = gd->bd->bi_flashsize;
 
+#if defined(CONFIG_VIDEO_MB862xx)
 	if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
 		/* Fixup LIME mapping */
 		val[i++] = 2;			/* chip select number */
@@ -238,6 +209,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 		val[i++] = CONFIG_SYS_LIME_BASE;
 		val[i++] = CONFIG_SYS_LIME_SIZE;
 	}
+#endif
 
 	/* Fixup FPGA mapping */
 	val[i++] = 3;				/* chip select number */
@@ -255,180 +227,22 @@ int ft_board_setup(void *blob, bd_t *bd)
 }
 #endif /* CONFIG_OF_BOARD_SETUP */
 
-#define DEFAULT_BRIGHTNESS	25
-#define BACKLIGHT_ENABLE	(1 << 31)
-
-static const gdc_regs init_regs [] =
-{
-	{0x0100, 0x00010f00},
-	{0x0020, 0x801901df},
-	{0x0024, 0x00000000},
-	{0x0028, 0x00000000},
-	{0x002c, 0x00000000},
-	{0x0110, 0x00000000},
-	{0x0114, 0x00000000},
-	{0x0118, 0x01df0320},
-	{0x0004, 0x041f0000},
-	{0x0008, 0x031f031f},
-	{0x000c, 0x017f0349},
-	{0x0010, 0x020c0000},
-	{0x0014, 0x01df01e9},
-	{0x0018, 0x00000000},
-	{0x001c, 0x01e00320},
-	{0x0100, 0x80010f00},
-	{0x0, 0x0}
-};
-
-const gdc_regs *board_get_regs (void)
-{
-	return init_regs;
-}
-
-int lime_probe(void)
-{
-	uint cfg_br2;
-	uint cfg_or2;
-	int type;
-
-	cfg_br2 = get_lbc_br(2);
-	cfg_or2 = get_lbc_or(2);
-
-	/* Configure GPCM for CS2 */
-	set_lbc_br(2, 0);
-	set_lbc_or(2, 0xfc000410);
-	set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901);
-
-	/* Get controller type */
-	type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
-
-	/* Restore previous CS2 configuration */
-	set_lbc_br(2, 0);
-	set_lbc_or(2, cfg_or2);
-	set_lbc_br(2, cfg_br2);
-
-	return (type == MB862XX_TYPE_LIME) ? 1 : 0;
-}
-
-/* Returns Lime base address */
-unsigned int board_video_init (void)
-{
-	if (!lime_probe())
-		return 0;
-
-	mb862xx.winSizeX = 800;
-	mb862xx.winSizeY = 480;
-	mb862xx.gdfIndex = GDF_15BIT_555RGB;
-	mb862xx.gdfBytesPP = 2;
-
-	return CONFIG_SYS_LIME_BASE;
-}
-
-#define W83782D_REG_CFG		0x40
-#define W83782D_REG_BANK_SEL	0x4e
-#define W83782D_REG_ADCCLK	0x4b
-#define W83782D_REG_BEEP_CTRL	0x4d
-#define W83782D_REG_BEEP_CTRL2	0x57
-#define W83782D_REG_PWMOUT1	0x5b
-#define W83782D_REG_VBAT	0x5d
-
-static int w83782d_hwmon_init(void)
-{
-	u8 buf;
-
-	if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1))
-		return -1;
-
-	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80);
-	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0);
-	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40);
-
-	buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL);
-	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL,
-		      buf | 0x80);
-	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0);
-	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47);
-	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01);
-
-	buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG);
-	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG,
-		      (buf & 0xf4) | 0x01);
-	return 0;
-}
-
-static void board_backlight_brightness(int br)
+#if defined(CONFIG_OF_SEPARATE)
+void *board_fdt_blob_setup(void)
 {
-	u32 reg;
-	u8 buf;
-	u8 old_buf;
+	void *fw_dtb;
 
-	/* Select bank 0 */
-	if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
-		goto err;
-	else
-		buf = old_buf & 0xf8;
-
-	if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1))
-		goto err;
-
-	if (br > 0) {
-		/* PWMOUT1 duty cycle ctrl */
-		buf = 255 / (100 / br);
-		if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
-			goto err;
-
-		/* LEDs on */
-		reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
-		if (!(reg & BACKLIGHT_ENABLE))
-			out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c),
-				 reg | BACKLIGHT_ENABLE);
-	} else {
-		buf = 0;
-		if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
-			goto err;
-
-		/* LEDs off */
-		reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
-		reg &= ~BACKLIGHT_ENABLE;
-		out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg);
+	fw_dtb = (void *)(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE);
+	if (fdt_magic(fw_dtb) != FDT_MAGIC) {
+		printf("DTB is not passed via %x\n", (u32)fw_dtb);
+		return NULL;
 	}
-	/* Restore previous bank setting */
-	if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
-		goto err;
 
-	return;
-err:
-	printf("W83782G I2C access failed\n");
-}
-
-void board_backlight_switch (int flag)
-{
-	char * param;
-	int rc;
-
-	if (w83782d_hwmon_init())
-		printf ("hwmon IC init failed\n");
-
-	if (flag) {
-		param = env_get("brightness");
-		rc = param ? simple_strtol(param, NULL, 10) : -1;
-		if (rc < 0)
-			rc = DEFAULT_BRIGHTNESS;
-	} else {
-		rc = 0;
-	}
-	board_backlight_brightness(rc);
+	return fw_dtb;
 }
+#endif
 
-#if defined(CONFIG_CONSOLE_EXTRA_INFO)
-/*
- * Return text to be printed besides the logo.
- */
-void video_get_info_str (int line_number, char *info)
+int get_serial_clock(void)
 {
-	if (line_number == 1) {
-		strcpy (info, " Board: Socrates");
-	} else {
-		info [0] = '\0';
-	}
+	return 333333330;
 }
-#endif

configs/socrates_defconfig

@@ -14,7 +14,12 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_REGINFO=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
 CONFIG_CMD_IMLS=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_PCI=y
@@ -26,12 +31,16 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_DATE=y
 # CONFIG_CMD_HASH is not set
 CONFIG_CMD_EXT2=y
 # CONFIG_CMD_IRQ is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="socrates"
 CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_DM=y
+CONFIG_BLK=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_FSL=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
@@ -39,11 +48,16 @@ CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_MARVELL=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_MPC85XX=y
+CONFIG_DM_RTC=y
 CONFIG_RTC_RX8025=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 # CONFIG_USB_EHCI_HCD is not set
+CONFIG_USB_OHCI_PCI=y
 CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_CONSOLE_EXTRA_INFO=y
-CONFIG_OF_LIBFDT=y

drivers/pci/Kconfig

@@ -68,6 +68,13 @@ config PCIE_FSL
 	  PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs.
 	  This driver does not support SRIO_PCIE_BOOT feature.
 
+config PCI_MPC85XX
+	bool "MPC85XX PowerPC PCI support"
+	depends on DM_PCI
+	help
+	  Say Y here if you want to enable PCI controller support on FSL
+	  PowerPC MPC85xx SoC.
+
 config PCI_RCAR_GEN2
 	bool "Renesas RCar Gen2 PCIe driver"
 	depends on DM_PCI

drivers/pci/Makefile

@@ -19,6 +19,7 @@ obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o
 obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
 obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
 obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
+obj-$(CONFIG_PCI_MPC85XX) += pci_mpc85xx.o
 obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
 obj-$(CONFIG_PCIE_IMX) += pcie_imx.o
 obj-$(CONFIG_FTPCI100) += pci_ftpci100.o

drivers/pci/pci_mpc85xx.c

+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2019
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ */
+#include <common.h>
+#include <asm/cpm_85xx.h>
+#include <pci.h>
+#include <dm.h>
+#include <asm/fsl_law.h>
+
+struct mpc85xx_pci_priv {
+	void __iomem		*cfg_addr;
+	void __iomem		*cfg_data;
+};
+
+static int mpc85xx_pci_dm_read_config(struct udevice *dev, pci_dev_t bdf,
+				      uint offset, ulong *value,
+				      enum pci_size_t size)
+{
+	struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
+	u32 addr;
+
+	addr = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
+	out_be32(priv->cfg_addr, addr);
+	sync();
+	*value = pci_conv_32_to_size(in_le32(priv->cfg_data), offset, size);
+
+	return 0;
+}
+
+static int mpc85xx_pci_dm_write_config(struct udevice *dev, pci_dev_t bdf,
+				       uint offset, ulong value,
+				       enum pci_size_t size)
+{
+	struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
+	u32 addr;
+
+	addr = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
+	out_be32(priv->cfg_addr, addr);
+	sync();
+	out_le32(priv->cfg_data, pci_conv_size_to_32(0, value, offset, size));
+
+	return 0;
+}
+
+static int
+mpc85xx_pci_dm_setup_laws(struct pci_region *io, struct pci_region *mem,
+			  struct pci_region *pre)
+{
+	/*
+	 * Unfortunately we have defines for this addresse,
+	 * as we have to setup the TLB, and at this stage
+	 * we have no access to DT ... may we check here
+	 * if the value in the define is the same ?
+	 */
+	if (mem)
+		set_next_law(mem->phys_start, law_size_bits(mem->size),
+			     LAW_TRGT_IF_PCI);
+	if (io)
+		set_next_law(io->phys_start, law_size_bits(io->size),
+			     LAW_TRGT_IF_PCI);
+	if (pre)
+		set_next_law(pre->phys_start, law_size_bits(pre->size),
+			     LAW_TRGT_IF_PCI);
+
+	return 0;
+}
+
+static int mpc85xx_pci_dm_probe(struct udevice *dev)
+{
+	struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
+	struct pci_region *io;
+	struct pci_region *mem;
+	struct pci_region *pre;
+	int count;
+	ccsr_pcix_t *pcix;
+
+	count = pci_get_regions(dev, &io, &mem, &pre);
+	if (count != 2) {
+		printf("%s: wrong count of regions %d only 2 allowed\n",
+		       __func__, count);
+		return -EINVAL;
+	}
+
+	mpc85xx_pci_dm_setup_laws(io, mem, pre);
+
+	pcix = priv->cfg_addr;
+	/* BAR 1: memory */
+	out_be32(&pcix->potar1, (mem->bus_start >> 12) & 0x000fffff);
+	out_be32(&pcix->potear1, 0);
+	out_be32(&pcix->powbar1, (mem->phys_start >> 12) & 0x000fffff);
+	out_be32(&pcix->powbear1, 0);
+	out_be32(&pcix->powar1, (POWAR_EN | POWAR_MEM_READ |
+		 POWAR_MEM_WRITE | (__ilog2(mem->size) - 1)));
+
+	/* BAR 1: IO */
+	out_be32(&pcix->potar2, (io->bus_start >> 12) & 0x000fffff);
+	out_be32(&pcix->potear2, 0);
+	out_be32(&pcix->powbar2, (io->phys_start >> 12) & 0x000fffff);
+	out_be32(&pcix->powbear2, 0);
+	out_be32(&pcix->powar2, (POWAR_EN | POWAR_IO_READ |
+		 POWAR_IO_WRITE | (__ilog2(io->size) - 1)));
+
+	out_be32(&pcix->pitar1, 0);
+	out_be32(&pcix->piwbar1, 0);
+	out_be32(&pcix->piwar1, (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
+		 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G));
+
+	out_be32(&pcix->powar3, 0);
+	out_be32(&pcix->powar4, 0);
+	out_be32(&pcix->piwar2, 0);
+	out_be32(&pcix->piwar3, 0);
+
+	return 0;
+}
+
+static int mpc85xx_pci_dm_remove(struct udevice *dev)
+{
+	return 0;
+}
+
+static int mpc85xx_pci_ofdata_to_platdata(struct udevice *dev)
+{
+	struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
+	fdt_addr_t addr;
+
+	addr = devfdt_get_addr_index(dev, 0);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+	priv->cfg_addr = (void __iomem *)addr;
+	addr += 4;
+	priv->cfg_data = (void __iomem *)addr;
+
+	return 0;
+}
+
+static const struct dm_pci_ops mpc85xx_pci_ops = {
+	.read_config	= mpc85xx_pci_dm_read_config,
+	.write_config	= mpc85xx_pci_dm_write_config,
+};
+
+static const struct udevice_id mpc85xx_pci_ids[] = {
+	{ .compatible = "fsl,mpc8540-pci" },
+	{ }
+};
+
+U_BOOT_DRIVER(mpc85xx_pci) = {
+	.name			= "mpc85xx_pci",
+	.id			= UCLASS_PCI,
+	.of_match		= mpc85xx_pci_ids,
+	.ops			= &mpc85xx_pci_ops,
+	.probe			= mpc85xx_pci_dm_probe,
+	.remove			= mpc85xx_pci_dm_remove,
+	.ofdata_to_platdata	= mpc85xx_pci_ofdata_to_platdata,
+	.priv_auto_alloc_size	= sizeof(struct mpc85xx_pci_priv),
+};

include/configs/socrates.h

@@ -19,8 +19,6 @@
 /* High Level Configuration Options */
 #define CONFIG_SOCRATES		1
 
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
 /*
  * Only possible on E500 Version 2 or newer cores.
  */
@@ -96,6 +94,7 @@
  */
 #define CONFIG_SYS_LBC_CACHE_BASE	0xf0000000	/* Localbus cacheable	 */
 
+#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_SYS_FLASH0		0xFE000000
 #define CONFIG_SYS_FLASH1		0xFC000000
 #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
@@ -147,50 +146,7 @@
 #define CONFIG_SYS_BR2_PRELIM		0xc80018a1	/* UPMB, 32-bit	*/
 #define CONFIG_SYS_OR2_PRELIM		0xfc000000	/* 64 MB	*/
 
-#define CONFIG_VIDEO_MB862xx
-#define CONFIG_VIDEO_MB862xx_ACCEL
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define VIDEO_FB_16BPP_PIXEL_SWAP
-#define VIDEO_FB_16BPP_WORD_SWAP
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */
-
-/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
-#define CONFIG_SYS_MB862xx_CCF		0x10000
-/* SDRAM parameter */
-#define CONFIG_SYS_MB862xx_MMR		0x4157BA63
-
-/* Serial Port */
-
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	102124
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED	102124
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
-
-/* I2C RTC */
-#define CONFIG_SYS_I2C_RTC_ADDR	0x32	/* at address 0x32		*/
-
-/* I2C W83782G HW-Monitoring IC */
-#define CONFIG_SYS_I2C_W83782G_ADDR	0x28	/* W83782G address 		*/
+#define CONFIG_SYS_SPD_BUS_NUM 0
 
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
 
@@ -198,7 +154,6 @@
  * General PCI
  * Memory space is mapped 1-1.
  */
-#define CONFIG_SYS_PCI_PHYS		0x80000000	/* 1G PCI TLB */
 
 /* PCI is clocked by the external source at 33 MHz */
 #define CONFIG_PCI_CLK_FREQ	33000000
@@ -209,10 +164,6 @@
 #define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
 #define CONFIG_SYS_PCI1_IO_SIZE	0x01000000	/* 16M			*/
 
-#if defined(CONFIG_PCI)
-#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
-#endif	/* CONFIG_PCI */
-
 #define CONFIG_TSEC1	1
 #define CONFIG_TSEC1_NAME	"TSEC0"
 #define CONFIG_TSEC3	1
@@ -237,9 +188,10 @@
  * Environment
  */
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env	*/
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - \
+				CONFIG_ENV_SECT_SIZE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x4000
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
@@ -279,7 +231,7 @@
 	"bootfile=/home/tftp/syscon3/uImage\0"				\
 	"fdt_file=/home/tftp/syscon3/socrates.dtb\0"			\
 	"initrd_file=/home/tftp/syscon3/uinitrd.gz\0"			\
-	"uboot_addr=FFFA0000\0"						\
+	"uboot_addr=FFF60000\0"						\
 	"kernel_addr=FE000000\0"					\
 	"fdt_addr=FE1E0000\0"						\
 	"ramdisk_addr=FE200000\0"					\
@@ -302,9 +254,9 @@
 		"run nfsargs addip addcons;"				\
 		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
 	"update_uboot=tftp 100000 ${uboot_file};"			\
-		"protect off fffa0000 ffffffff;"			\
-		"era fffa0000 ffffffff;"				\
-		"cp.b 100000 fffa0000 ${filesize};"			\
+		"protect off fff60000 ffffffff;"			\
+		"era fff60000 ffffffff;"				\
+		"cp.b 100000 fff60000 ${filesize};"			\
 		"setenv filesize;saveenv\0"				\
 	"update_kernel=tftp 100000 ${bootfile};"			\
 		"era fe000000 fe1dffff;"				\
@@ -333,8 +285,6 @@
 /* USB support */
 #define CONFIG_USB_OHCI_NEW		1
 #define CONFIG_PCI_OHCI			1
-#define CONFIG_PCI_OHCI_DEVNO		3 /* Number in PCI list */
-#define CONFIG_PCI_EHCI_DEVNO		(CONFIG_PCI_OHCI_DEVNO / 2)
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"ohci_pci"
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1