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体验新版 GitCode,发现更多精彩内容 >>
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d8247774
编写于
1月 25, 2016
作者:
T
Tom Rini
浏览文件
操作
浏览文件
下载
差异文件
Merge branch 'master' of
git://git.denx.de/u-boot-mpc85xx
上级
ac01603d
2f66a828
变更
18
隐藏空白更改
内联
并排
Showing
18 changed file
with
53 addition
and
70 deletion
+53
-70
arch/powerpc/cpu/mpc83xx/law.c
arch/powerpc/cpu/mpc83xx/law.c
+2
-2
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/cpu_init.c
+11
-0
arch/powerpc/cpu/mpc8xxx/law.c
arch/powerpc/cpu/mpc8xxx/law.c
+2
-2
board/freescale/b4860qds/b4860qds.c
board/freescale/b4860qds/b4860qds.c
+0
-5
board/freescale/common/vid.c
board/freescale/common/vid.c
+17
-2
board/freescale/common/vid.h
board/freescale/common/vid.h
+4
-0
board/freescale/corenet_ds/corenet_ds.c
board/freescale/corenet_ds/corenet_ds.c
+0
-6
board/freescale/p2041rdb/p2041rdb.c
board/freescale/p2041rdb/p2041rdb.c
+0
-3
board/freescale/t102xqds/t102xqds.c
board/freescale/t102xqds/t102xqds.c
+0
-5
board/freescale/t102xrdb/t102xrdb.c
board/freescale/t102xrdb/t102xrdb.c
+0
-5
board/freescale/t1040qds/t1040qds.c
board/freescale/t1040qds/t1040qds.c
+0
-5
board/freescale/t104xrdb/t104xrdb.c
board/freescale/t104xrdb/t104xrdb.c
+0
-6
board/freescale/t208xqds/t208xqds.c
board/freescale/t208xqds/t208xqds.c
+0
-6
board/freescale/t208xrdb/t208xrdb.c
board/freescale/t208xrdb/t208xrdb.c
+0
-6
board/freescale/t4qds/t4240emu.c
board/freescale/t4qds/t4240emu.c
+0
-6
board/freescale/t4qds/t4240qds.c
board/freescale/t4qds/t4240qds.c
+0
-6
board/freescale/t4rdb/t4240rdb.c
board/freescale/t4rdb/t4240rdb.c
+7
-5
include/configs/T4240RDB.h
include/configs/T4240RDB.h
+10
-0
未找到文件。
arch/powerpc/cpu/mpc83xx/law.c
浏览文件 @
d8247774
...
...
@@ -19,7 +19,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
if
(
start
==
0
)
start_align
=
1ull
<<
(
LAW_SIZE_2G
+
1
);
else
start_align
=
1ull
<<
(
__ffs64
(
start
)
-
1
);
start_align
=
1ull
<<
(
__ffs64
(
start
));
law_sz
=
min
(
start_align
,
sz
);
law_sz_enc
=
__ilog2_u64
(
law_sz
)
-
1
;
...
...
@@ -39,7 +39,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
if
(
sz
)
{
start
+=
law_sz
;
start_align
=
1ull
<<
(
__ffs64
(
start
)
-
1
);
start_align
=
1ull
<<
(
__ffs64
(
start
));
law_sz
=
min
(
start_align
,
sz
);
law_sz_enc
=
__ilog2_u64
(
law_sz
)
-
1
;
ecm
=
&
immap
->
sysconf
.
ddrlaw
[
1
];
...
...
arch/powerpc/cpu/mpc85xx/cpu_init.c
浏览文件 @
d8247774
...
...
@@ -23,6 +23,10 @@
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_srio.h>
#ifdef CONFIG_FSL_CORENET
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#endif
#include <fsl_usb.h>
#include <hwconfig.h>
#include <linux/compiler.h>
...
...
@@ -788,6 +792,13 @@ int cpu_init_r(void)
spin_table_compat
=
1
;
#endif
#ifdef CONFIG_FSL_CORENET
set_liodns
();
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals
();
#endif
#endif
l2cache_init
();
#if defined(CONFIG_RAMBOOT_PBL)
disable_cpc_sram
();
...
...
arch/powerpc/cpu/mpc8xxx/law.c
浏览文件 @
d8247774
...
...
@@ -188,7 +188,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
if
(
start
==
0
)
start_align
=
1ull
<<
(
LAW_SIZE_32G
+
1
);
else
start_align
=
1ull
<<
(
__ffs64
(
start
)
-
1
);
start_align
=
1ull
<<
(
__ffs64
(
start
));
law_sz
=
min
(
start_align
,
sz
);
law_sz_enc
=
__ilog2_u64
(
law_sz
)
-
1
;
...
...
@@ -203,7 +203,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
if
(
sz
)
{
start
+=
law_sz
;
start_align
=
1ull
<<
(
__ffs64
(
start
)
-
1
);
start_align
=
1ull
<<
(
__ffs64
(
start
));
law_sz
=
min
(
start_align
,
sz
);
law_sz_enc
=
__ilog2_u64
(
law_sz
)
-
1
;
...
...
board/freescale/b4860qds/b4860qds.c
浏览文件 @
d8247774
...
...
@@ -16,7 +16,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <hwconfig.h>
...
...
@@ -1023,10 +1022,6 @@ int board_early_init_r(void)
MAS3_SX
|
MAS3_SW
|
MAS3_SR
,
MAS2_I
|
MAS2_G
,
0
,
flash_esel
,
BOOKE_PAGESZ_256M
,
1
);
set_liodns
();
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals
();
#endif
/*
* Adjust core voltage according to voltage ID
* This function changes I2C mux to channel 2.
...
...
board/freescale/common/vid.c
浏览文件 @
d8247774
...
...
@@ -42,7 +42,7 @@ int __weak board_vdd_drop_compensation(void)
* The IR chip can show up under the following addresses:
* 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA)
* 0x09 (Verified on T1040RDB-PA)
* 0x38 (Verified on T2080QDS, T2081QDS)
* 0x38 (Verified on T2080QDS, T2081QDS
, T4240RDB
)
*/
static
int
find_ir_chip_on_i2c
(
void
)
{
...
...
@@ -292,7 +292,7 @@ int adjust_vdd(ulong vdd_override)
(
void
__iomem
*
)(
CONFIG_SYS_MPC85xx_GUTS_ADDR
);
#endif
u32
fusesr
;
u8
vid
;
u8
vid
,
buf
;
int
vdd_target
,
vdd_current
,
vdd_last
;
int
ret
,
i2caddress
;
unsigned
long
vdd_string_override
;
...
...
@@ -346,6 +346,21 @@ int adjust_vdd(ulong vdd_override)
debug
(
"VID: IR Chip found on I2C address 0x%02x
\n
"
,
i2caddress
);
}
/* check IR chip work on Intel mode*/
ret
=
i2c_read
(
i2caddress
,
IR36021_INTEL_MODE_OOFSET
,
1
,
(
void
*
)
&
buf
,
1
);
if
(
ret
)
{
printf
(
"VID: failed to read IR chip mode.
\n
"
);
ret
=
-
1
;
goto
exit
;
}
if
((
buf
&
IR36021_MODE_MASK
)
!=
IR36021_INTEL_MODE
)
{
printf
(
"VID: IR Chip is not used in Intel mode.
\n
"
);
ret
=
-
1
;
goto
exit
;
}
/* get the voltage ID from fuse status register */
fusesr
=
in_be32
(
&
gur
->
dcfg_fusesr
);
/*
...
...
board/freescale/common/vid.h
浏览文件 @
d8247774
...
...
@@ -11,6 +11,10 @@
#define IR36021_LOOP1_VOUT_OFFSET 0x9A
#define IR36021_MFR_ID_OFFSET 0x92
#define IR36021_MFR_ID 0x43
#define IR36021_INTEL_MODE_OOFSET 0x14
#define IR36021_MODE_MASK 0x20
#define IR36021_INTEL_MODE 0x00
#define IR36021_AMD_MODE 0x20
/* step the IR regulator in 5mV increments */
#define IR_VDD_STEP_DOWN 5
...
...
board/freescale/corenet_ds/corenet_ds.c
浏览文件 @
d8247774
...
...
@@ -14,7 +14,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
...
...
@@ -125,11 +124,6 @@ int board_early_init_r(void)
MAS3_SX
|
MAS3_SW
|
MAS3_SR
,
MAS2_I
|
MAS2_G
,
/* perms, wimge */
0
,
flash_esel
,
BOOKE_PAGESZ_256M
,
1
);
/* ts, esel, tsize, iprot */
set_liodns
();
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals
();
#endif
return
0
;
}
...
...
board/freescale/p2041rdb/p2041rdb.c
浏览文件 @
d8247774
...
...
@@ -14,7 +14,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
...
...
@@ -140,8 +139,6 @@ int board_early_init_r(void)
MAS3_SX
|
MAS3_SW
|
MAS3_SR
,
MAS2_I
|
MAS2_G
,
0
,
flash_esel
,
BOOKE_PAGESZ_256M
,
1
);
set_liodns
();
setup_portals
();
board_config_lanes_mux
();
return
0
;
...
...
board/freescale/t102xqds/t102xqds.c
浏览文件 @
d8247774
...
...
@@ -15,7 +15,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <hwconfig.h>
...
...
@@ -279,10 +278,6 @@ int board_early_init_r(void)
set_tlb
(
1
,
flashbase
,
CONFIG_SYS_FLASH_BASE_PHYS
,
MAS3_SX
|
MAS3_SW
|
MAS3_SR
,
MAS2_I
|
MAS2_G
,
0
,
flash_esel
,
BOOKE_PAGESZ_256M
,
1
);
#endif
set_liodns
();
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals
();
#endif
select_i2c_ch_pca9547
(
I2C_MUX_CH_DEFAULT
);
board_mux_lane_to_slot
();
...
...
board/freescale/t102xrdb/t102xrdb.c
浏览文件 @
d8247774
...
...
@@ -14,7 +14,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "t102xrdb.h"
...
...
@@ -151,10 +150,6 @@ int board_early_init_r(void)
0
,
flash_esel
,
BOOKE_PAGESZ_256M
,
1
);
#endif
set_liodns
();
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals
();
#endif
#ifdef CONFIG_T1024RDB
board_mux_lane
();
#endif
...
...
board/freescale/t1040qds/t1040qds.c
浏览文件 @
d8247774
...
...
@@ -15,7 +15,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <hwconfig.h>
...
...
@@ -152,10 +151,6 @@ int board_early_init_r(void)
set_tlb
(
1
,
flashbase
,
CONFIG_SYS_FLASH_BASE_PHYS
,
MAS3_SX
|
MAS3_SW
|
MAS3_SR
,
MAS2_I
|
MAS2_G
,
0
,
flash_esel
,
BOOKE_PAGESZ_256M
,
1
);
#endif
set_liodns
();
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals
();
#endif
select_i2c_ch_pca9547
(
I2C_MUX_CH_DEFAULT
);
...
...
board/freescale/t104xrdb/t104xrdb.c
浏览文件 @
d8247774
...
...
@@ -16,7 +16,6 @@
#include <asm/fsl_fdt.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "../common/sleep.h"
...
...
@@ -84,11 +83,6 @@ int board_early_init_r(void)
MAS3_SX
|
MAS3_SW
|
MAS3_SR
,
MAS2_I
|
MAS2_G
,
0
,
flash_esel
,
BOOKE_PAGESZ_256M
,
1
);
#endif
set_liodns
();
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals
();
#endif
return
0
;
}
...
...
board/freescale/t208xqds/t208xqds.c
浏览文件 @
d8247774
...
...
@@ -14,7 +14,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
...
...
@@ -356,11 +355,6 @@ int board_early_init_r(void)
MAS3_SX
|
MAS3_SW
|
MAS3_SR
,
MAS2_I
|
MAS2_G
,
0
,
flash_esel
,
BOOKE_PAGESZ_256M
,
1
);
set_liodns
();
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals
();
#endif
/* Disable remote I2C connection to qixis fpga */
QIXIS_WRITE
(
brdcfg
[
5
],
QIXIS_READ
(
brdcfg
[
5
])
&
~
BRDCFG5_IRE
);
...
...
board/freescale/t208xrdb/t208xrdb.c
浏览文件 @
d8247774
...
...
@@ -14,7 +14,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "t208xrdb.h"
...
...
@@ -81,11 +80,6 @@ int board_early_init_r(void)
MAS3_SX
|
MAS3_SW
|
MAS3_SR
,
MAS2_I
|
MAS2_G
,
0
,
flash_esel
,
BOOKE_PAGESZ_256M
,
1
);
set_liodns
();
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals
();
#endif
/*
* Adjust core voltage according to voltage ID
* This function changes I2C mux to channel 2.
...
...
board/freescale/t4qds/t4240emu.c
浏览文件 @
d8247774
...
...
@@ -15,7 +15,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
DECLARE_GLOBAL_DATA_PTR
;
...
...
@@ -56,11 +55,6 @@ int board_early_init_r(void)
MAS3_SW
|
MAS3_SR
,
MAS2_I
|
MAS2_G
,
0
,
flash_esel
,
BOOKE_PAGESZ_256M
,
1
);
set_liodns
();
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals
();
#endif
return
0
;
}
...
...
board/freescale/t4qds/t4240qds.c
浏览文件 @
d8247774
...
...
@@ -15,7 +15,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
...
...
@@ -552,11 +551,6 @@ int board_early_init_r(void)
MAS3_SX
|
MAS3_SW
|
MAS3_SR
,
MAS2_I
|
MAS2_G
,
0
,
flash_esel
,
BOOKE_PAGESZ_256M
,
1
);
set_liodns
();
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals
();
#endif
/* Disable remote I2C connection to qixis fpga */
QIXIS_WRITE
(
brdcfg
[
5
],
QIXIS_READ
(
brdcfg
[
5
])
&
~
BRDCFG5_IRE
);
...
...
board/freescale/t4rdb/t4240rdb.c
浏览文件 @
d8247774
...
...
@@ -15,12 +15,12 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "t4rdb.h"
#include "cpld.h"
#include "../common/vid.h"
DECLARE_GLOBAL_DATA_PTR
;
...
...
@@ -75,10 +75,12 @@ int board_early_init_r(void)
MAS3_SX
|
MAS3_SW
|
MAS3_SR
,
MAS2_I
|
MAS2_G
,
0
,
flash_esel
,
BOOKE_PAGESZ_256M
,
1
);
set_liodns
();
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals
();
#endif
/*
* Adjust core voltage according to voltage ID
* This function changes I2C mux to channel 2.
*/
if
(
adjust_vdd
(
0
))
printf
(
"Warning: Adjusting core voltage failed.
\n
"
);
return
0
;
}
...
...
include/configs/T4240RDB.h
浏览文件 @
d8247774
...
...
@@ -606,6 +606,16 @@ unsigned long get_board_ddr_clk(void);
#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
#define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
#ifndef CONFIG_SPL_BUILD
#define CONFIG_VID
#endif
#define CONFIG_VOL_MONITOR_IR36021_SET
#define CONFIG_VOL_MONITOR_IR36021_READ
/* The lowest and highest voltage allowed for T4240RDB */
#define VDD_MV_MIN 819
#define VDD_MV_MAX 1212
/*
* eSPI - Enhanced SPI
*/
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