提交 d7787c6e 编写于 作者: S stroese

Fixed bug in ext. serial clock setup on PPC405 (since PPC440 port).

上级 ad10dd9a
...@@ -2,6 +2,9 @@ ...@@ -2,6 +2,9 @@
Changes since U-Boot 0.2.1: Changes since U-Boot 0.2.1:
====================================================================== ======================================================================
* Patch by Stefan Roese, 17 Feb 2003:
Fixed bug in ext. serial clock setup on PPC405 (since PPC440 port).
* Patch by Stefan Roese, 13 Feb 2003: * Patch by Stefan Roese, 13 Feb 2003:
Add "pcidelay" environment variable (in ms, enabled via Add "pcidelay" environment variable (in ms, enabled via
CONFIG_PCI_BOOTDELAY). CONFIG_PCI_BOOTDELAY).
......
...@@ -279,7 +279,7 @@ int serial_tstc () ...@@ -279,7 +279,7 @@ int serial_tstc ()
#define UART0_BASE 0xef600300 #define UART0_BASE 0xef600300
#define UART1_BASE 0xef600400 #define UART1_BASE 0xef600400
#define CR0_MASK 0x00001fff #define CR0_MASK 0x00001fff
#define CR0_EXTCLK_ENA 0x00000c00 #define CR0_EXTCLK_ENA 0x000000c0
#define CR0_UDIV_POS 1 #define CR0_UDIV_POS 1
#endif #endif
......
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