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提交 d49a5267 编写于 作者: K Kever Yang
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rockchip: clk: add px30 clock driver 

The px30 contains 2 separate clock controllers, pmucru and cru.
Add drivers for them.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
上级 8fb32685
展开全部 隐藏空白更改
内联 并排
Showing with 2452 addition and 0 deletion
arch/arm/include/asm/arch-rockchip/cru_px30.h 0 → 100644
浏览文件 @ d49a5267
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
*/
#ifndef _ASM_ARCH_CRU_PX30_H
#define _ASM_ARCH_CRU_PX30_H
#include <common.h>
#define MHz 1000000
#define KHz 1000
#define OSC_HZ (24 * MHz)
#define APLL_HZ (600 * MHz)
#define GPLL_HZ (1200 * MHz)
#define NPLL_HZ (1188 * MHz)
#define ACLK_BUS_HZ (200 * MHz)
#define HCLK_BUS_HZ (150 * MHz)
#define PCLK_BUS_HZ (100 * MHz)
#define ACLK_PERI_HZ (200 * MHz)
#define HCLK_PERI_HZ (150 * MHz)
#define PCLK_PMU_HZ (100 * MHz)
/* PX30 pll id */
enum px30_pll_id {
APLL,
DPLL,
CPLL,
NPLL,
GPLL,
PLL_COUNT,
};
struct px30_clk_priv {
struct px30_cru *cru;
ulong gpll_hz;
};
struct px30_pmuclk_priv {
struct px30_pmucru *pmucru;
ulong gpll_hz;
};
struct px30_pll {
unsigned int con0;
unsigned int con1;
unsigned int con2;
unsigned int con3;
unsigned int con4;
unsigned int reserved0[3];
};
struct px30_cru {
struct px30_pll pll[4];
unsigned int reserved1[8];
unsigned int mode;
unsigned int misc;
unsigned int reserved2[2];
unsigned int glb_cnt_th;
unsigned int glb_rst_st;
unsigned int glb_srst_fst;
unsigned int glb_srst_snd;
unsigned int glb_rst_con;
unsigned int reserved3[7];
unsigned int hwffc_con0;
unsigned int reserved4;
unsigned int hwffc_th;
unsigned int hwffc_intst;
unsigned int apll_con0_s;
unsigned int apll_con1_s;
unsigned int clksel_con0_s;
unsigned int reserved5;
unsigned int clksel_con[60];
unsigned int reserved6[4];
unsigned int clkgate_con[18];
unsigned int reserved7[(0x280 - 0x244) / 4 - 1];
unsigned int ssgtbl[32];
unsigned int softrst_con[12];
unsigned int reserved8[(0x380 - 0x32c) / 4 - 1];
unsigned int sdmmc_con[2];
unsigned int sdio_con[2];
unsigned int emmc_con[2];
unsigned int reserved9[(0x400 - 0x394) / 4 - 1];
unsigned int autocs_con[8];
};
check_member(px30_cru, autocs_con[7], 0x41c);
struct px30_pmucru {
struct px30_pll pll;
unsigned int pmu_mode;
unsigned int reserved1[7];
unsigned int pmu_clksel_con[6];
unsigned int reserved2[10];
unsigned int pmu_clkgate_con[2];
unsigned int reserved3[14];
unsigned int pmu_autocs_con[2];
};
check_member(px30_pmucru, pmu_autocs_con[1], 0xc4);
struct pll_rate_table {
unsigned long rate;
unsigned int fbdiv;
unsigned int postdiv1;
unsigned int refdiv;
unsigned int postdiv2;
unsigned int dsmpd;
unsigned int frac;
};
struct cpu_rate_table {
unsigned long rate;
unsigned int aclk_div;
unsigned int pclk_div;
};
enum {
/* PLLCON0*/
PLL_BP_SHIFT = 15,
PLL_POSTDIV1_SHIFT = 12,
PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
PLL_FBDIV_SHIFT = 0,
PLL_FBDIV_MASK = 0xfff,
/* PLLCON1 */
PLL_PDSEL_SHIFT = 15,
PLL_PD1_SHIFT = 14,
PLL_PD_SHIFT = 13,
PLL_PD_MASK = 1 << PLL_PD_SHIFT,
PLL_DSMPD_SHIFT = 12,
PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
PLL_LOCK_STATUS_SHIFT = 10,
PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
PLL_POSTDIV2_SHIFT = 6,
PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
PLL_REFDIV_SHIFT = 0,
PLL_REFDIV_MASK = 0x3f,
/* PLLCON2 */
PLL_FOUT4PHASEPD_SHIFT = 27,
PLL_FOUTVCOPD_SHIFT = 26,
PLL_FOUTPOSTDIVPD_SHIFT = 25,
PLL_DACPD_SHIFT = 24,
PLL_FRAC_DIV = 0xffffff,
/* CRU_MODE */
PLLMUX_FROM_XIN24M = 0,
PLLMUX_FROM_PLL,
PLLMUX_FROM_RTC32K,
USBPHY480M_MODE_SHIFT = 8,
USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT,
NPLL_MODE_SHIFT = 6,
NPLL_MODE_MASK = 3 << NPLL_MODE_SHIFT,
DPLL_MODE_SHIFT = 4,
DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT,
CPLL_MODE_SHIFT = 2,
CPLL_MODE_MASK = 3 << CPLL_MODE_SHIFT,
APLL_MODE_SHIFT = 0,
APLL_MODE_MASK = 3 << APLL_MODE_SHIFT,
/* CRU_CLK_SEL0_CON */
CORE_ACLK_DIV_SHIFT = 12,
CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT,
CORE_DBG_DIV_SHIFT = 8,
CORE_DBG_DIV_MASK = 0x03 << CORE_DBG_DIV_SHIFT,
CORE_CLK_PLL_SEL_SHIFT = 7,
CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT,
CORE_CLK_PLL_SEL_APLL = 0,
CORE_CLK_PLL_SEL_GPLL,
CORE_DIV_CON_SHIFT = 0,
CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT,
/* CRU_CLK_SEL3_CON */
ACLK_VO_PLL_SHIFT = 6,
ACLK_VO_PLL_MASK = 0x3 << ACLK_VO_PLL_SHIFT,
ACLK_VO_SEL_GPLL = 0,
ACLK_VO_SEL_CPLL,
ACLK_VO_SEL_NPLL,
ACLK_VO_DIV_SHIFT = 0,
ACLK_VO_DIV_MASK = 0x1f << ACLK_VO_DIV_SHIFT,
/* CRU_CLK_SEL5_CON */
DCLK_VOPB_SEL_SHIFT = 14,
DCLK_VOPB_SEL_MASK = 0x3 << DCLK_VOPB_SEL_SHIFT,
DCLK_VOPB_SEL_DIVOUT = 0,
DCLK_VOPB_SEL_FRACOUT,
DCLK_VOPB_SEL_24M,
DCLK_VOPB_PLL_SEL_SHIFT = 11,
DCLK_VOPB_PLL_SEL_MASK = 0x1 << DCLK_VOPB_PLL_SEL_SHIFT,
DCLK_VOPB_PLL_SEL_CPLL = 0,
DCLK_VOPB_PLL_SEL_NPLL,
DCLK_VOPB_DIV_SHIFT = 0,
DCLK_VOPB_DIV_MASK = 0xff,
/* CRU_CLK_SEL8_CON */
DCLK_VOPL_SEL_SHIFT = 14,
DCLK_VOPL_SEL_MASK = 0x3 << DCLK_VOPL_SEL_SHIFT,
DCLK_VOPL_SEL_DIVOUT = 0,
DCLK_VOPL_SEL_FRACOUT,
DCLK_VOPL_SEL_24M,
DCLK_VOPL_PLL_SEL_SHIFT = 11,
DCLK_VOPL_PLL_SEL_MASK = 0x1 << DCLK_VOPL_PLL_SEL_SHIFT,
DCLK_VOPL_PLL_SEL_NPLL = 0,
DCLK_VOPL_PLL_SEL_CPLL,
DCLK_VOPL_DIV_SHIFT = 0,
DCLK_VOPL_DIV_MASK = 0xff,
/* CRU_CLK_SEL14_CON */
PERI_PLL_SEL_SHIFT = 15,
PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT,
PERI_PLL_GPLL = 0,
PERI_PLL_CPLL,
PERI_HCLK_DIV_SHIFT = 8,
PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT,
PERI_ACLK_DIV_SHIFT = 0,
PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
/* CRU_CLKSEL15_CON */
NANDC_CLK_SEL_SHIFT = 15,
NANDC_CLK_SEL_MASK = 0x1 << NANDC_CLK_SEL_SHIFT,
NANDC_CLK_SEL_NANDC = 0,
NANDC_CLK_SEL_NANDC_DIV50,
NANDC_DIV50_SHIFT = 8,
NANDC_DIV50_MASK = 0x1f << NANDC_DIV50_SHIFT,
NANDC_PLL_SHIFT = 6,
NANDC_PLL_MASK = 0x3 << NANDC_PLL_SHIFT,
NANDC_SEL_GPLL = 0,
NANDC_SEL_CPLL,
NANDC_SEL_NPLL,
NANDC_DIV_SHIFT = 0,
NANDC_DIV_MASK = 0x1f << NANDC_DIV_SHIFT,
/* CRU_CLKSEL20_CON */
EMMC_PLL_SHIFT = 14,
EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
EMMC_SEL_GPLL = 0,
EMMC_SEL_CPLL,
EMMC_SEL_NPLL,
EMMC_SEL_24M,
EMMC_DIV_SHIFT = 0,
EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT,
/* CRU_CLKSEL21_CON */
EMMC_CLK_SEL_SHIFT = 15,
EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT,
EMMC_CLK_SEL_EMMC = 0,
EMMC_CLK_SEL_EMMC_DIV50,
EMMC_DIV50_SHIFT = 0,
EMMC_DIV50_MASK = 0xff << EMMC_DIV_SHIFT,
/* CRU_CLKSEL22_CON */
GMAC_PLL_SEL_SHIFT = 14,
GMAC_PLL_SEL_MASK = 3 << GMAC_PLL_SEL_SHIFT,
GMAC_PLL_SEL_GPLL = 0,
GMAC_PLL_SEL_CPLL,
GMAC_PLL_SEL_NPLL,
CLK_GMAC_DIV_SHIFT = 8,
CLK_GMAC_DIV_MASK = 0x1f << CLK_GMAC_DIV_SHIFT,
SFC_PLL_SEL_SHIFT = 7,
SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT,
SFC_DIV_CON_SHIFT = 0,
SFC_DIV_CON_MASK = 0x7f,
/* CRU_CLK_SEL23_CON */
BUS_PLL_SEL_SHIFT = 15,
BUS_PLL_SEL_MASK = 1 << BUS_PLL_SEL_SHIFT,
BUS_PLL_SEL_GPLL = 0,
BUS_PLL_SEL_CPLL,
BUS_ACLK_DIV_SHIFT = 8,
BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
RMII_CLK_SEL_SHIFT = 7,
RMII_CLK_SEL_MASK = 1 << RMII_CLK_SEL_SHIFT,
RMII_CLK_SEL_10M = 0,
RMII_CLK_SEL_100M,
RMII_EXTCLK_SEL_SHIFT = 6,
RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT,
RMII_EXTCLK_SEL_INT = 0,
RMII_EXTCLK_SEL_EXT,
PCLK_GMAC_DIV_SHIFT = 0,
PCLK_GMAC_DIV_MASK = 0x0f << PCLK_GMAC_DIV_SHIFT,
/* CRU_CLK_SEL24_CON */
BUS_PCLK_DIV_SHIFT = 8,
BUS_PCLK_DIV_MASK = 3 << BUS_PCLK_DIV_SHIFT,
BUS_HCLK_DIV_SHIFT = 0,
BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT,
/* CRU_CLK_SEL25_CON */
CRYPTO_APK_SEL_SHIFT = 14,
CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT,
CRYPTO_PLL_SEL_GPLL = 0,
CRYPTO_PLL_SEL_CPLL,
CRYPTO_PLL_SEL_NPLL = 0,
CRYPTO_APK_DIV_SHIFT = 8,
CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT,
CRYPTO_PLL_SEL_SHIFT = 6,
CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT,
CRYPTO_DIV_SHIFT = 0,
CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT,
/* CRU_CLK_SEL30_CON */
CLK_I2S1_DIV_CON_MASK = 0x7f,
CLK_I2S1_PLL_SEL_MASK = 0X1 << 8,
CLK_I2S1_PLL_SEL_GPLL = 0X0 << 8,
CLK_I2S1_PLL_SEL_NPLL = 0X1 << 8,
CLK_I2S1_SEL_MASK = 0x3 << 10,
CLK_I2S1_SEL_I2S1 = 0x0 << 10,
CLK_I2S1_SEL_FRAC = 0x1 << 10,
CLK_I2S1_SEL_MCLK_IN = 0x2 << 10,
CLK_I2S1_SEL_OSC = 0x3 << 10,
CLK_I2S1_OUT_SEL_MASK = 0x1 << 15,
CLK_I2S1_OUT_SEL_I2S1 = 0x0 << 15,
CLK_I2S1_OUT_SEL_OSC = 0x1 << 15,
/* CRU_CLK_SEL31_CON */
CLK_I2S1_FRAC_NUMERATOR_SHIFT = 16,
CLK_I2S1_FRAC_NUMERATOR_MASK = 0xffff << 16,
CLK_I2S1_FRAC_DENOMINATOR_SHIFT = 0,
CLK_I2S1_FRAC_DENOMINATOR_MASK = 0xffff,
/* CRU_CLK_SEL34_CON */
UART1_PLL_SEL_SHIFT = 14,
UART1_PLL_SEL_MASK = 3 << UART1_PLL_SEL_SHIFT,
UART1_PLL_SEL_GPLL = 0,
UART1_PLL_SEL_24M,
UART1_PLL_SEL_480M,
UART1_PLL_SEL_NPLL,
UART1_DIV_CON_SHIFT = 0,
UART1_DIV_CON_MASK = 0x1f << UART1_DIV_CON_SHIFT,
/* CRU_CLK_SEL35_CON */
UART1_CLK_SEL_SHIFT = 14,
UART1_CLK_SEL_MASK = 3 << UART1_PLL_SEL_SHIFT,
UART1_CLK_SEL_UART1 = 0,
UART1_CLK_SEL_UART1_NP5,
UART1_CLK_SEL_UART1_FRAC,
UART1_DIVNP5_SHIFT = 0,
UART1_DIVNP5_MASK = 0x1f << UART1_DIVNP5_SHIFT,
/* CRU_CLK_SEL37_CON */
UART2_PLL_SEL_SHIFT = 14,
UART2_PLL_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT,
UART2_PLL_SEL_GPLL = 0,
UART2_PLL_SEL_24M,
UART2_PLL_SEL_480M,
UART2_PLL_SEL_NPLL,
UART2_DIV_CON_SHIFT = 0,
UART2_DIV_CON_MASK = 0x1f << UART2_DIV_CON_SHIFT,
/* CRU_CLK_SEL38_CON */
UART2_CLK_SEL_SHIFT = 14,
UART2_CLK_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT,
UART2_CLK_SEL_UART2 = 0,
UART2_CLK_SEL_UART2_NP5,
UART2_CLK_SEL_UART2_FRAC,
UART2_DIVNP5_SHIFT = 0,
UART2_DIVNP5_MASK = 0x1f << UART2_DIVNP5_SHIFT,
/* CRU_CLK_SEL46_CON */
UART5_PLL_SEL_SHIFT = 14,
UART5_PLL_SEL_MASK = 3 << UART5_PLL_SEL_SHIFT,
UART5_PLL_SEL_GPLL = 0,
UART5_PLL_SEL_24M,
UART5_PLL_SEL_480M,
UART5_PLL_SEL_NPLL,
UART5_DIV_CON_SHIFT = 0,
UART5_DIV_CON_MASK = 0x1f << UART5_DIV_CON_SHIFT,
/* CRU_CLK_SEL47_CON */
UART5_CLK_SEL_SHIFT = 14,
UART5_CLK_SEL_MASK = 3 << UART5_PLL_SEL_SHIFT,
UART5_CLK_SEL_UART5 = 0,
UART5_CLK_SEL_UART5_NP5,
UART5_CLK_SEL_UART5_FRAC,
UART5_DIVNP5_SHIFT = 0,
UART5_DIVNP5_MASK = 0x1f << UART5_DIVNP5_SHIFT,
/* CRU_CLK_SEL49_CON */
CLK_I2C_PLL_SEL_GPLL = 0,
CLK_I2C_PLL_SEL_24M,
CLK_I2C_DIV_CON_MASK = 0x7f,
CLK_I2C_PLL_SEL_MASK = 1,
CLK_I2C1_PLL_SEL_SHIFT = 15,
CLK_I2C1_DIV_CON_SHIFT = 8,
CLK_I2C0_PLL_SEL_SHIFT = 7,
CLK_I2C0_DIV_CON_SHIFT = 0,
/* CRU_CLK_SEL50_CON */
CLK_I2C3_PLL_SEL_SHIFT = 15,
CLK_I2C3_DIV_CON_SHIFT = 8,
CLK_I2C2_PLL_SEL_SHIFT = 7,
CLK_I2C2_DIV_CON_SHIFT = 0,
/* CRU_CLK_SEL52_CON */
CLK_PWM_PLL_SEL_GPLL = 0,
CLK_PWM_PLL_SEL_24M,
CLK_PWM_DIV_CON_MASK = 0x7f,
CLK_PWM_PLL_SEL_MASK = 1,
CLK_PWM1_PLL_SEL_SHIFT = 15,
CLK_PWM1_DIV_CON_SHIFT = 8,
CLK_PWM0_PLL_SEL_SHIFT = 7,
CLK_PWM0_DIV_CON_SHIFT = 0,
/* CRU_CLK_SEL53_CON */
CLK_SPI_PLL_SEL_GPLL = 0,
CLK_SPI_PLL_SEL_24M,
CLK_SPI_DIV_CON_MASK = 0x7f,
CLK_SPI_PLL_SEL_MASK = 1,
CLK_SPI1_PLL_SEL_SHIFT = 15,
CLK_SPI1_DIV_CON_SHIFT = 8,
CLK_SPI0_PLL_SEL_SHIFT = 7,
CLK_SPI0_DIV_CON_SHIFT = 0,
/* CRU_CLK_SEL55_CON */
CLK_SARADC_DIV_CON_SHIFT = 0,
CLK_SARADC_DIV_CON_MASK = 0x7ff,
/* CRU_CLK_GATE10_CON */
CLK_I2S1_OUT_MCLK_PAD_MASK = 0x1 << 9,
CLK_I2S1_OUT_MCLK_PAD_ENABLE = 0x1 << 9,
CLK_I2S1_OUT_MCLK_PAD_DISABLE = 0x0 << 9,
/* CRU_PMU_MODE */
GPLL_MODE_SHIFT = 0,
GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT,
/* CRU_PMU_CLK_SEL0_CON */
CLK_PMU_PCLK_DIV_SHIFT = 0,
CLK_PMU_PCLK_DIV_MASK = 0x1f << CLK_PMU_PCLK_DIV_SHIFT,
};
#endif
drivers/clk/rockchip/Makefile
浏览文件 @ d49a5267
......@@ -3,6 +3,7 @@
# Copyright (c) 2017 Rockchip Electronics Co., Ltd
#
obj-$(CONFIG_ROCKCHIP_PX30) += clk_px30.o
obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
obj-$(CONFIG_ROCKCHIP_RK3128) += clk_rk3128.o
obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
......
drivers/clk/rockchip/clk_px30.c 0 → 100644
浏览文件 @ d49a5267
此差异已折叠。
include/dt-bindings/clock/px30-cru.h 0 → 100644
浏览文件 @ d49a5267
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2017 Rockchip Electronics Co. Ltd.
* Author: Elaine <zhangqing@rock-chips.com>
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
/* core clocks */
#define PLL_APLL 1
#define PLL_DPLL 2
#define PLL_CPLL 3
#define PLL_NPLL 4
#define APLL_BOOST_H 5
#define APLL_BOOST_L 6
#define ARMCLK 7
/* sclk gates (special clocks) */
#define USB480M 14
#define SCLK_PDM 15
#define SCLK_I2S0_TX 16
#define SCLK_I2S0_TX_OUT 17
#define SCLK_I2S0_RX 18
#define SCLK_I2S0_RX_OUT 19
#define SCLK_I2S1 20
#define SCLK_I2S1_OUT 21
#define SCLK_I2S2 22
#define SCLK_I2S2_OUT 23
#define SCLK_UART1 24
#define SCLK_UART2 25
#define SCLK_UART3 26
#define SCLK_UART4 27
#define SCLK_UART5 28
#define SCLK_I2C0 29
#define SCLK_I2C1 30
#define SCLK_I2C2 31
#define SCLK_I2C3 32
#define SCLK_I2C4 33
#define SCLK_PWM0 34
#define SCLK_PWM1 35
#define SCLK_SPI0 36
#define SCLK_SPI1 37
#define SCLK_TIMER0 38
#define SCLK_TIMER1 39
#define SCLK_TIMER2 40
#define SCLK_TIMER3 41
#define SCLK_TIMER4 42
#define SCLK_TIMER5 43
#define SCLK_TSADC 44
#define SCLK_SARADC 45
#define SCLK_OTP 46
#define SCLK_OTP_USR 47
#define SCLK_CRYPTO 48
#define SCLK_CRYPTO_APK 49
#define SCLK_DDRC 50
#define SCLK_ISP 51
#define SCLK_CIF_OUT 52
#define SCLK_RGA_CORE 53
#define SCLK_VOPB_PWM 54
#define SCLK_NANDC 55
#define SCLK_SDIO 56
#define SCLK_EMMC 57
#define SCLK_SFC 58
#define SCLK_SDMMC 59
#define SCLK_OTG_ADP 60
#define SCLK_GMAC_SRC 61
#define SCLK_GMAC 62
#define SCLK_GMAC_RX_TX 63
#define SCLK_MAC_REF 64
#define SCLK_MAC_REFOUT 65
#define SCLK_MAC_OUT 66
#define SCLK_SDMMC_DRV 67
#define SCLK_SDMMC_SAMPLE 68
#define SCLK_SDIO_DRV 69
#define SCLK_SDIO_SAMPLE 70
#define SCLK_EMMC_DRV 71
#define SCLK_EMMC_SAMPLE 72
#define SCLK_GPU 73
#define SCLK_PVTM 74
#define SCLK_CORE_VPU 75
#define SCLK_GMAC_RMII 76
#define SCLK_UART2_SRC 77
#define SCLK_NANDC_DIV 78
#define SCLK_NANDC_DIV50 79
#define SCLK_SDIO_DIV 80
#define SCLK_SDIO_DIV50 81
#define SCLK_EMMC_DIV 82
#define SCLK_EMMC_DIV50 83
/* dclk gates */
#define DCLK_VOPB 150
#define DCLK_VOPL 151
/* aclk gates */
#define ACLK_GPU 170
#define ACLK_BUS_PRE 171
#define ACLK_CRYPTO 172
#define ACLK_VI_PRE 173
#define ACLK_VO_PRE 174
#define ACLK_VPU 175
#define ACLK_PERI_PRE 176
#define ACLK_GMAC 178
#define ACLK_CIF 179
#define ACLK_ISP 180
#define ACLK_VOPB 181
#define ACLK_VOPL 182
#define ACLK_RGA 183
#define ACLK_GIC 184
#define ACLK_DCF 186
#define ACLK_DMAC 187
/* hclk gates */
#define HCLK_BUS_PRE 240
#define HCLK_CRYPTO 241
#define HCLK_VI_PRE 242
#define HCLK_VO_PRE 243
#define HCLK_VPU 244
#define HCLK_PERI_PRE 245
#define HCLK_MMC_NAND 246
#define HCLK_SDMMC 247
#define HCLK_USB 248
#define HCLK_CIF 249
#define HCLK_ISP 250
#define HCLK_VOPB 251
#define HCLK_VOPL 252
#define HCLK_RGA 253
#define HCLK_NANDC 254
#define HCLK_SDIO 255
#define HCLK_EMMC 256
#define HCLK_SFC 257
#define HCLK_OTG 258
#define HCLK_HOST 259
#define HCLK_HOST_ARB 260
#define HCLK_PDM 261
#define HCLK_I2S0 262
#define HCLK_I2S1 263
#define HCLK_I2S2 264
/* pclk gates */
#define PCLK_BUS_PRE 320
#define PCLK_DDR 321
#define PCLK_VO_PRE 322
#define PCLK_GMAC 323
#define PCLK_MIPI_DSI 324
#define PCLK_MIPIDSIPHY 325
#define PCLK_MIPICSIPHY 326
#define PCLK_USB_GRF 327
#define PCLK_DCF 328
#define PCLK_UART1 329
#define PCLK_UART2 330
#define PCLK_UART3 331
#define PCLK_UART4 332
#define PCLK_UART5 333
#define PCLK_I2C0 334
#define PCLK_I2C1 335
#define PCLK_I2C2 336
#define PCLK_I2C3 337
#define PCLK_I2C4 338
#define PCLK_PWM0 339
#define PCLK_PWM1 340
#define PCLK_SPI0 341
#define PCLK_SPI1 342
#define PCLK_SARADC 343
#define PCLK_TSADC 344
#define PCLK_TIMER 345
#define PCLK_OTP_NS 346
#define PCLK_WDT_NS 347
#define PCLK_GPIO1 348
#define PCLK_GPIO2 349
#define PCLK_GPIO3 350
#define PCLK_ISP 351
#define PCLK_CIF 352
#define PCLK_OTP_PHY 353
#define CLK_NR_CLKS (PCLK_OTP_PHY + 1)
/* pmu-clocks indices */
#define PLL_GPLL 1
#define SCLK_RTC32K_PMU 4
#define SCLK_WIFI_PMU 5
#define SCLK_UART0_PMU 6
#define SCLK_PVTM_PMU 7
#define PCLK_PMU_PRE 8
#define SCLK_REF24M_PMU 9
#define SCLK_USBPHY_REF 10
#define SCLK_MIPIDSIPHY_REF 11
#define XIN24M_DIV 12
#define PCLK_GPIO0_PMU 20
#define PCLK_UART0_PMU 21
#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1)
/* soft-reset indices */
#define SRST_CORE0_PO 0
#define SRST_CORE1_PO 1
#define SRST_CORE2_PO 2
#define SRST_CORE3_PO 3
#define SRST_CORE0 4
#define SRST_CORE1 5
#define SRST_CORE2 6
#define SRST_CORE3 7
#define SRST_CORE0_DBG 8
#define SRST_CORE1_DBG 9
#define SRST_CORE2_DBG 10
#define SRST_CORE3_DBG 11
#define SRST_TOPDBG 12
#define SRST_CORE_NOC 13
#define SRST_STRC_A 14
#define SRST_L2C 15
#define SRST_DAP 16
#define SRST_CORE_PVTM 17
#define SRST_GPU 18
#define SRST_GPU_NIU 19
#define SRST_UPCTL2 20
#define SRST_UPCTL2_A 21
#define SRST_UPCTL2_P 22
#define SRST_MSCH 23
#define SRST_MSCH_P 24
#define SRST_DDRMON_P 25
#define SRST_DDRSTDBY_P 26
#define SRST_DDRSTDBY 27
#define SRST_DDRGRF_p 28
#define SRST_AXI_SPLIT_A 29
#define SRST_AXI_CMD_A 30
#define SRST_AXI_CMD_P 31
#define SRST_DDRPHY 32
#define SRST_DDRPHYDIV 33
#define SRST_DDRPHY_P 34
#define SRST_VPU_A 36
#define SRST_VPU_NIU_A 37
#define SRST_VPU_H 38
#define SRST_VPU_NIU_H 39
#define SRST_VI_NIU_A 40
#define SRST_VI_NIU_H 41
#define SRST_ISP_H 42
#define SRST_ISP 43
#define SRST_CIF_A 44
#define SRST_CIF_H 45
#define SRST_CIF_PCLKIN 46
#define SRST_MIPICSIPHY_P 47
#define SRST_VO_NIU_A 48
#define SRST_VO_NIU_H 49
#define SRST_VO_NIU_P 50
#define SRST_VOPB_A 51
#define SRST_VOPB_H 52
#define SRST_VOPB 53
#define SRST_PWM_VOPB 54
#define SRST_VOPL_A 55
#define SRST_VOPL_H 56
#define SRST_VOPL 57
#define SRST_RGA_A 58
#define SRST_RGA_H 59
#define SRST_RGA 60
#define SRST_MIPIDSI_HOST_P 61
#define SRST_MIPIDSIPHY_P 62
#define SRST_VPU_CORE 63
#define SRST_PERI_NIU_A 64
#define SRST_USB_NIU_H 65
#define SRST_USB2OTG_H 66
#define SRST_USB2OTG 67
#define SRST_USB2OTG_ADP 68
#define SRST_USB2HOST_H 69
#define SRST_USB2HOST_ARB_H 70
#define SRST_USB2HOST_AUX_H 71
#define SRST_USB2HOST_EHCI 72
#define SRST_USB2HOST 73
#define SRST_USBPHYPOR 74
#define SRST_USBPHY_OTG_PORT 75
#define SRST_USBPHY_HOST_PORT 76
#define SRST_USBPHY_GRF 77
#define SRST_CPU_BOOST_P 78
#define SRST_CPU_BOOST 79
#define SRST_MMC_NAND_NIU_H 80
#define SRST_SDIO_H 81
#define SRST_EMMC_H 82
#define SRST_SFC_H 83
#define SRST_SFC 84
#define SRST_SDCARD_NIU_H 85
#define SRST_SDMMC_H 86
#define SRST_NANDC_H 89
#define SRST_NANDC 90
#define SRST_GMAC_NIU_A 92
#define SRST_GMAC_NIU_P 93
#define SRST_GMAC_A 94
#define SRST_PMU_NIU_P 96
#define SRST_PMU_SGRF_P 97
#define SRST_PMU_GRF_P 98
#define SRST_PMU 99
#define SRST_PMU_MEM_P 100
#define SRST_PMU_GPIO0_P 101
#define SRST_PMU_UART0_P 102
#define SRST_PMU_CRU_P 103
#define SRST_PMU_PVTM 104
#define SRST_PMU_UART 105
#define SRST_PMU_NIU_H 106
#define SRST_PMU_DDR_FAIL_SAVE 107
#define SRST_PMU_CORE_PERF_A 108
#define SRST_PMU_CORE_GRF_P 109
#define SRST_PMU_GPU_PERF_A 110
#define SRST_PMU_GPU_GRF_P 111
#define SRST_CRYPTO_NIU_A 112
#define SRST_CRYPTO_NIU_H 113
#define SRST_CRYPTO_A 114
#define SRST_CRYPTO_H 115
#define SRST_CRYPTO 116
#define SRST_CRYPTO_APK 117
#define SRST_BUS_NIU_H 120
#define SRST_USB_NIU_P 121
#define SRST_BUS_TOP_NIU_P 122
#define SRST_INTMEM_A 123
#define SRST_GIC_A 124
#define SRST_ROM_H 126
#define SRST_DCF_A 127
#define SRST_DCF_P 128
#define SRST_PDM_H 129
#define SRST_PDM 130
#define SRST_I2S0_H 131
#define SRST_I2S0_TX 132
#define SRST_I2S1_H 133
#define SRST_I2S1 134
#define SRST_I2S2_H 135
#define SRST_I2S2 136
#define SRST_UART1_P 137
#define SRST_UART1 138
#define SRST_UART2_P 139
#define SRST_UART2 140
#define SRST_UART3_P 141
#define SRST_UART3 142
#define SRST_UART4_P 143
#define SRST_UART4 144
#define SRST_UART5_P 145
#define SRST_UART5 146
#define SRST_I2C0_P 147
#define SRST_I2C0 148
#define SRST_I2C1_P 149
#define SRST_I2C1 150
#define SRST_I2C2_P 151
#define SRST_I2C2 152
#define SRST_I2C3_P 153
#define SRST_I2C3 154
#define SRST_PWM0_P 157
#define SRST_PWM0 158
#define SRST_PWM1_P 159
#define SRST_PWM1 160
#define SRST_SPI0_P 161
#define SRST_SPI0 162
#define SRST_SPI1_P 163
#define SRST_SPI1 164
#define SRST_SARADC_P 165
#define SRST_SARADC 166
#define SRST_TSADC_P 167
#define SRST_TSADC 168
#define SRST_TIMER_P 169
#define SRST_TIMER0 170
#define SRST_TIMER1 171
#define SRST_TIMER2 172
#define SRST_TIMER3 173
#define SRST_TIMER4 174
#define SRST_TIMER5 175
#define SRST_OTP_NS_P 176
#define SRST_OTP_NS_SBPI 177
#define SRST_OTP_NS_USR 178
#define SRST_OTP_PHY_P 179
#define SRST_OTP_PHY 180
#define SRST_WDT_NS_P 181
#define SRST_GPIO1_P 182
#define SRST_GPIO2_P 183
#define SRST_GPIO3_P 184
#define SRST_SGRF_P 185
#define SRST_GRF_P 186
#define SRST_I2S0_RX 191
#endif
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