cpu/86xx fixes.
Remove rev 1 fixes. Always set PICGCR_MODE. Enable machine check and provide board config option to set and handle SoC error interrupts. Include MSSSR0 in error message. Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT. Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: NJon Loeliger <jdl@freescale.com>
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