fpga: zynqpl: Flush dcache only for non-bitstream data
In case of aes decryption destination address range must be flushed before transferring decrypted data to destination. Signed-off-by: NT Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: NSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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