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c956662c
编写于
2月 10, 2015
作者:
T
Tom Rini
浏览文件
操作
浏览文件
下载
差异文件
Merge branch 'master' of
git://git.denx.de/u-boot-atmel
上级
0dac731d
657006a1
变更
41
隐藏空白更改
内联
并排
Showing
41 changed file
with
518 addition
and
428 deletion
+518
-428
README
README
+3
-0
arch/arm/Kconfig
arch/arm/Kconfig
+2
-0
arch/arm/cpu/arm926ejs/at91/Makefile
arch/arm/cpu/arm926ejs/at91/Makefile
+0
-1
arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c
arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c
+0
-189
arch/arm/cpu/armv7/at91/clock.c
arch/arm/cpu/armv7/at91/clock.c
+8
-0
arch/arm/cpu/armv7/at91/sama5d4_devices.c
arch/arm/cpu/armv7/at91/sama5d4_devices.c
+47
-0
arch/arm/cpu/at91-common/Makefile
arch/arm/cpu/at91-common/Makefile
+1
-0
arch/arm/cpu/at91-common/mpddrc.c
arch/arm/cpu/at91-common/mpddrc.c
+1
-1
arch/arm/cpu/at91-common/spl.c
arch/arm/cpu/at91-common/spl.c
+4
-0
arch/arm/cpu/at91-common/spl_atmel.c
arch/arm/cpu/at91-common/spl_atmel.c
+16
-0
arch/arm/include/asm/arch-at91/at91_common.h
arch/arm/include/asm/arch-at91/at91_common.h
+1
-0
arch/arm/include/asm/arch-at91/at91_pmc.h
arch/arm/include/asm/arch-at91/at91_pmc.h
+3
-6
arch/arm/include/asm/arch-at91/at91_rstc.h
arch/arm/include/asm/arch-at91/at91_rstc.h
+2
-0
arch/arm/include/asm/arch-at91/at91cap9.h
arch/arm/include/asm/arch-at91/at91cap9.h
+0
-78
arch/arm/include/asm/arch-at91/at91cap9_matrix.h
arch/arm/include/asm/arch-at91/at91cap9_matrix.h
+0
-129
arch/arm/include/asm/arch-at91/at91sam9_matrix.h
arch/arm/include/asm/arch-at91/at91sam9_matrix.h
+0
-2
arch/arm/include/asm/arch-at91/hardware.h
arch/arm/include/asm/arch-at91/hardware.h
+0
-2
arch/arm/include/asm/arch-at91/sama5_matrix.h
arch/arm/include/asm/arch-at91/sama5_matrix.h
+37
-0
arch/arm/include/asm/arch-at91/sama5_sfr.h
arch/arm/include/asm/arch-at91/sama5_sfr.h
+38
-0
arch/arm/include/asm/arch-at91/sama5d4.h
arch/arm/include/asm/arch-at91/sama5d4.h
+2
-0
board/atmel/sama5d4_xplained/sama5d4_xplained.c
board/atmel/sama5d4_xplained/sama5d4_xplained.c
+85
-0
board/atmel/sama5d4ek/sama5d4ek.c
board/atmel/sama5d4ek/sama5d4ek.c
+85
-0
common/board_f.c
common/board_f.c
+1
-1
configs/at91sam9g20ek_2mmc_defconfig
configs/at91sam9g20ek_2mmc_defconfig
+3
-0
configs/sama5d4_xplained_mmc_defconfig
configs/sama5d4_xplained_mmc_defconfig
+1
-0
configs/sama5d4_xplained_nandflash_defconfig
configs/sama5d4_xplained_nandflash_defconfig
+1
-0
configs/sama5d4_xplained_spiflash_defconfig
configs/sama5d4_xplained_spiflash_defconfig
+1
-0
configs/sama5d4ek_mmc_defconfig
configs/sama5d4ek_mmc_defconfig
+1
-0
configs/sama5d4ek_nandflash_defconfig
configs/sama5d4ek_nandflash_defconfig
+1
-0
configs/sama5d4ek_spiflash_defconfig
configs/sama5d4ek_spiflash_defconfig
+1
-0
drivers/mtd/nand/atmel_nand.c
drivers/mtd/nand/atmel_nand.c
+9
-0
drivers/mtd/nand/atmel_nand_ecc.h
drivers/mtd/nand/atmel_nand_ecc.h
+20
-0
drivers/video/atmel_lcdfb.c
drivers/video/atmel_lcdfb.c
+1
-1
drivers/watchdog/at91sam9_wdt.c
drivers/watchdog/at91sam9_wdt.c
+4
-0
include/configs/at91sam9260ek.h
include/configs/at91sam9260ek.h
+4
-2
include/configs/at91sam9x5ek.h
include/configs/at91sam9x5ek.h
+6
-5
include/configs/sama5d3_xplained.h
include/configs/sama5d3_xplained.h
+5
-4
include/configs/sama5d3xek.h
include/configs/sama5d3xek.h
+6
-4
include/configs/sama5d4_xplained.h
include/configs/sama5d4_xplained.h
+56
-0
include/configs/sama5d4ek.h
include/configs/sama5d4ek.h
+56
-0
include/configs/taurus.h
include/configs/taurus.h
+6
-3
未找到文件。
README
浏览文件 @
c956662c
...
...
@@ -1257,6 +1257,9 @@ The following options need to be configured:
SoC, then define this variable and provide board
specific code for the "hw_watchdog_reset" function.
CONFIG_AT91_HW_WDT_TIMEOUT
specify the timeout in seconds. default 2 seconds.
- U-Boot Version:
CONFIG_VERSION_VARIABLE
If this variable is defined, an environment variable
...
...
arch/arm/Kconfig
浏览文件 @
c956662c
...
...
@@ -527,10 +527,12 @@ config TARGET_SAMA5D3XEK
config TARGET_SAMA5D4_XPLAINED
bool "Support sama5d4_xplained"
select CPU_V7
select SUPPORT_SPL
config TARGET_SAMA5D4EK
bool "Support sama5d4ek"
select CPU_V7
select SUPPORT_SPL
config TARGET_BCM28155_AP
bool "Support bcm28155_ap"
...
...
arch/arm/cpu/arm926ejs/at91/Makefile
浏览文件 @
c956662c
...
...
@@ -5,7 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_AT91CAP9)
+=
at91cap9_devices.o
obj-$(CONFIG_AT91SAM9260)
+=
at91sam9260_devices.o
obj-$(CONFIG_AT91SAM9G20)
+=
at91sam9260_devices.o
obj-$(CONFIG_AT91SAM9XE)
+=
at91sam9260_devices.o
...
...
arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c
已删除
100644 → 0
浏览文件 @
0dac731d
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
*
* (C) Copyright 2009
* Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
* esd electronic system design gmbh <www.esd.eu>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
void
at91_serial0_hw_init
(
void
)
{
at91_pmc_t
*
pmc
=
(
at91_pmc_t
*
)
AT91_PMC_BASE
;
at91_set_a_periph
(
AT91_PIO_PORTA
,
22
,
1
);
/* TXD0 */
at91_set_a_periph
(
AT91_PIO_PORTA
,
23
,
0
);
/* RXD0 */
writel
(
1
<<
AT91CAP9_ID_US0
,
&
pmc
->
pcer
);
}
void
at91_serial1_hw_init
(
void
)
{
at91_pmc_t
*
pmc
=
(
at91_pmc_t
*
)
AT91_PMC_BASE
;
at91_set_a_periph
(
AT91_PIO_PORTD
,
0
,
1
);
/* TXD1 */
at91_set_a_periph
(
AT91_PIO_PORTD
,
1
,
0
);
/* RXD1 */
writel
(
1
<<
AT91CAP9_ID_US1
,
&
pmc
->
pcer
);
}
void
at91_serial2_hw_init
(
void
)
{
at91_pmc_t
*
pmc
=
(
at91_pmc_t
*
)
AT91_PMC_BASE
;
at91_set_a_periph
(
AT91_PIO_PORTD
,
2
,
1
);
/* TXD2 */
at91_set_a_periph
(
AT91_PIO_PORTD
,
3
,
0
);
/* RXD2 */
writel
(
1
<<
AT91CAP9_ID_US2
,
&
pmc
->
pcer
);
}
void
at91_serial3_hw_init
(
void
)
{
at91_pmc_t
*
pmc
=
(
at91_pmc_t
*
)
AT91_PMC_BASE
;
at91_set_a_periph
(
AT91_PIO_PORTC
,
30
,
0
);
/* DRXD */
at91_set_a_periph
(
AT91_PIO_PORTC
,
31
,
1
);
/* DTXD */
writel
(
1
<<
AT91_ID_SYS
,
&
pmc
->
pcer
);
}
void
at91_serial_hw_init
(
void
)
{
#ifdef CONFIG_USART0
at91_serial0_hw_init
();
#endif
#ifdef CONFIG_USART1
at91_serial1_hw_init
();
#endif
#ifdef CONFIG_USART2
at91_serial2_hw_init
();
#endif
#ifdef CONFIG_USART3
/* DBGU */
at91_serial3_hw_init
();
#endif
}
#ifdef CONFIG_HAS_DATAFLASH
void
at91_spi0_hw_init
(
unsigned
long
cs_mask
)
{
at91_pmc_t
*
pmc
=
(
at91_pmc_t
*
)
AT91_PMC_BASE
;
at91_set_b_periph
(
AT91_PIO_PORTA
,
0
,
0
);
/* SPI0_MISO */
at91_set_b_periph
(
AT91_PIO_PORTA
,
1
,
0
);
/* SPI0_MOSI */
at91_set_b_periph
(
AT91_PIO_PORTA
,
2
,
0
);
/* SPI0_SPCK */
/* Enable clock */
writel
(
1
<<
AT91CAP9_ID_SPI0
,
&
pmc
->
pcer
);
if
(
cs_mask
&
(
1
<<
0
))
{
at91_set_b_periph
(
AT91_PIO_PORTA
,
5
,
1
);
}
if
(
cs_mask
&
(
1
<<
1
))
{
at91_set_b_periph
(
AT91_PIO_PORTA
,
3
,
1
);
}
if
(
cs_mask
&
(
1
<<
2
))
{
at91_set_b_periph
(
AT91_PIO_PORTD
,
0
,
1
);
}
if
(
cs_mask
&
(
1
<<
3
))
{
at91_set_b_periph
(
AT91_PIO_PORTD
,
1
,
1
);
}
if
(
cs_mask
&
(
1
<<
4
))
{
at91_set_pio_output
(
AT91_PIO_PORTA
,
5
,
1
);
}
if
(
cs_mask
&
(
1
<<
5
))
{
at91_set_pio_output
(
AT91_PIO_PORTA
,
3
,
1
);
}
if
(
cs_mask
&
(
1
<<
6
))
{
at91_set_pio_output
(
AT91_PIO_PORTD
,
0
,
1
);
}
if
(
cs_mask
&
(
1
<<
7
))
{
at91_set_pio_output
(
AT91_PIO_PORTD
,
1
,
1
);
}
}
void
at91_spi1_hw_init
(
unsigned
long
cs_mask
)
{
at91_pmc_t
*
pmc
=
(
at91_pmc_t
*
)
AT91_PMC_BASE
;
at91_set_a_periph
(
AT91_PIO_PORTB
,
12
,
0
);
/* SPI1_MISO */
at91_set_a_periph
(
AT91_PIO_PORTB
,
13
,
0
);
/* SPI1_MOSI */
at91_set_a_periph
(
AT91_PIO_PORTB
,
14
,
0
);
/* SPI1_SPCK */
/* Enable clock */
writel
(
1
<<
AT91CAP9_ID_SPI1
,
&
pmc
->
pcer
);
if
(
cs_mask
&
(
1
<<
0
))
{
at91_set_a_periph
(
AT91_PIO_PORTB
,
15
,
1
);
}
if
(
cs_mask
&
(
1
<<
1
))
{
at91_set_a_periph
(
AT91_PIO_PORTB
,
16
,
1
);
}
if
(
cs_mask
&
(
1
<<
2
))
{
at91_set_a_periph
(
AT91_PIO_PORTB
,
17
,
1
);
}
if
(
cs_mask
&
(
1
<<
3
))
{
at91_set_a_periph
(
AT91_PIO_PORTB
,
18
,
1
);
}
if
(
cs_mask
&
(
1
<<
4
))
{
at91_set_pio_output
(
AT91_PIO_PORTB
,
15
,
1
);
}
if
(
cs_mask
&
(
1
<<
5
))
{
at91_set_pio_output
(
AT91_PIO_PORTB
,
16
,
1
);
}
if
(
cs_mask
&
(
1
<<
6
))
{
at91_set_pio_output
(
AT91_PIO_PORTB
,
17
,
1
);
}
if
(
cs_mask
&
(
1
<<
7
))
{
at91_set_pio_output
(
AT91_PIO_PORTB
,
18
,
1
);
}
}
#endif
#ifdef CONFIG_MACB
void
at91_macb_hw_init
(
void
)
{
at91_set_a_periph
(
AT91_PIO_PORTB
,
21
,
0
);
/* ETXCK_EREFCK */
at91_set_a_periph
(
AT91_PIO_PORTB
,
22
,
0
);
/* ERXDV */
at91_set_a_periph
(
AT91_PIO_PORTB
,
25
,
0
);
/* ERX0 */
at91_set_a_periph
(
AT91_PIO_PORTB
,
26
,
0
);
/* ERX1 */
at91_set_a_periph
(
AT91_PIO_PORTB
,
27
,
0
);
/* ERXER */
at91_set_a_periph
(
AT91_PIO_PORTB
,
28
,
0
);
/* ETXEN */
at91_set_a_periph
(
AT91_PIO_PORTB
,
23
,
0
);
/* ETX0 */
at91_set_a_periph
(
AT91_PIO_PORTB
,
24
,
0
);
/* ETX1 */
at91_set_a_periph
(
AT91_PIO_PORTB
,
30
,
0
);
/* EMDIO */
at91_set_a_periph
(
AT91_PIO_PORTB
,
29
,
0
);
/* EMDC */
#ifndef CONFIG_RMII
at91_set_b_periph
(
AT91_PIO_PORTC
,
25
,
0
);
/* ECRS */
at91_set_b_periph
(
AT91_PIO_PORTC
,
26
,
0
);
/* ECOL */
at91_set_b_periph
(
AT91_PIO_PORTC
,
22
,
0
);
/* ERX2 */
at91_set_b_periph
(
AT91_PIO_PORTC
,
23
,
0
);
/* ERX3 */
at91_set_b_periph
(
AT91_PIO_PORTC
,
27
,
0
);
/* ERXCK */
at91_set_b_periph
(
AT91_PIO_PORTC
,
20
,
0
);
/* ETX2 */
at91_set_b_periph
(
AT91_PIO_PORTC
,
21
,
0
);
/* ETX3 */
at91_set_b_periph
(
AT91_PIO_PORTC
,
24
,
0
);
/* ETXER */
#endif
}
#endif
#ifdef CONFIG_AT91_CAN
void
at91_can_hw_init
(
void
)
{
at91_pmc_t
*
pmc
=
(
at91_pmc_t
*
)
AT91_PMC_BASE
;
at91_set_a_periph
(
AT91_PIO_PORTA
,
12
,
0
);
/* CAN_TX */
at91_set_a_periph
(
AT91_PIO_PORTA
,
13
,
1
);
/* CAN_RX */
/* Enable clock */
writel
(
1
<<
AT91CAP9_ID_CAN
,
&
pmc
->
pcer
);
}
#endif
arch/arm/cpu/armv7/at91/clock.c
浏览文件 @
c956662c
...
...
@@ -130,10 +130,18 @@ void at91_mck_init(u32 mckr)
AT91_PMC_MCKR_PRES_MASK
|
AT91_PMC_MCKR_MDIV_MASK
|
AT91_PMC_MCKR_PLLADIV_2
);
#ifdef CPU_HAS_H32MXDIV
tmp
&=
~
AT91_PMC_MCKR_H32MXDIV
;
#endif
tmp
|=
mckr
&
(
AT91_PMC_MCKR_CSS_MASK
|
AT91_PMC_MCKR_PRES_MASK
|
AT91_PMC_MCKR_MDIV_MASK
|
AT91_PMC_MCKR_PLLADIV_2
);
#ifdef CPU_HAS_H32MXDIV
tmp
|=
mckr
&
AT91_PMC_MCKR_H32MXDIV
;
#endif
writel
(
tmp
,
&
pmc
->
mckr
);
while
(
!
(
readl
(
&
pmc
->
sr
)
&
AT91_PMC_MCKRDY
))
...
...
arch/arm/cpu/armv7/at91/sama5d4_devices.c
浏览文件 @
c956662c
...
...
@@ -10,6 +10,8 @@
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/clk.h>
#include <asm/arch/sama5_matrix.h>
#include <asm/arch/sama5_sfr.h>
#include <asm/arch/sama5d4.h>
char
*
get_cpu_name
()
...
...
@@ -44,3 +46,48 @@ void at91_udp_hw_init(void)
at91_periph_clk_enable
(
ATMEL_ID_UDPHS
);
}
#endif
#ifdef CONFIG_SPL_BUILD
void
matrix_init
(
void
)
{
struct
atmel_matrix
*
h64mx
=
(
struct
atmel_matrix
*
)
ATMEL_BASE_MATRIX0
;
struct
atmel_matrix
*
h32mx
=
(
struct
atmel_matrix
*
)
ATMEL_BASE_MATRIX1
;
int
i
;
/* Disable the write protect */
writel
(
ATMEL_MATRIX_WPMR_WPKEY
&
~
ATMEL_MATRIX_WPMR_WPEN
,
&
h64mx
->
wpmr
);
writel
(
ATMEL_MATRIX_WPMR_WPKEY
&
~
ATMEL_MATRIX_WPMR_WPEN
,
&
h32mx
->
wpmr
);
/* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */
for
(
i
=
4
;
i
<=
10
;
i
++
)
{
writel
(
0x000f0f0f
,
&
h64mx
->
ssr
[
i
]);
writel
(
0x0000ffff
,
&
h64mx
->
sassr
[
i
]);
writel
(
0x0000000f
,
&
h64mx
->
srtsr
[
i
]);
}
/* CS3 */
writel
(
0x00c0c0c0
,
&
h32mx
->
ssr
[
3
]);
writel
(
0xff000000
,
&
h32mx
->
sassr
[
3
]);
writel
(
0xff000000
,
&
h32mx
->
srtsr
[
3
]);
/* NFC SRAM */
writel
(
0x00010101
,
&
h32mx
->
ssr
[
4
]);
writel
(
0x00000001
,
&
h32mx
->
sassr
[
4
]);
writel
(
0x00000001
,
&
h32mx
->
srtsr
[
4
]);
/* Enable the write protect */
writel
(
ATMEL_MATRIX_WPMR_WPKEY
|
ATMEL_MATRIX_WPMR_WPEN
,
&
h64mx
->
wpmr
);
writel
(
ATMEL_MATRIX_WPMR_WPKEY
|
ATMEL_MATRIX_WPMR_WPEN
,
&
h32mx
->
wpmr
);
}
void
redirect_int_from_saic_to_aic
(
void
)
{
struct
atmel_sfr
*
sfr
=
(
struct
atmel_sfr
*
)
ATMEL_BASE_SFR
;
u32
key32
;
if
(
!
(
readl
(
&
sfr
->
aicredir
)
&
ATMEL_SFR_AICREDIR_NSAIC
))
{
key32
=
readl
(
&
sfr
->
sn1
)
^
ATMEL_SFR_AICREDIR_KEY
;
writel
((
key32
|
ATMEL_SFR_AICREDIR_NSAIC
),
&
sfr
->
aicredir
);
}
}
#endif
arch/arm/cpu/at91-common/Makefile
浏览文件 @
c956662c
...
...
@@ -13,5 +13,6 @@ ifneq ($(CONFIG_SPL_BUILD),)
obj-$(CONFIG_AT91SAM9G20)
+=
sdram.o spl_at91.o
obj-$(CONFIG_AT91SAM9M10G45)
+=
mpddrc.o spl_at91.o
obj-$(CONFIG_SAMA5D3)
+=
mpddrc.o spl_atmel.o
obj-$(CONFIG_SAMA5D4)
+=
mpddrc.o spl_atmel.o
obj-y
+=
spl.o
endif
arch/arm/cpu/at91-common/mpddrc.c
浏览文件 @
c956662c
...
...
@@ -19,7 +19,7 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address)
static
int
ddr2_decodtype_is_seq
(
u32
cr
)
{
#if defined(CONFIG_SAMA5D3)
#if defined(CONFIG_SAMA5D3)
|| defined(CONFIG_SAMA5D4)
if
(
cr
&
ATMEL_MPDDRC_CR_DECOD_INTERLEAVED
)
return
0
;
#endif
...
...
arch/arm/cpu/at91-common/spl.c
浏览文件 @
c956662c
...
...
@@ -12,12 +12,16 @@
#include <asm/arch/clk.h>
#include <spl.h>
#if defined(CONFIG_AT91SAM9_WATCHDOG)
void
at91_disable_wdt
(
void
)
{
}
#else
void
at91_disable_wdt
(
void
)
{
struct
at91_wdt
*
wdt
=
(
struct
at91_wdt
*
)
ATMEL_BASE_WDT
;
writel
(
AT91_WDT_MR_WDDIS
,
&
wdt
->
mr
);
}
#endif
u32
spl_boot_device
(
void
)
{
...
...
arch/arm/cpu/at91-common/spl_atmel.c
浏览文件 @
c956662c
...
...
@@ -51,11 +51,23 @@ static void switch_to_main_crystal_osc(void)
while
(
!
(
readl
(
&
pmc
->
mcfr
)
&
AT91_PMC_MAINRDY
))
;
#ifndef CONFIG_SAMA5D4
tmp
=
readl
(
&
pmc
->
mor
);
tmp
&=
~
AT91_PMC_MOR_MOSCRCEN
;
tmp
&=
~
AT91_PMC_MOR_KEY
(
0xff
);
tmp
|=
AT91_PMC_MOR_KEY
(
0x37
);
writel
(
tmp
,
&
pmc
->
mor
);
#endif
}
__weak
void
matrix_init
(
void
)
{
/* This only be used for sama5d4 soc now */
}
__weak
void
redirect_int_from_saic_to_aic
(
void
)
{
/* This only be used for sama5d4 soc now */
}
void
s_init
(
void
)
...
...
@@ -70,6 +82,10 @@ void s_init(void)
at91_clock_init
(
CONFIG_SYS_AT91_MAIN_CLOCK
);
matrix_init
();
redirect_int_from_saic_to_aic
();
timer_init
();
board_early_init_f
();
...
...
arch/arm/include/asm/arch-at91/at91_common.h
浏览文件 @
c956662c
...
...
@@ -33,5 +33,6 @@ void at91_mck_init(u32 mckr);
void
at91_spl_board_init
(
void
);
void
at91_disable_wdt
(
void
);
void
matrix_init
(
void
);
void
redirect_int_from_saic_to_aic
(
void
);
#endif
/* AT91_COMMON_H */
arch/arm/include/asm/arch-at91/at91_pmc.h
浏览文件 @
c956662c
...
...
@@ -157,10 +157,8 @@ typedef struct at91_pmc {
#define AT91_PMC_PCK (1 << 0)
/* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1)
/* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91RM9200_PMC_MCKUDP (1 << 2)
/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
#define AT91CAP9_PMC_DDR (1 << 2)
/* DDR Clock [AT91CAP9 revC only] */
#define AT91RM9200_PMC_UHP (1 << 4)
/* USB Host Port Clock [AT91RM9200 only] */
#define AT91SAM926x_PMC_UHP (1 << 6)
/* USB Host Port Clock [AT91SAM926x only] */
#define AT91CAP9_PMC_UHP (1 << 6)
/* USB Host Port Clock [AT91CAP9 only] */
#define AT91SAM926x_PMC_UDP (1 << 7)
/* USB Devcice Port Clock [AT91SAM926x only] */
#define AT91_PMC_PCK0 (1 << 8)
/* Programmable Clock 0 */
#define AT91_PMC_PCK1 (1 << 9)
/* Programmable Clock 1 */
...
...
@@ -175,7 +173,7 @@ typedef struct at91_pmc {
#define AT91_PMC_BIASCOUNT (0xf << 28)
/* UTMI PLL Start-up Time */
#define AT91_PMC_MOSCEN (1 << 0)
/* Main Oscillator Enable */
#define AT91_PMC_OSCBYPASS (1 << 1)
/* Oscillator Bypass [SAM9x
, CAP9
] */
#define AT91_PMC_OSCBYPASS (1 << 1)
/* Oscillator Bypass [SAM9x] */
#define AT91_PMC_OSCOUNT (0xff << 8)
/* Main Oscillator Start-up Time */
#define AT91_PMC_MAINF (0xffff << 0)
/* Main Clock Frequency */
...
...
@@ -210,7 +208,7 @@ typedef struct at91_pmc {
#define AT91RM9200_PMC_MDIV_2 (1 << 8)
#define AT91RM9200_PMC_MDIV_3 (2 << 8)
#define AT91RM9200_PMC_MDIV_4 (3 << 8)
#define AT91SAM9_PMC_MDIV_1 (0 << 8)
/* [SAM9
,CAP9
only] */
#define AT91SAM9_PMC_MDIV_1 (0 << 8)
/* [SAM9 only] */
#define AT91SAM9_PMC_MDIV_2 (1 << 8)
#define AT91SAM9_PMC_MDIV_4 (2 << 8)
#define AT91SAM9_PMC_MDIV_3 (3 << 8)
/* [some SAM9 only] */
...
...
@@ -230,8 +228,7 @@ typedef struct at91_pmc {
#define AT91_PMC_LOCKA (1 << 1)
/* PLLA Lock */
#define AT91_PMC_LOCKB (1 << 2)
/* PLLB Lock */
#define AT91_PMC_MCKRDY (1 << 3)
/* Master Clock */
#define AT91_PMC_LOCKU (1 << 6)
/* UPLL Lock [AT91CAP9 only] */
#define AT91_PMC_OSCSEL (1 << 7)
/* Slow Clock Oscillator [AT91CAP9 revC only] */
#define AT91_PMC_LOCKU (1 << 6)
/* UPLL Lock */
#define AT91_PMC_PCK0RDY (1 << 8)
/* Programmable Clock 0 */
#define AT91_PMC_PCK1RDY (1 << 9)
/* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10)
/* Programmable Clock 2 */
...
...
arch/arm/include/asm/arch-at91/at91_rstc.h
浏览文件 @
c956662c
...
...
@@ -13,6 +13,8 @@
#ifndef AT91_RSTC_H
#define AT91_RSTC_H
/* Reset Controller Status Register */
#define AT91_ASM_RSTC_SR (ATMEL_BASE_RSTC + 0x04)
#define AT91_ASM_RSTC_MR (ATMEL_BASE_RSTC + 0x08)
#ifndef __ASSEMBLY__
...
...
arch/arm/include/asm/arch-at91/at91cap9.h
已删除
100644 → 0
浏览文件 @
0dac731d
/*
* [origin: Linux kernel include/asm-arm/arch-at91/at91cap9.h]
*
* Copyright (C) 2007 Stelian Pop <stelian@popies.net>
* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
* Copyright (C) 2007 Atmel Corporation.
*
* Common definitions.
* Based on AT91CAP9 datasheet revision B (Preliminary).
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef AT91CAP9_H
#define AT91CAP9_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0
/* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1
/* System Peripherals */
#define AT91CAP9_ID_PIOABCD 2
/* Parallel IO Controller A, B, C and D */
#define AT91CAP9_ID_MPB0 3
/* MP Block Peripheral 0 */
#define AT91CAP9_ID_MPB1 4
/* MP Block Peripheral 1 */
#define AT91CAP9_ID_MPB2 5
/* MP Block Peripheral 2 */
#define AT91CAP9_ID_MPB3 6
/* MP Block Peripheral 3 */
#define AT91CAP9_ID_MPB4 7
/* MP Block Peripheral 4 */
#define AT91CAP9_ID_US0 8
/* USART 0 */
#define AT91CAP9_ID_US1 9
/* USART 1 */
#define AT91CAP9_ID_US2 10
/* USART 2 */
#define AT91CAP9_ID_MCI0 11
/* Multimedia Card Interface 0 */
#define AT91CAP9_ID_MCI1 12
/* Multimedia Card Interface 1 */
#define AT91CAP9_ID_CAN 13
/* CAN */
#define AT91CAP9_ID_TWI 14
/* Two-Wire Interface */
#define AT91CAP9_ID_SPI0 15
/* Serial Peripheral Interface 0 */
#define AT91CAP9_ID_SPI1 16
/* Serial Peripheral Interface 0 */
#define AT91CAP9_ID_SSC0 17
/* Serial Synchronous Controller 0 */
#define AT91CAP9_ID_SSC1 18
/* Serial Synchronous Controller 1 */
#define AT91CAP9_ID_AC97C 19
/* AC97 Controller */
#define AT91CAP9_ID_TCB 20
/* Timer Counter 0, 1 and 2 */
#define AT91CAP9_ID_PWMC 21
/* Pulse Width Modulation Controller */
#define AT91CAP9_ID_EMAC 22
/* Ethernet */
#define AT91CAP9_ID_AESTDES 23
/* Advanced Encryption Standard, Triple DES */
#define AT91CAP9_ID_ADC 24
/* Analog-to-Digital Converter */
#define AT91CAP9_ID_ISI 25
/* Image Sensor Interface */
#define AT91CAP9_ID_LCDC 26
/* LCD Controller */
#define AT91CAP9_ID_DMA 27
/* DMA Controller */
#define AT91CAP9_ID_UDPHS 28
/* USB High Speed Device Port */
#define AT91CAP9_ID_UHP 29
/* USB Host Port */
#define AT91CAP9_ID_IRQ0 30
/* Advanced Interrupt Controller (IRQ0) */
#define AT91CAP9_ID_IRQ1 31
/* Advanced Interrupt Controller (IRQ1) */
#define AT91_PIO_BASE 0xfffff200
#define AT91_PMC_BASE 0xfffffc00
#define AT91_RSTC_BASE 0xfffffd00
#define AT91_PIT_BASE 0xfffffd30
/*
* Internal Memory.
*/
#define AT91CAP9_SRAM_BASE 0x00100000
/* Internal SRAM base address */
#define AT91CAP9_SRAM_SIZE (32 * SZ_1K)
/* Internal SRAM size (32Kb) */
#define AT91CAP9_ROM_BASE 0x00400000
/* Internal ROM base address */
#define AT91CAP9_ROM_SIZE (32 * SZ_1K)
/* Internal ROM size (32Kb) */
#define AT91CAP9_LCDC_BASE 0x00500000
/* LCD Controller */
#define AT91CAP9_UDPHS_BASE 0x00600000
/* USB High Speed Device Port */
#define AT91CAP9_UHP_BASE 0x00700000
/* USB Host controller */
#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
/*
* Cpu Name
*/
#define CONFIG_SYS_AT91_CPU_NAME "AT91CAP9"
#endif
arch/arm/include/asm/arch-at91/at91cap9_matrix.h
已删除
100644 → 0
浏览文件 @
0dac731d
/*
* [origin: Linux kernel include/asm-arm/arch-at91/at91cap9_matrix.h]
*
* Copyright (C) 2007 Stelian Pop <stelian@popies.net>
* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
* Copyright (C) 2006 Atmel Corporation.
*
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
* Based on AT91CAP9 datasheet revision B (Preliminary).
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef AT91CAP9_MATRIX_H
#define AT91CAP9_MATRIX_H
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00)
/* Master Configuration Register 0 */
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04)
/* Master Configuration Register 1 */
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08)
/* Master Configuration Register 2 */
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C)
/* Master Configuration Register 3 */
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10)
/* Master Configuration Register 4 */
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14)
/* Master Configuration Register 5 */
#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18)
/* Master Configuration Register 6 */
#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C)
/* Master Configuration Register 7 */
#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20)
/* Master Configuration Register 8 */
#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24)
/* Master Configuration Register 9 */
#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28)
/* Master Configuration Register 10 */
#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C)
/* Master Configuration Register 11 */
#define AT91_MATRIX_ULBT (7 << 0)
/* Undefined Length Burst Type */
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40)
/* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44)
/* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48)
/* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C)
/* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50)
/* Slave Configuration Register 4 */
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54)
/* Slave Configuration Register 5 */
#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58)
/* Slave Configuration Register 6 */
#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C)
/* Slave Configuration Register 7 */
#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60)
/* Slave Configuration Register 8 */
#define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64)
/* Slave Configuration Register 9 */
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0)
/* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16)
/* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18)
/* Fixed Index of Default Master */
#define AT91_MATRIX_ARBT (3 << 24)
/* Arbitration Type */
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80)
/* Priority Register A for Slave 0 */
#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84)
/* Priority Register B for Slave 0 */
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88)
/* Priority Register A for Slave 1 */
#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C)
/* Priority Register B for Slave 1 */
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90)
/* Priority Register A for Slave 2 */
#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94)
/* Priority Register B for Slave 2 */
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98)
/* Priority Register A for Slave 3 */
#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C)
/* Priority Register B for Slave 3 */
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0)
/* Priority Register A for Slave 4 */
#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4)
/* Priority Register B for Slave 4 */
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8)
/* Priority Register A for Slave 5 */
#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC)
/* Priority Register B for Slave 5 */
#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0)
/* Priority Register A for Slave 6 */
#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4)
/* Priority Register B for Slave 6 */
#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8)
/* Priority Register A for Slave 7 */
#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC)
/* Priority Register B for Slave 7 */
#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0)
/* Priority Register A for Slave 8 */
#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4)
/* Priority Register B for Slave 8 */
#define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8)
/* Priority Register A for Slave 9 */
#define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC)
/* Priority Register B for Slave 9 */
#define AT91_MATRIX_M0PR (3 << 0)
/* Master 0 Priority */
#define AT91_MATRIX_M1PR (3 << 4)
/* Master 1 Priority */
#define AT91_MATRIX_M2PR (3 << 8)
/* Master 2 Priority */
#define AT91_MATRIX_M3PR (3 << 12)
/* Master 3 Priority */
#define AT91_MATRIX_M4PR (3 << 16)
/* Master 4 Priority */
#define AT91_MATRIX_M5PR (3 << 20)
/* Master 5 Priority */
#define AT91_MATRIX_M6PR (3 << 24)
/* Master 6 Priority */
#define AT91_MATRIX_M7PR (3 << 28)
/* Master 7 Priority */
#define AT91_MATRIX_M8PR (3 << 0)
/* Master 8 Priority (in Register B) */
#define AT91_MATRIX_M9PR (3 << 4)
/* Master 9 Priority (in Register B) */
#define AT91_MATRIX_M10PR (3 << 8)
/* Master 10 Priority (in Register B) */
#define AT91_MATRIX_M11PR (3 << 12)
/* Master 11 Priority (in Register B) */
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100)
/* Master Remap Control Register */
#define AT91_MATRIX_RCB0 (1 << 0)
/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1)
/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_RCB2 (1 << 2)
#define AT91_MATRIX_RCB3 (1 << 3)
#define AT91_MATRIX_RCB4 (1 << 4)
#define AT91_MATRIX_RCB5 (1 << 5)
#define AT91_MATRIX_RCB6 (1 << 6)
#define AT91_MATRIX_RCB7 (1 << 7)
#define AT91_MATRIX_RCB8 (1 << 8)
#define AT91_MATRIX_RCB9 (1 << 9)
#define AT91_MATRIX_RCB10 (1 << 10)
#define AT91_MATRIX_RCB11 (1 << 11)
#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114)
/* MPBlock Slave 0 Special Function Register */
#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C)
/* MPBlock Slave 1 Special Function Register */
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120)
/* EBI Chip Select Assignment Register */
#define AT91_MATRIX_EBI_CS1A (1 << 1)
/* Chip Select 1 Assignment */
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
#define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1)
#define AT91_MATRIX_EBI_CS3A (1 << 3)
/* Chip Select 3 Assignment */
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_EBI_CS4A (1 << 4)
/* Chip Select 4 Assignment */
#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
#define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4)
#define AT91_MATRIX_EBI_CS5A (1 << 5)
/* Chip Select 5 Assignment */
#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
#define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5)
#define AT91_MATRIX_EBI_DBPUC (1 << 8)
/* Data Bus Pull-up Configuration */
#define AT91_MATRIX_EBI_DQSPDC (1 << 9)
/* Data Qualifier Strobe Pull-Down Configuration */
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16)
/* Memory voltage selection */
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
#define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C)
/* MPBlock Slave 2 Special Function Register */
#define AT91_MPBS3_SFR (AT91_MATRIX + 0x130)
/* MPBlock Slave 3 Special Function Register */
#define AT91_APB_SFR (AT91_MATRIX + 0x134)
/* APB Bridge Special Function Register */
#endif
arch/arm/include/asm/arch-at91/at91sam9_matrix.h
浏览文件 @
c956662c
...
...
@@ -15,8 +15,6 @@
#include <asm/arch/at91sam9263_matrix.h>
#elif defined(CONFIG_AT91SAM9RL)
#include <asm/arch/at91sam9rl_matrix.h>
#elif defined(CONFIG_AT91CAP9)
#include <asm/arch/at91cap9_matrix.h>
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
#include <asm/arch/at91sam9g45_matrix.h>
#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
...
...
arch/arm/include/asm/arch-at91/hardware.h
浏览文件 @
c956662c
...
...
@@ -23,8 +23,6 @@
# include <asm/arch/at91sam9g45.h>
#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
# include <asm/arch/at91sam9x5.h>
#elif defined(CONFIG_AT91CAP9)
# include <asm/arch/at91cap9.h>
#elif defined(CONFIG_SAMA5D3)
# include <asm/arch/sama5d3.h>
#elif defined(CONFIG_SAMA5D4)
...
...
arch/arm/include/asm/arch-at91/sama5_matrix.h
0 → 100644
浏览文件 @
c956662c
/*
* Bus Matrix header file for the SAMA5 family
*
* Copyright (C) 2014 Atmel
* Bo Shen <voice.shen@atmel.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __SAMA5_MATRIX_H
#define __SAMA5_MATRIX_H
struct
atmel_matrix
{
u32
mcfg
[
16
];
/* 0x00 ~ 0x3c: Master Configuration Register */
u32
scfg
[
16
];
/* 0x40 ~ 0x7c: Slave Configuration Register */
u32
pras
[
16
][
2
];
/* 0x80 ~ 0xfc: Priority Register A/B */
u32
res1
[
20
];
/* 0x100 ~ 0x14c */
u32
meier
;
/* 0x150: Master Error Interrupt Enable Register */
u32
meidr
;
/* 0x154: Master Error Interrupt Disable Register */
u32
meimr
;
/* 0x158: Master Error Interrupt Mask Register */
u32
mesr
;
/* 0x15c: Master Error Status Register */
u32
mear
[
16
];
/* 0x160 ~ 0x19c: Master Error Address Register */
u32
res2
[
17
];
/* 0x1A0 ~ 0x1E0 */
u32
wpmr
;
/* 0x1E4: Write Protection Mode Register */
u32
wpsr
;
/* 0x1E8: Write Protection Status Register */
u32
res3
[
5
];
/* 0x1EC ~ 0x1FC */
u32
ssr
[
16
];
/* 0x200 ~ 0x23c: Security Slave Register */
u32
sassr
[
16
];
/* 0x240 ~ 0x27c: Security Areas Split Slave Register */
u32
srtsr
[
16
];
/* 0x280 ~ 0x2bc: Security Region Top Slave */
u32
spselr
[
3
];
/* 0x2c0 ~ 0x2c8: Security Peripheral Select Register */
};
/* Bit field in WPMR */
#define ATMEL_MATRIX_WPMR_WPKEY 0x4D415400
#define ATMEL_MATRIX_WPMR_WPEN 0x00000001
#endif
arch/arm/include/asm/arch-at91/sama5_sfr.h
0 → 100644
浏览文件 @
c956662c
/*
* Special Function Register (SFR)
*
* Copyright (C) 2014 Atmel
* Bo Shen <voice.shen@atmel.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __SAMA5_SFR_H
#define __SAMA5_SFR_H
struct
atmel_sfr
{
u32
reserved1
;
/* 0x00 */
u32
ddrcfg
;
/* 0x04: DDR Configuration Register */
u32
reserved2
;
/* 0x08 */
u32
reserved3
;
/* 0x0c */
u32
ohciicr
;
/* 0x10: OHCI Interrupt Configuration Register */
u32
ohciisr
;
/* 0x14: OHCI Interrupt Status Register */
u32
reserved4
[
4
];
/* 0x18 ~ 0x24 */
u32
secure
;
/* 0x28: Security Configuration Register */
u32
reserved5
[
5
];
/* 0x2c ~ 0x3c */
u32
ebicfg
;
/* 0x40: EBI Configuration Register */
u32
reserved6
[
2
];
/* 0x44 ~ 0x48 */
u32
sn0
;
/* 0x4c */
u32
sn1
;
/* 0x50 */
u32
aicredir
;
/* 0x54 */
};
/* Bit field in DDRCFG */
#define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000
#define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000
/* Bit field in AICREDIR */
#define ATMEL_SFR_AICREDIR_KEY 0x5F67B102
#define ATMEL_SFR_AICREDIR_NSAIC 0x00000001
#endif
arch/arm/include/asm/arch-at91/sama5d4.h
浏览文件 @
c956662c
...
...
@@ -126,6 +126,8 @@
#define ATMEL_BASE_ADC 0xfc034000
#define ATMEL_BASE_TWI3 0xfc038000
#define ATMEL_BASE_MATRIX1 0xfc054000
#define ATMEL_BASE_SMC 0xfc05c000
#define ATMEL_BASE_PMECC (ATMEL_BASE_SMC + 0x070)
#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_SMC + 0x500)
...
...
board/atmel/sama5d4_xplained/sama5d4_xplained.c
浏览文件 @
c956662c
...
...
@@ -10,6 +10,7 @@
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/atmel_mpddrc.h>
#include <asm/arch/atmel_usba_udc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
...
...
@@ -326,3 +327,87 @@ int board_eth_init(bd_t *bis)
return
rc
;
}
/* SPL */
#ifdef CONFIG_SPL_BUILD
void
spl_board_init
(
void
)
{
#ifdef CONFIG_SYS_USE_MMC
sama5d4_xplained_mci1_hw_init
();
#elif CONFIG_SYS_USE_NANDFLASH
sama5d4_xplained_nand_hw_init
();
#elif CONFIG_SYS_USE_SERIALFLASH
sama5d4_xplained_spi0_hw_init
();
#endif
}
static
void
ddr2_conf
(
struct
atmel_mpddr
*
ddr2
)
{
ddr2
->
md
=
(
ATMEL_MPDDRC_MD_DBW_32_BITS
|
ATMEL_MPDDRC_MD_DDR2_SDRAM
);
ddr2
->
cr
=
(
ATMEL_MPDDRC_CR_NC_COL_10
|
ATMEL_MPDDRC_CR_NR_ROW_14
|
ATMEL_MPDDRC_CR_CAS_DDR_CAS3
|
ATMEL_MPDDRC_CR_NB_8BANKS
|
ATMEL_MPDDRC_CR_NDQS_DISABLED
|
ATMEL_MPDDRC_CR_DECOD_INTERLEAVED
|
ATMEL_MPDDRC_CR_UNAL_SUPPORTED
);
ddr2
->
rtr
=
0x2b0
;
ddr2
->
tpr0
=
(
8
<<
ATMEL_MPDDRC_TPR0_TRAS_OFFSET
|
3
<<
ATMEL_MPDDRC_TPR0_TRCD_OFFSET
|
3
<<
ATMEL_MPDDRC_TPR0_TWR_OFFSET
|
10
<<
ATMEL_MPDDRC_TPR0_TRC_OFFSET
|
3
<<
ATMEL_MPDDRC_TPR0_TRP_OFFSET
|
2
<<
ATMEL_MPDDRC_TPR0_TRRD_OFFSET
|
2
<<
ATMEL_MPDDRC_TPR0_TWTR_OFFSET
|
2
<<
ATMEL_MPDDRC_TPR0_TMRD_OFFSET
);
ddr2
->
tpr1
=
(
2
<<
ATMEL_MPDDRC_TPR1_TXP_OFFSET
|
200
<<
ATMEL_MPDDRC_TPR1_TXSRD_OFFSET
|
25
<<
ATMEL_MPDDRC_TPR1_TXSNR_OFFSET
|
23
<<
ATMEL_MPDDRC_TPR1_TRFC_OFFSET
);
ddr2
->
tpr2
=
(
7
<<
ATMEL_MPDDRC_TPR2_TFAW_OFFSET
|
2
<<
ATMEL_MPDDRC_TPR2_TRTP_OFFSET
|
3
<<
ATMEL_MPDDRC_TPR2_TRPA_OFFSET
|
2
<<
ATMEL_MPDDRC_TPR2_TXARDS_OFFSET
|
8
<<
ATMEL_MPDDRC_TPR2_TXARD_OFFSET
);
}
void
mem_init
(
void
)
{
struct
at91_pmc
*
pmc
=
(
struct
at91_pmc
*
)
ATMEL_BASE_PMC
;
struct
atmel_mpddr
ddr2
;
ddr2_conf
(
&
ddr2
);
/* enable MPDDR clock */
at91_periph_clk_enable
(
ATMEL_ID_MPDDRC
);
writel
(
0x4
,
&
pmc
->
scer
);
/* DDRAM2 Controller initialize */
ddr2_init
(
ATMEL_BASE_DDRCS
,
&
ddr2
);
}
void
at91_pmc_init
(
void
)
{
struct
at91_pmc
*
pmc
=
(
struct
at91_pmc
*
)
ATMEL_BASE_PMC
;
u32
tmp
;
tmp
=
AT91_PMC_PLLAR_29
|
AT91_PMC_PLLXR_PLLCOUNT
(
0x3f
)
|
AT91_PMC_PLLXR_MUL
(
87
)
|
AT91_PMC_PLLXR_DIV
(
1
);
at91_plla_init
(
tmp
);
writel
(
0x0
<<
8
,
&
pmc
->
pllicpr
);
tmp
=
AT91_PMC_MCKR_H32MXDIV
|
AT91_PMC_MCKR_PLLADIV_2
|
AT91_PMC_MCKR_MDIV_3
|
AT91_PMC_MCKR_CSS_PLLA
;
at91_mck_init
(
tmp
);
}
#endif
board/atmel/sama5d4ek/sama5d4ek.c
浏览文件 @
c956662c
...
...
@@ -10,6 +10,7 @@
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/atmel_mpddrc.h>
#include <asm/arch/atmel_usba_udc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
...
...
@@ -325,3 +326,87 @@ int board_eth_init(bd_t *bis)
return
rc
;
}
/* SPL */
#ifdef CONFIG_SPL_BUILD
void
spl_board_init
(
void
)
{
#ifdef CONFIG_SYS_USE_MMC
sama5d4ek_mci1_hw_init
();
#elif CONFIG_SYS_USE_NANDFLASH
sama5d4ek_nand_hw_init
();
#elif CONFIG_SYS_USE_SERIALFLASH
sama5d4ek_spi0_hw_init
();
#endif
}
static
void
ddr2_conf
(
struct
atmel_mpddr
*
ddr2
)
{
ddr2
->
md
=
(
ATMEL_MPDDRC_MD_DBW_32_BITS
|
ATMEL_MPDDRC_MD_DDR2_SDRAM
);
ddr2
->
cr
=
(
ATMEL_MPDDRC_CR_NC_COL_10
|
ATMEL_MPDDRC_CR_NR_ROW_14
|
ATMEL_MPDDRC_CR_CAS_DDR_CAS3
|
ATMEL_MPDDRC_CR_NB_8BANKS
|
ATMEL_MPDDRC_CR_NDQS_DISABLED
|
ATMEL_MPDDRC_CR_DECOD_INTERLEAVED
|
ATMEL_MPDDRC_CR_UNAL_SUPPORTED
);
ddr2
->
rtr
=
0x2b0
;
ddr2
->
tpr0
=
(
8
<<
ATMEL_MPDDRC_TPR0_TRAS_OFFSET
|
3
<<
ATMEL_MPDDRC_TPR0_TRCD_OFFSET
|
3
<<
ATMEL_MPDDRC_TPR0_TWR_OFFSET
|
10
<<
ATMEL_MPDDRC_TPR0_TRC_OFFSET
|
3
<<
ATMEL_MPDDRC_TPR0_TRP_OFFSET
|
2
<<
ATMEL_MPDDRC_TPR0_TRRD_OFFSET
|
2
<<
ATMEL_MPDDRC_TPR0_TWTR_OFFSET
|
2
<<
ATMEL_MPDDRC_TPR0_TMRD_OFFSET
);
ddr2
->
tpr1
=
(
2
<<
ATMEL_MPDDRC_TPR1_TXP_OFFSET
|
200
<<
ATMEL_MPDDRC_TPR1_TXSRD_OFFSET
|
25
<<
ATMEL_MPDDRC_TPR1_TXSNR_OFFSET
|
23
<<
ATMEL_MPDDRC_TPR1_TRFC_OFFSET
);
ddr2
->
tpr2
=
(
7
<<
ATMEL_MPDDRC_TPR2_TFAW_OFFSET
|
2
<<
ATMEL_MPDDRC_TPR2_TRTP_OFFSET
|
3
<<
ATMEL_MPDDRC_TPR2_TRPA_OFFSET
|
2
<<
ATMEL_MPDDRC_TPR2_TXARDS_OFFSET
|
8
<<
ATMEL_MPDDRC_TPR2_TXARD_OFFSET
);
}
void
mem_init
(
void
)
{
struct
at91_pmc
*
pmc
=
(
struct
at91_pmc
*
)
ATMEL_BASE_PMC
;
struct
atmel_mpddr
ddr2
;
ddr2_conf
(
&
ddr2
);
/* enable MPDDR clock */
at91_periph_clk_enable
(
ATMEL_ID_MPDDRC
);
writel
(
0x4
,
&
pmc
->
scer
);
/* DDRAM2 Controller initialize */
ddr2_init
(
ATMEL_BASE_DDRCS
,
&
ddr2
);
}
void
at91_pmc_init
(
void
)
{
struct
at91_pmc
*
pmc
=
(
struct
at91_pmc
*
)
ATMEL_BASE_PMC
;
u32
tmp
;
tmp
=
AT91_PMC_PLLAR_29
|
AT91_PMC_PLLXR_PLLCOUNT
(
0x3f
)
|
AT91_PMC_PLLXR_MUL
(
87
)
|
AT91_PMC_PLLXR_DIV
(
1
);
at91_plla_init
(
tmp
);
writel
(
0x0
<<
8
,
&
pmc
->
pllicpr
);
tmp
=
AT91_PMC_MCKR_H32MXDIV
|
AT91_PMC_MCKR_PLLADIV_2
|
AT91_PMC_MCKR_MDIV_3
|
AT91_PMC_MCKR_CSS_PLLA
;
at91_mck_init
(
tmp
);
}
#endif
common/board_f.c
浏览文件 @
c956662c
...
...
@@ -111,7 +111,7 @@ static int init_func_watchdog_init(void)
{
# if defined(CONFIG_HW_WATCHDOG) && (defined(CONFIG_BLACKFIN) || \
defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
defined(CONFIG_SH))
defined(CONFIG_SH)
|| defined(CONFIG_AT91SAM9_WATCHDOG)
)
hw_watchdog_init
();
# endif
puts
(
" Watchdog enabled
\n
"
);
...
...
configs/at91sam9g20ek_mmc_defconfig
→
configs/at91sam9g20ek_
2
mmc_defconfig
浏览文件 @
c956662c
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_MMC"
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,
AT91SAM9G20EK_2MMC,
SYS_USE_MMC"
CONFIG_ARM=y
CONFIG_TARGET_AT91SAM9260EK=y
configs/sama5d4_xplained_mmc_defconfig
浏览文件 @
c956662c
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_SAMA5D4_XPLAINED=y
configs/sama5d4_xplained_nandflash_defconfig
浏览文件 @
c956662c
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_SAMA5D4_XPLAINED=y
configs/sama5d4_xplained_spiflash_defconfig
浏览文件 @
c956662c
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_SAMA5D4_XPLAINED=y
configs/sama5d4ek_mmc_defconfig
浏览文件 @
c956662c
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_SAMA5D4EK=y
configs/sama5d4ek_nandflash_defconfig
浏览文件 @
c956662c
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_SAMA5D4EK=y
configs/sama5d4ek_spiflash_defconfig
浏览文件 @
c956662c
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_SAMA5D4EK=y
drivers/mtd/nand/atmel_nand.c
浏览文件 @
c956662c
...
...
@@ -44,6 +44,7 @@ struct atmel_nand_host {
u8
pmecc_corr_cap
;
u16
pmecc_sector_size
;
u32
pmecc_index_table_offset
;
u32
pmecc_version
;
int
pmecc_bytes_per_sector
;
int
pmecc_sector_number
;
...
...
@@ -486,6 +487,10 @@ static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
int
i
,
err_nbr
,
eccbytes
;
uint8_t
*
buf_pos
;
/* SAMA5D4 PMECC IP can correct errors for all 0xff page */
if
(
host
->
pmecc_version
>=
PMECC_VERSION_SAMA5D4
)
goto
normal_check
;
eccbytes
=
nand_chip
->
ecc
.
bytes
;
for
(
i
=
0
;
i
<
eccbytes
;
i
++
)
if
(
ecc
[
i
]
!=
0xff
)
...
...
@@ -961,6 +966,10 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
nand
->
ecc
.
write_page
=
atmel_nand_pmecc_write_page
;
nand
->
ecc
.
strength
=
cap
;
/* Check the PMECC ip version */
host
->
pmecc_version
=
pmecc_readl
(
host
->
pmerrloc
,
version
);
dev_dbg
(
host
->
dev
,
"PMECC IP version is: %x
\n
"
,
host
->
pmecc_version
);
atmel_pmecc_core_init
(
mtd
);
return
0
;
...
...
drivers/mtd/nand/atmel_nand_ecc.h
浏览文件 @
c956662c
...
...
@@ -123,6 +123,20 @@ struct pmecc_errloc_regs {
u32
sigma
[
25
];
/* 0x28-0x88 Error Location Sigma Registers */
u32
el
[
24
];
/* 0x8C-0xE8 Error Location Registers */
u32
reserved1
[
5
];
/* 0xEC-0xFC Reserved */
/*
* 0x100-0x1F8:
* Reserved for AT91SAM9X5, AT91SAM9N12.
* HSMC registers for SAMA5D3, SAMA5D4.
*/
u32
reserved2
[
63
];
/*
* 0x1FC:
* PMECC version for AT91SAM9X5, AT91SAM9N12.
* HSMC version for SAMA5D3, SAMA5D4. Can refer as PMECC version.
*/
u32
version
;
};
/* For Error Location Configuration Register */
...
...
@@ -137,6 +151,12 @@ struct pmecc_errloc_regs {
#define PMERRLOC_ERR_NUM_MASK (0x1f << 8)
#define PMERRLOC_CALC_DONE (1 << 0)
/* PMECC IP version */
#define PMECC_VERSION_SAMA5D4 0x113
#define PMECC_VERSION_SAMA5D3 0x112
#define PMECC_VERSION_AT91SAM9N12 0x102
#define PMECC_VERSION_AT91SAM9X5 0x101
/* Galois field dimension */
#define PMECC_GF_DIMENSION_13 13
#define PMECC_GF_DIMENSION_14 14
...
...
drivers/video/atmel_lcdfb.c
浏览文件 @
c956662c
...
...
@@ -21,7 +21,7 @@
#define ATMEL_LCDC_GUARD_TIME 1
#endif
#if defined(CONFIG_AT91SAM9263)
|| defined(CONFIG_AT91CAP9)
#if defined(CONFIG_AT91SAM9263)
#define ATMEL_LCDC_FIFO_SIZE 2048
#else
#define ATMEL_LCDC_FIFO_SIZE 512
...
...
drivers/watchdog/at91sam9_wdt.c
浏览文件 @
c956662c
...
...
@@ -30,7 +30,11 @@
#define ticks_to_ms(t) (((t + 1) * 1000) >> 8)
/* Hardware timeout in seconds */
#if !defined(CONFIG_AT91_HW_WDT_TIMEOUT)
#define WDT_HW_TIMEOUT 2
#else
#define WDT_HW_TIMEOUT CONFIG_AT91_HW_WDT_TIMEOUT
#endif
/*
* Set the watchdog time interval in 1/256Hz (write-once)
...
...
include/configs/at91sam9260ek.h
浏览文件 @
c956662c
...
...
@@ -90,7 +90,6 @@
#define CONFIG_CMD_PING 1
#define CONFIG_CMD_DHCP 1
#define CONFIG_CMD_NAND 1
#define CONFIG_CMD_MMC
#define CONFIG_CMD_FAT
#define CONFIG_CMD_USB 1
...
...
@@ -133,14 +132,17 @@
# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9260EK
#endif
/* DataFlash */
#ifndef CONFIG_AT91SAM9G20EK_2MMC
/* DataFlash */
#define CONFIG_ATMEL_DATAFLASH_SPI
#define CONFIG_HAS_DATAFLASH 1
#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000
/* CS0 */
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000
/* CS1 */
#define AT91_SPI_CLK 15000000
#else
/* Enable MMC. The MCCK is conflicted with DataFlash */
#define CONFIG_CMD_MMC
#endif
#ifdef CONFIG_AT91SAM9G20EK
...
...
include/configs/at91sam9x5ek.h
浏览文件 @
c956662c
...
...
@@ -203,11 +203,12 @@
"bootm 0x22000000"
#else
/* CONFIG_SYS_USE_MMC */
/* bootstrap + u-boot + env + linux in mmc */
#define CONFIG_ENV_IS_IN_MMC
/* For FAT system, most cases it should be in the reserved sector */
#define CONFIG_ENV_OFFSET 0x2000
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_IS_IN_FAT
#define CONFIG_FAT_WRITE
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_FILE "uboot.env"
#define FAT_ENV_DEVICE_AND_PART "0"
#define CONFIG_ENV_SIZE 0x4000
#endif
#ifdef CONFIG_SYS_USE_MMC
...
...
include/configs/sama5d3_xplained.h
浏览文件 @
c956662c
...
...
@@ -169,13 +169,14 @@
"bootz 0x22000000 - 0x21000000"
#elif CONFIG_SYS_USE_MMC
/* bootstrap + u-boot + env in sd card */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET 0x2000
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_IS_IN_FAT
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_FILE "uboot.env"
#define FAT_ENV_DEVICE_AND_PART "0"
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d3_xplained.dtb; " \
"fatload mmc 0:1 0x22000000 zImage; " \
"bootz 0x22000000 - 0x21000000"
#define CONFIG_SYS_MMC_ENV_DEV 0
#else
#define CONFIG_ENV_IS_NOWHERE
#endif
...
...
include/configs/sama5d3xek.h
浏览文件 @
c956662c
...
...
@@ -191,6 +191,7 @@
#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
#endif
#define CONFIG_SYS_LOAD_ADDR 0x22000000
/* load address */
...
...
@@ -215,13 +216,14 @@
"bootm 0x22000000 - 0x21000000"
#elif CONFIG_SYS_USE_MMC
/* bootstrap + u-boot + env in sd card */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET 0x2000
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_IS_IN_FAT
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_FILE "uboot.env"
#define FAT_ENV_DEVICE_AND_PART "0"
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 dtb; " \
"fatload mmc 0:1 0x22000000 uImage; " \
"bootm 0x22000000 - 0x21000000"
#define CONFIG_SYS_MMC_ENV_DEV 0
#else
#define CONFIG_ENV_IS_NOWHERE
#endif
...
...
include/configs/sama5d4_xplained.h
浏览文件 @
c956662c
...
...
@@ -20,7 +20,9 @@
#define CONFIG_ARCH_CPU_INIT
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO
...
...
@@ -66,8 +68,12 @@
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR 0x210000
#else
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
#define CONFIG_SYS_LOAD_ADDR 0x22000000
/* load address */
...
...
@@ -221,4 +227,54 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x200000
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#elif CONFIG_SYS_USE_NANDFLASH
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_PMECC_CAP 8
#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_OOBSIZE 224
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#elif CONFIG_SYS_USE_SERIALFLASH
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#endif
#endif
include/configs/sama5d4ek.h
浏览文件 @
c956662c
...
...
@@ -20,7 +20,9 @@
#define CONFIG_ARCH_CPU_INIT
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO
...
...
@@ -66,8 +68,12 @@
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR 0x210000
#else
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
#define CONFIG_SYS_LOAD_ADDR 0x22000000
/* load address */
...
...
@@ -219,4 +225,54 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x200000
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#elif CONFIG_SYS_USE_NANDFLASH
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_PMECC_CAP 8
#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_OOBSIZE 224
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#elif CONFIG_SYS_USE_SERIALFLASH
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#endif
#endif
include/configs/taurus.h
浏览文件 @
c956662c
...
...
@@ -21,9 +21,6 @@
*/
#include <asm/hardware.h>
#define MACH_TYPE_TAURUS 2067
#define MACH_TYPE_AXM 2068
#define CONFIG_SYS_GENERIC_BOARD
#if defined(CONFIG_SPL_BUILD)
...
...
@@ -121,6 +118,12 @@
#define CONFIG_RMII
#define CONFIG_AT91_WANTS_COMMON_PHY
#define CONFIG_AT91SAM9_WATCHDOG
#if !defined(CONFIG_SPL_BUILD)
/* Enable the watchdog */
#define CONFIG_HW_WATCHDOG
#endif
/* USB */
#if defined(CONFIG_BOARD_TAURUS)
#define CONFIG_USB_ATMEL
...
...
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