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体验新版 GitCode,发现更多精彩内容 >>
提交
c6d88630
编写于
3月 26, 2012
作者:
A
Alison Wang
提交者:
jason
9月 20, 2012
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
ColdFire: Clean up checkpatch warnings for MCF523x
Signed-off-by:
N
Alison Wang
<
b18965@freescale.com
>
上级
aa0d99fc
变更
5
隐藏空白更改
内联
并排
Showing
5 changed file
with
120 addition
and
103 deletion
+120
-103
arch/m68k/cpu/mcf523x/cpu.c
arch/m68k/cpu/mcf523x/cpu.c
+18
-15
arch/m68k/cpu/mcf523x/cpu_init.c
arch/m68k/cpu/mcf523x/cpu_init.c
+64
-58
arch/m68k/cpu/mcf523x/interrupts.c
arch/m68k/cpu/mcf523x/interrupts.c
+8
-7
arch/m68k/cpu/mcf523x/speed.c
arch/m68k/cpu/mcf523x/speed.c
+6
-4
board/freescale/m5235evb/m5235evb.c
board/freescale/m5235evb/m5235evb.c
+24
-19
未找到文件。
arch/m68k/cpu/mcf523x/cpu.c
浏览文件 @
c6d88630
...
...
@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2007
, 2012
Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
...
...
@@ -31,28 +31,29 @@
#include <netdev.h>
#include <asm/immap.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR
;
int
do_reset
(
cmd_tbl_t
*
cmdtp
,
int
flag
,
int
argc
,
char
*
const
argv
[])
{
volatile
ccm_t
*
ccm
=
(
ccm_t
*
)
MMAP_CCM
;
ccm_t
*
ccm
=
(
ccm_t
*
)
MMAP_CCM
;
ccm
->
rcr
=
CCM_RCR_SOFTRST
;
out_8
(
&
ccm
->
rcr
,
CCM_RCR_SOFTRST
)
;
/* we don't return! */
return
0
;
}
;
}
int
checkcpu
(
void
)
{
volatile
ccm_t
*
ccm
=
(
ccm_t
*
)
MMAP_CCM
;
ccm_t
*
ccm
=
(
ccm_t
*
)
MMAP_CCM
;
u16
msk
;
u16
id
=
0
;
u8
ver
;
puts
(
"CPU: "
);
msk
=
(
ccm
->
cir
>>
6
);
ver
=
(
ccm
->
cir
&
0x003f
);
msk
=
(
in_be16
(
&
ccm
->
cir
)
>>
6
);
ver
=
(
in_be16
(
&
ccm
->
cir
)
&
0x003f
);
switch
(
msk
)
{
case
0x31
:
id
=
5235
;
...
...
@@ -76,19 +77,21 @@ int checkcpu(void)
/* Called by macro WATCHDOG_RESET */
void
watchdog_reset
(
void
)
{
volatile
wdog_t
*
wdp
=
(
wdog_t
*
)
(
MMAP_WDOG
);
wdog_t
*
wdp
=
(
wdog_t
*
)
(
MMAP_WDOG
);
wdp
->
sr
=
0x5555
;
/* Count register */
/* Count register */
out_be16
(
&
wdp
->
sr
,
0x5555
);
asm
(
"nop"
);
wdp
->
sr
=
0xAAAA
;
/* Count register */
out_be16
(
&
wdp
->
sr
,
0xaaaa
);
}
int
watchdog_disable
(
void
)
{
volatile
wdog_t
*
wdp
=
(
wdog_t
*
)
(
MMAP_WDOG
);
wdog_t
*
wdp
=
(
wdog_t
*
)
(
MMAP_WDOG
);
/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
wdp
->
cr
|=
WTM_WCR_HALTED
;
/* halted watchdog timer */
/* halted watchdog timer */
setbits_be16
(
&
wdp
->
cr
,
WTM_WCR_HALTED
);
puts
(
"WATCHDOG:disabled
\n
"
);
return
(
0
);
...
...
@@ -96,15 +99,15 @@ int watchdog_disable(void)
int
watchdog_init
(
void
)
{
volatile
wdog_t
*
wdp
=
(
wdog_t
*
)
(
MMAP_WDOG
);
wdog_t
*
wdp
=
(
wdog_t
*
)
(
MMAP_WDOG
);
u32
wdog_module
=
0
;
/* set timeout and enable watchdog */
wdog_module
=
((
CONFIG_SYS_CLK
/
CONFIG_SYS_HZ
)
*
CONFIG_WATCHDOG_TIMEOUT
);
wdog_module
|=
(
wdog_module
/
8192
);
wdp
->
mr
=
wdog_module
;
out_be16
(
&
wdp
->
mr
,
wdog_module
)
;
wdp
->
cr
=
WTM_WCR_EN
;
out_be16
(
&
wdp
->
cr
,
WTM_WCR_EN
)
;
puts
(
"WATCHDOG:enabled
\n
"
);
return
(
0
);
...
...
arch/m68k/cpu/mcf523x/cpu_init.c
浏览文件 @
c6d88630
...
...
@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2007 Freescale Semiconductor, Inc.
* (C) Copyright 2007
, 2012
Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
...
...
@@ -28,6 +28,7 @@
#include <common.h>
#include <watchdog.h>
#include <asm/immap.h>
#include <asm/io.h>
#if defined(CONFIG_CMD_NET)
#include <config.h>
...
...
@@ -44,74 +45,74 @@
*/
void
cpu_init_f
(
void
)
{
volatile
gpio_t
*
gpio
=
(
gpio_t
*
)
MMAP_GPIO
;
volatile
fbcs_t
*
fbcs
=
(
fbcs_t
*
)
MMAP_FBCS
;
volatile
wdog_t
*
wdog
=
(
wdog_t
*
)
MMAP_WDOG
;
volatile
scm_t
*
scm
=
(
scm_t
*
)
MMAP_SCM
;
gpio_t
*
gpio
=
(
gpio_t
*
)
MMAP_GPIO
;
fbcs_t
*
fbcs
=
(
fbcs_t
*
)
MMAP_FBCS
;
wdog_t
*
wdog
=
(
wdog_t
*
)
MMAP_WDOG
;
scm_t
*
scm
=
(
scm_t
*
)
MMAP_SCM
;
/* watchdog is enabled by default - disable the watchdog */
#ifndef CONFIG_WATCHDOG
wdog
->
cr
=
0
;
out_be16
(
&
wdog
->
cr
,
0
)
;
#endif
scm
->
rambar
=
(
CONFIG_SYS_INIT_RAM_ADDR
|
SCM_RAMBAR_BDE
);
out_be32
(
&
scm
->
rambar
,
CONFIG_SYS_INIT_RAM_ADDR
|
SCM_RAMBAR_BDE
);
/* Port configuration */
gpio
->
par_cs
=
0
;
out_8
(
&
gpio
->
par_cs
,
0
)
;
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
fbcs
->
csar0
=
CONFIG_SYS_CS0_BASE
;
fbcs
->
cscr0
=
CONFIG_SYS_CS0_CTRL
;
fbcs
->
csmr0
=
CONFIG_SYS_CS0_MASK
;
out_be32
(
&
fbcs
->
csar0
,
CONFIG_SYS_CS0_BASE
)
;
out_be32
(
&
fbcs
->
cscr0
,
CONFIG_SYS_CS0_CTRL
)
;
out_be32
(
&
fbcs
->
csmr0
,
CONFIG_SYS_CS0_MASK
)
;
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
gpio
->
par_cs
|=
GPIO_PAR_CS_CS1
;
fbcs
->
csar1
=
CONFIG_SYS_CS1_BASE
;
fbcs
->
cscr1
=
CONFIG_SYS_CS1_CTRL
;
fbcs
->
csmr1
=
CONFIG_SYS_CS1_MASK
;
setbits_8
(
&
gpio
->
par_cs
,
GPIO_PAR_CS_CS1
)
;
out_be32
(
&
fbcs
->
csar1
,
CONFIG_SYS_CS1_BASE
)
;
out_be32
(
&
fbcs
->
cscr1
,
CONFIG_SYS_CS1_CTRL
)
;
out_be32
(
&
fbcs
->
csmr1
,
CONFIG_SYS_CS1_MASK
)
;
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
gpio
->
par_cs
|=
GPIO_PAR_CS_CS2
;
fbcs
->
csar2
=
CONFIG_SYS_CS2_BASE
;
fbcs
->
cscr2
=
CONFIG_SYS_CS2_CTRL
;
fbcs
->
csmr2
=
CONFIG_SYS_CS2_MASK
;
setbits_8
(
&
gpio
->
par_cs
,
GPIO_PAR_CS_CS2
)
;
out_be32
(
&
fbcs
->
csar2
,
CONFIG_SYS_CS2_BASE
)
;
out_be32
(
&
fbcs
->
cscr2
,
CONFIG_SYS_CS2_CTRL
)
;
out_be32
(
&
fbcs
->
csmr2
,
CONFIG_SYS_CS2_MASK
)
;
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
gpio
->
par_cs
|=
GPIO_PAR_CS_CS3
;
fbcs
->
csar3
=
CONFIG_SYS_CS3_BASE
;
fbcs
->
cscr3
=
CONFIG_SYS_CS3_CTRL
;
fbcs
->
csmr3
=
CONFIG_SYS_CS3_MASK
;
setbits_8
(
&
gpio
->
par_cs
,
GPIO_PAR_CS_CS3
)
;
out_be32
(
&
fbcs
->
csar3
,
CONFIG_SYS_CS3_BASE
)
;
out_be32
(
&
fbcs
->
cscr3
,
CONFIG_SYS_CS3_CTRL
)
;
out_be32
(
&
fbcs
->
csmr3
,
CONFIG_SYS_CS3_MASK
)
;
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
gpio
->
par_cs
|=
GPIO_PAR_CS_CS4
;
fbcs
->
csar4
=
CONFIG_SYS_CS4_BASE
;
fbcs
->
cscr4
=
CONFIG_SYS_CS4_CTRL
;
fbcs
->
csmr4
=
CONFIG_SYS_CS4_MASK
;
setbits_8
(
&
gpio
->
par_cs
,
GPIO_PAR_CS_CS4
)
;
out_be32
(
&
fbcs
->
csar4
,
CONFIG_SYS_CS4_BASE
)
;
out_be32
(
&
fbcs
->
cscr4
,
CONFIG_SYS_CS4_CTRL
)
;
out_be32
(
&
fbcs
->
csmr4
,
CONFIG_SYS_CS4_MASK
)
;
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
gpio
->
par_cs
|=
GPIO_PAR_CS_CS5
;
fbcs
->
csar5
=
CONFIG_SYS_CS5_BASE
;
fbcs
->
cscr5
=
CONFIG_SYS_CS5_CTRL
;
fbcs
->
csmr5
=
CONFIG_SYS_CS5_MASK
;
setbits_8
(
&
gpio
->
par_cs
,
GPIO_PAR_CS_CS5
)
;
out_be32
(
&
fbcs
->
csar5
,
CONFIG_SYS_CS5_BASE
)
;
out_be32
(
&
fbcs
->
cscr5
,
CONFIG_SYS_CS5_CTRL
)
;
out_be32
(
&
fbcs
->
csmr5
,
CONFIG_SYS_CS5_MASK
)
;
#endif
#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
gpio
->
par_cs
|=
GPIO_PAR_CS_CS6
;
fbcs
->
csar6
=
CONFIG_SYS_CS6_BASE
;
fbcs
->
cscr6
=
CONFIG_SYS_CS6_CTRL
;
fbcs
->
csmr6
=
CONFIG_SYS_CS6_MASK
;
setbits_8
(
&
gpio
->
par_cs
,
GPIO_PAR_CS_CS6
)
;
out_be32
(
&
fbcs
->
csar6
,
CONFIG_SYS_CS6_BASE
)
;
out_be32
(
&
fbcs
->
cscr6
,
CONFIG_SYS_CS6_CTRL
)
;
out_be32
(
&
fbcs
->
csmr6
,
CONFIG_SYS_CS6_MASK
)
;
#endif
#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
gpio
->
par_cs
|=
GPIO_PAR_CS_CS7
;
fbcs
->
csar7
=
CONFIG_SYS_CS7_BASE
;
fbcs
->
cscr7
=
CONFIG_SYS_CS7_CTRL
;
fbcs
->
csmr7
=
CONFIG_SYS_CS7_MASK
;
setbits_8
(
&
gpio
->
par_cs
,
GPIO_PAR_CS_CS7
)
;
out_be32
(
&
fbcs
->
csar7
,
CONFIG_SYS_CS7_BASE
)
;
out_be32
(
&
fbcs
->
cscr7
,
CONFIG_SYS_CS7_CTRL
)
;
out_be32
(
&
fbcs
->
csmr7
,
CONFIG_SYS_CS7_MASK
)
;
#endif
#ifdef CONFIG_FSL_I2C
...
...
@@ -132,29 +133,33 @@ int cpu_init_r(void)
void
uart_port_conf
(
int
port
)
{
volatile
gpio_t
*
gpio
=
(
gpio_t
*
)
MMAP_GPIO
;
gpio_t
*
gpio
=
(
gpio_t
*
)
MMAP_GPIO
;
/* Setup Ports: */
switch
(
port
)
{
case
0
:
gpio
->
par_uart
&=
~
(
GPIO_PAR_UART_U0RXD
|
GPIO_PAR_UART_U0TXD
);
gpio
->
par_uart
|=
(
GPIO_PAR_UART_U0RXD
|
GPIO_PAR_UART_U0TXD
);
clrbits_be16
(
&
gpio
->
par_uart
,
GPIO_PAR_UART_U0RXD
|
GPIO_PAR_UART_U0TXD
);
setbits_be16
(
&
gpio
->
par_uart
,
GPIO_PAR_UART_U0RXD
|
GPIO_PAR_UART_U0TXD
);
break
;
case
1
:
gpio
->
par_uart
&=
~
(
GPIO_PAR_UART_U1RXD_MASK
|
GPIO_PAR_UART_U1TXD_MASK
);
gpio
->
par_uart
|=
(
GPIO_PAR_UART_U1RXD_U1RXD
|
GPIO_PAR_UART_U1TXD_U1TXD
);
clrbits_be16
(
&
gpio
->
par_uart
,
GPIO_PAR_UART_U1RXD_MASK
|
GPIO_PAR_UART_U1TXD_MASK
);
setbits_be16
(
&
gpio
->
par_uart
,
GPIO_PAR_UART_U1RXD_U1RXD
|
GPIO_PAR_UART_U1TXD_U1TXD
);
break
;
case
2
:
#ifdef CONFIG_SYS_UART2_PRI_GPIO
gpio
->
par_uart
&=
~
(
GPIO_PAR_UART_U2RXD
|
GPIO_PAR_UART_U2TXD
);
gpio
->
par_uart
|=
(
GPIO_PAR_UART_U2RXD
|
GPIO_PAR_UART_U2TXD
);
clrbits_be16
(
&
gpio
->
par_uart
,
GPIO_PAR_UART_U2RXD
|
GPIO_PAR_UART_U2TXD
);
setbits_be16
(
&
gpio
->
par_uart
,
GPIO_PAR_UART_U2RXD
|
GPIO_PAR_UART_U2TXD
);
#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
gpio
->
feci2c
&=
~
(
GPIO_PAR_FECI2C_EMDC_MASK
|
GPIO_PAR_FECI2C_EMDIO_MASK
);
gpio
->
feci2c
|=
(
GPIO_PAR_FECI2C_EMDC_U2TXD
|
GPIO_PAR_FECI2C_EMDIO_U2RXD
);
clrbits_8
(
&
gpio
->
par_feci2c
,
GPIO_PAR_FECI2C_EMDC_MASK
|
GPIO_PAR_FECI2C_EMDIO_MASK
);
setbits_8
(
&
gpio
->
par_feci2c
,
GPIO_PAR_FECI2C_EMDC_U2TXD
|
GPIO_PAR_FECI2C_EMDIO_U2RXD
);
#endif
break
;
}
...
...
@@ -163,15 +168,16 @@ void uart_port_conf(int port)
#if defined(CONFIG_CMD_NET)
int
fecpin_setclear
(
struct
eth_device
*
dev
,
int
setclear
)
{
volatile
gpio_t
*
gpio
=
(
gpio_t
*
)
MMAP_GPIO
;
gpio_t
*
gpio
=
(
gpio_t
*
)
MMAP_GPIO
;
if
(
setclear
)
{
gpio
->
par_feci2c
|=
(
GPIO_PAR_FECI2C_EMDC_FECEMDC
|
GPIO_PAR_FECI2C_EMDIO_FECEMDIO
);
setbits_8
(
&
gpio
->
par_feci2c
,
GPIO_PAR_FECI2C_EMDC_FECEMDC
|
GPIO_PAR_FECI2C_EMDIO_FECEMDIO
);
}
else
{
gpio
->
par_feci2c
&=
~
(
GPIO_PAR_FECI2C_EMDC_MASK
|
GPIO_PAR_FECI2C_EMDIO_MASK
);
clrbits_8
(
&
gpio
->
par_feci2c
,
GPIO_PAR_FECI2C_EMDC_MASK
|
GPIO_PAR_FECI2C_EMDIO_MASK
);
}
return
0
;
...
...
arch/m68k/cpu/mcf523x/interrupts.c
浏览文件 @
c6d88630
/*
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2007
, 2012
Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
...
...
@@ -25,13 +25,14 @@
/* CPU specific interrupt routine */
#include <common.h>
#include <asm/immap.h>
#include <asm/io.h>
int
interrupt_init
(
void
)
{
volatile
int0_t
*
intp
=
(
int0_t
*
)
(
CONFIG_SYS_INTR_BASE
);
int0_t
*
intp
=
(
int0_t
*
)
(
CONFIG_SYS_INTR_BASE
);
/* Make sure all interrupts are disabled */
intp
->
imrl0
|=
0x1
;
setbits_be32
(
&
intp
->
imrl0
,
0x1
)
;
enable_interrupts
();
return
0
;
...
...
@@ -40,10 +41,10 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void
dtimer_intr_setup
(
void
)
{
volatile
int0_t
*
intp
=
(
int0_t
*
)
(
CONFIG_SYS_INTR_BASE
);
int0_t
*
intp
=
(
int0_t
*
)
(
CONFIG_SYS_INTR_BASE
);
intp
->
icr0
[
CONFIG_SYS_TMRINTR_NO
]
=
CONFIG_SYS_TMRINTR_PRI
;
intp
->
imrl0
&=
~
INTC_IPRL_INT0
;
intp
->
imrl0
&=
~
CONFIG_SYS_TMRINTR_MASK
;
out_8
(
&
intp
->
icr0
[
CONFIG_SYS_TMRINTR_NO
],
CONFIG_SYS_TMRINTR_PRI
)
;
clrbits_be32
(
&
intp
->
imrl0
,
INTC_IPRL_INT0
)
;
clrbits_be32
(
&
intp
->
imrl0
,
CONFIG_SYS_TMRINTR_MASK
)
;
}
#endif
arch/m68k/cpu/mcf523x/speed.c
浏览文件 @
c6d88630
...
...
@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2007
, 2012
Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
...
...
@@ -29,6 +29,7 @@
#include <asm/processor.h>
#include <asm/immap.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR
;
/*
...
...
@@ -36,11 +37,12 @@ DECLARE_GLOBAL_DATA_PTR;
*/
int
get_clocks
(
void
)
{
volatile
pll_t
*
pll
=
(
volatile
pll_t
*
)(
MMAP_PLL
);
pll_t
*
pll
=
(
pll_t
*
)(
MMAP_PLL
);
pll
->
syncr
=
PLL_SYNCR_MFD
(
1
);
out_be32
(
&
pll
->
syncr
,
PLL_SYNCR_MFD
(
1
)
);
while
(
!
(
pll
->
synsr
&
PLL_SYNSR_LOCK
));
while
(
!
(
in_be32
(
&
pll
->
synsr
)
&
PLL_SYNSR_LOCK
))
;
gd
->
bus_clk
=
CONFIG_SYS_CLK
;
gd
->
cpu_clk
=
(
gd
->
bus_clk
*
2
);
...
...
board/freescale/m5235evb/m5235evb.c
浏览文件 @
c6d88630
...
...
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2007
, 2012
Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
...
...
@@ -27,6 +27,7 @@
#include <config.h>
#include <common.h>
#include <asm/immap.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR
;
...
...
@@ -39,8 +40,8 @@ int checkboard(void)
phys_size_t
initdram
(
int
board_type
)
{
volatile
sdram_t
*
sdram
=
(
volatile
sdram_t
*
)(
MMAP_SDRAM
);
volatile
gpio_t
*
gpio
=
(
volatile
gpio_t
*
)(
MMAP_GPIO
);
sdram_t
*
sdram
=
(
sdram_t
*
)(
MMAP_SDRAM
);
gpio_t
*
gpio
=
(
gpio_t
*
)(
MMAP_GPIO
);
u32
dramsize
,
i
,
dramclk
;
/*
...
...
@@ -48,14 +49,15 @@ phys_size_t initdram(int board_type)
* the port-size of SDRAM. In this case it is necessary to enable
* Data[15:0] on Port Address/Data.
*/
gpio
->
par_ad
=
GPIO_PAR_AD_ADDR23
|
GPIO_PAR_AD_ADDR22
|
GPIO_PAR_AD_ADDR21
|
GPIO_PAR_AD_DATAL
;
out_8
(
&
gpio
->
par_ad
,
GPIO_PAR_AD_ADDR23
|
GPIO_PAR_AD_ADDR22
|
GPIO_PAR_AD_ADDR21
|
GPIO_PAR_AD_DATAL
)
;
/* Initialize PAR to enable SDRAM signals */
gpio
->
par_sdram
=
GPIO_PAR_SDRAM_SDWE
|
GPIO_PAR_SDRAM_SCAS
|
GPIO_PAR_SDRAM_SRAS
|
GPIO_PAR_SDRAM_SCKE
|
GPIO_PAR_SDRAM_SDCS
(
3
);
out_8
(
&
gpio
->
par_sdram
,
GPIO_PAR_SDRAM_SDWE
|
GPIO_PAR_SDRAM_SCAS
|
GPIO_PAR_SDRAM_SRAS
|
GPIO_PAR_SDRAM_SCKE
|
GPIO_PAR_SDRAM_SDCS
(
3
));
dramsize
=
CONFIG_SYS_SDRAM_SIZE
*
0x100000
;
for
(
i
=
0x13
;
i
<
0x20
;
i
++
)
{
...
...
@@ -64,25 +66,28 @@ phys_size_t initdram(int board_type)
}
i
--
;
if
(
!
(
sdram
->
dacr0
&
SDRAMC_DARCn_RE
))
{
if
(
!
(
in_be32
(
&
sdram
->
dacr0
)
&
SDRAMC_DARCn_RE
))
{
dramclk
=
gd
->
bus_clk
/
(
CONFIG_SYS_HZ
*
CONFIG_SYS_HZ
);
/* Initialize DRAM Control Register: DCR */
sdram
->
dcr
=
SDRAMC_DCR_RTIM_9CLKS
|
SDRAMC_DCR_RTIM_6CLKS
|
SDRAMC_DCR_RC
((
15
*
dramclk
)
>>
4
);
out_be16
(
&
sdram
->
dcr
,
SDRAMC_DCR_RTIM_9CLKS
|
SDRAMC_DCR_RTIM_6CLKS
|
SDRAMC_DCR_RC
((
15
*
dramclk
)
>>
4
));
/* Initialize DACR0 */
sdram
->
dacr0
=
SDRAMC_DARCn_BA
(
CONFIG_SYS_SDRAM_BASE
)
|
SDRAMC_DARCn_CASL_C1
|
SDRAMC_DARCn_CBM_CMD20
|
SDRAMC_DARCn_PS_32
;
out_be32
(
&
sdram
->
dacr0
,
SDRAMC_DARCn_BA
(
CONFIG_SYS_SDRAM_BASE
)
|
SDRAMC_DARCn_CASL_C1
|
SDRAMC_DARCn_CBM_CMD20
|
SDRAMC_DARCn_PS_32
);
asm
(
"nop"
);
/* Initialize DMR0 */
sdram
->
dmr0
=
((
dramsize
-
1
)
&
0xFFFC0000
)
|
SDRAMC_DMRn_V
;
out_be32
(
&
sdram
->
dmr0
,
((
dramsize
-
1
)
&
0xFFFC0000
)
|
SDRAMC_DMRn_V
);
asm
(
"nop"
);
/* Set IP (bit 3) in DACR */
s
dram
->
dacr0
|=
SDRAMC_DARCn_IP
;
s
etbits_be32
(
&
sdram
->
dacr0
,
SDRAMC_DARCn_IP
)
;
/* Wait 30ns to allow banks to precharge */
for
(
i
=
0
;
i
<
5
;
i
++
)
{
...
...
@@ -93,7 +98,7 @@ phys_size_t initdram(int board_type)
*
(
u32
*
)
(
CONFIG_SYS_SDRAM_BASE
)
=
0xA5A59696
;
/* Set RE (bit 15) in DACR */
s
dram
->
dacr0
|=
SDRAMC_DARCn_RE
;
s
etbits_be32
(
&
sdram
->
dacr0
,
SDRAMC_DARCn_RE
)
;
/* Wait for at least 8 auto refresh cycles to occur */
for
(
i
=
0
;
i
<
0x2000
;
i
++
)
{
...
...
@@ -101,7 +106,7 @@ phys_size_t initdram(int board_type)
}
/* Finish the configuration by issuing the MRS. */
s
dram
->
dacr0
|=
SDRAMC_DARCn_IMRS
;
s
etbits_be32
(
&
sdram
->
dacr0
,
SDRAMC_DARCn_IMRS
)
;
asm
(
"nop"
);
/* Write to the SDRAM Mode Register */
...
...
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