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体验新版 GitCode,发现更多精彩内容 >>
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c14d4b00
编写于
10月 12, 2016
作者:
T
Tom Rini
浏览文件
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浏览文件
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差异文件
Merge branch 'master' of
http://git.denx.de/u-boot-sunxi
上级
3c594d34
55cdcdaa
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
45 addition
and
23 deletion
+45
-23
arch/arm/mach-sunxi/dram_sun8i_h3.c
arch/arm/mach-sunxi/dram_sun8i_h3.c
+43
-21
configs/A20-OLinuXino-Lime2_defconfig
configs/A20-OLinuXino-Lime2_defconfig
+1
-1
configs/A20-OLinuXino-Lime_defconfig
configs/A20-OLinuXino-Lime_defconfig
+1
-1
未找到文件。
arch/arm/mach-sunxi/dram_sun8i_h3.c
浏览文件 @
c14d4b00
...
...
@@ -217,35 +217,57 @@ static void mctl_zq_calibration(struct dram_para *para)
struct
sunxi_mctl_ctl_reg
*
const
mctl_ctl
=
(
struct
sunxi_mctl_ctl_reg
*
)
SUNXI_DRAM_CTL0_BASE
;
i
nt
i
;
u16
zq_val
[
6
];
u8
val
;
i
f
((
readl
(
SUNXI_SRAMC_BASE
+
0x24
)
&
0xff
)
==
0
&&
(
readl
(
SUNXI_SRAMC_BASE
+
0xf0
)
&
0x1
)
==
0
)
{
u32
reg_
val
;
writel
(
0x0a0a0a0a
,
&
mctl_ctl
->
zqdr
[
2
]);
for
(
i
=
0
;
i
<
6
;
i
++
)
{
u8
zq
=
(
CONFIG_DRAM_ZQ
>>
(
i
*
4
))
&
0xf
;
writel
((
zq
<<
20
)
|
(
zq
<<
16
)
|
(
zq
<<
12
)
|
(
zq
<<
8
)
|
(
zq
<<
4
)
|
(
zq
<<
0
),
&
mctl_ctl
->
zqcr
);
clrsetbits_le32
(
&
mctl_ctl
->
zqcr
,
0xffff
,
CONFIG_DRAM_ZQ
&
0xffff
);
writel
(
PIR_CLRSR
,
&
mctl_ctl
->
pir
);
mctl_phy_init
(
PIR_ZCAL
);
zq_val
[
i
]
=
readl
(
&
mctl_ctl
->
zqdr
[
0
])
&
0xff
;
writel
(
REPEAT_BYTE
(
zq_val
[
i
]),
&
mctl_ctl
->
zqdr
[
2
]);
reg_val
=
readl
(
&
mctl_ctl
->
zqdr
[
0
]);
reg_val
&=
(
0x1f
<<
16
)
|
(
0x1f
<<
0
);
reg_val
|=
reg_val
<<
8
;
writel
(
reg_val
,
&
mctl_ctl
->
zqdr
[
0
]);
writel
(
PIR_CLRSR
,
&
mctl_ctl
->
pir
);
mctl_phy_init
(
PIR_ZCAL
);
reg_val
=
readl
(
&
mctl_ctl
->
zqdr
[
1
]);
reg_val
&=
(
0x1f
<<
16
)
|
(
0x1f
<<
0
);
reg_val
|=
reg_val
<<
8
;
writel
(
reg_val
,
&
mctl_ctl
->
zqdr
[
1
]);
writel
(
reg_val
,
&
mctl_ctl
->
zqdr
[
2
]);
}
else
{
int
i
;
u16
zq_val
[
6
];
u8
val
;
val
=
readl
(
&
mctl_ctl
->
zqdr
[
0
])
>>
24
;
zq_val
[
i
]
|=
bin_to_mgray
(
mgray_to_bin
(
val
)
-
1
)
<<
8
;
}
writel
(
0x0a0a0a0a
,
&
mctl_ctl
->
zqdr
[
2
]);
for
(
i
=
0
;
i
<
6
;
i
++
)
{
u8
zq
=
(
CONFIG_DRAM_ZQ
>>
(
i
*
4
))
&
0xf
;
writel
((
zq
<<
20
)
|
(
zq
<<
16
)
|
(
zq
<<
12
)
|
(
zq
<<
8
)
|
(
zq
<<
4
)
|
(
zq
<<
0
),
&
mctl_ctl
->
zqcr
);
writel
((
zq_val
[
1
]
<<
16
)
|
zq_val
[
0
],
&
mctl_ctl
->
zqdr
[
0
]);
writel
((
zq_val
[
3
]
<<
16
)
|
zq_val
[
2
],
&
mctl_ctl
->
zqdr
[
1
]);
writel
((
zq_val
[
5
]
<<
16
)
|
zq_val
[
4
],
&
mctl_ctl
->
zqdr
[
2
]);
writel
(
PIR_CLRSR
,
&
mctl_ctl
->
pir
);
mctl_phy_init
(
PIR_ZCAL
);
zq_val
[
i
]
=
readl
(
&
mctl_ctl
->
zqdr
[
0
])
&
0xff
;
writel
(
REPEAT_BYTE
(
zq_val
[
i
]),
&
mctl_ctl
->
zqdr
[
2
]);
writel
(
PIR_CLRSR
,
&
mctl_ctl
->
pir
);
mctl_phy_init
(
PIR_ZCAL
);
val
=
readl
(
&
mctl_ctl
->
zqdr
[
0
])
>>
24
;
zq_val
[
i
]
|=
bin_to_mgray
(
mgray_to_bin
(
val
)
-
1
)
<<
8
;
}
writel
((
zq_val
[
1
]
<<
16
)
|
zq_val
[
0
],
&
mctl_ctl
->
zqdr
[
0
]);
writel
((
zq_val
[
3
]
<<
16
)
|
zq_val
[
2
],
&
mctl_ctl
->
zqdr
[
1
]);
writel
((
zq_val
[
5
]
<<
16
)
|
zq_val
[
4
],
&
mctl_ctl
->
zqdr
[
2
]);
}
}
static
void
mctl_set_cr
(
struct
dram_para
*
para
)
...
...
configs/A20-OLinuXino-Lime2_defconfig
浏览文件 @
c14d4b00
...
...
@@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=
480
CONFIG_DRAM_CLK=
384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
...
...
configs/A20-OLinuXino-Lime_defconfig
浏览文件 @
c14d4b00
...
...
@@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=
480
CONFIG_DRAM_CLK=
384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
...
...
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