提交 bf9e3b38 编写于 作者: W wdenk

* Some code cleanup

* Patch by Josef Baumgartner, 10 Feb 2004:
  Fixes for Coldfire port

* Patch by Brad Kemp, 11 Feb 2004:
  Fix CFI flash driver problems
上级 a2d18bb7
......@@ -2,9 +2,17 @@
Changes since U-Boot 1.0.1:
======================================================================
* Some code cleanup
* Patch by Josef Baumgartner, 10 Feb 2004:
Fixes for Coldfire port
* Patch by Brad Kemp, 11 Feb 2004:
Fix CFI flash driver problems
* Make sure to use a bus clock divider of 2 only when running TQM8xxM
modules at CPU clock frequencies above 66 MHz.
* Optimize flash programming speed for LWMON (by another 100% :-)
* Patch by Jian Zhang, 3 Feb 2004:
......
......@@ -833,10 +833,10 @@ ZPC1900_config: unconfig
#########################################################################
M5272C3_config : unconfig
@./mkconfig $(@:_config=) m68k coldfire m5272c3
@./mkconfig $(@:_config=) m68k mcf52x2 m5272c3
M5282EVB_config : unconfig
@./mkconfig $(@:_config=) m68k coldfire m5282evb
@./mkconfig $(@:_config=) m68k mcf52x2 m5282evb
#########################################################################
## MPC85xx Systems
......
此差异已折叠。
......@@ -9,49 +9,49 @@
typedef struct NS16550 *NS16550_t;
const NS16550_t COM_PORTS[] = { (NS16550_t) ((CFG_EUMB_ADDR) + 0x4500), (NS16550_t) ((CFG_EUMB_ADDR) + 0x4600)};
const NS16550_t COM_PORTS[] =
{ (NS16550_t) ((CFG_EUMB_ADDR) + 0x4500),
(NS16550_t) ((CFG_EUMB_ADDR) + 0x4600) };
volatile struct NS16550 *
NS16550_init(int chan, int baud_divisor)
volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
{
volatile struct NS16550 *com_port;
com_port = (struct NS16550 *) COM_PORTS[chan];
com_port->ier = 0x00;
com_port->lcr = LCR_BKSE; /* Access baud rate */
com_port->dll = baud_divisor & 0xff; /* 9600 baud */
com_port->dlm = (baud_divisor >> 8) & 0xff;
com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
com_port->mcr = MCR_RTS; /* RTS/DTR */
com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */
return (com_port);
volatile struct NS16550 *com_port;
com_port = (struct NS16550 *) COM_PORTS[chan];
com_port->ier = 0x00;
com_port->lcr = LCR_BKSE; /* Access baud rate */
com_port->dll = baud_divisor & 0xff; /* 9600 baud */
com_port->dlm = (baud_divisor >> 8) & 0xff;
com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
com_port->mcr = MCR_RTS; /* RTS/DTR */
com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */
return (com_port);
}
void
NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor)
void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
{
com_port->ier = 0x00;
com_port->lcr = LCR_BKSE; /* Access baud rate */
com_port->dll = baud_divisor & 0xff; /* 9600 baud */
com_port->dlm = (baud_divisor >> 8) & 0xff;
com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
com_port->mcr = MCR_RTS; /* RTS/DTR */
com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */
com_port->ier = 0x00;
com_port->lcr = LCR_BKSE; /* Access baud rate */
com_port->dll = baud_divisor & 0xff; /* 9600 baud */
com_port->dlm = (baud_divisor >> 8) & 0xff;
com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
com_port->mcr = MCR_RTS; /* RTS/DTR */
com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */
}
void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c)
void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
{
while ((com_port->lsr & LSR_THRE) == 0) ;
com_port->thr = c;
while ((com_port->lsr & LSR_THRE) == 0);
com_port->thr = c;
}
unsigned char
NS16550_getc(volatile struct NS16550 *com_port)
unsigned char NS16550_getc (volatile struct NS16550 *com_port)
{
while ((com_port->lsr & LSR_DR) == 0) ;
return (com_port->rbr);
while ((com_port->lsr & LSR_DR) == 0);
return (com_port->rbr);
}
int NS16550_tstc(volatile struct NS16550 *com_port)
int NS16550_tstc (volatile struct NS16550 *com_port)
{
return ((com_port->lsr & LSR_DR) != 0);
return ((com_port->lsr & LSR_DR) != 0);
}
......@@ -12,20 +12,19 @@
*/
struct NS16550
{
unsigned char rbrthrdlb; /* 0 */
unsigned char ierdmb; /* 1 */
unsigned char iirfcrafr; /* 2 */
unsigned char lcr; /* 3 */
unsigned char mcr; /* 4 */
unsigned char lsr; /* 5 */
unsigned char msr; /* 6 */
unsigned char scr; /* 7 */
unsigned char reserved[2]; /* 8 & 9 */
unsigned char dsr; /* 10 */
unsigned char dcr; /* 11 */
};
struct NS16550 {
unsigned char rbrthrdlb; /* 0 */
unsigned char ierdmb; /* 1 */
unsigned char iirfcrafr; /* 2 */
unsigned char lcr; /* 3 */
unsigned char mcr; /* 4 */
unsigned char lsr; /* 5 */
unsigned char msr; /* 6 */
unsigned char scr; /* 7 */
unsigned char reserved[2]; /* 8 & 9 */
unsigned char dsr; /* 10 */
unsigned char dcr; /* 11 */
};
#define rbr rbrthrdlb
......@@ -37,44 +36,44 @@ struct NS16550
#define fcr iirfcrafr
#define afr iirfcrafr
#define FCR_FIFO_EN 0x01 /*fifo enable*/
#define FCR_RXSR 0x02 /*reciever soft reset*/
#define FCR_TXSR 0x04 /*transmitter soft reset*/
#define FCR_DMS 0x08 /* DMA Mode Select */
#define FCR_FIFO_EN 0x01 /*fifo enable */
#define FCR_RXSR 0x02 /*reciever soft reset */
#define FCR_TXSR 0x04 /*transmitter soft reset */
#define FCR_DMS 0x08 /* DMA Mode Select */
#define MCR_RTS 0x02 /* Readyu to Send */
#define MCR_RTS 0x02 /* Readyu to Send */
#define MCR_LOOP 0x10 /* Local loopback mode enable */
/* #define MCR_DTR 0x01 noton 8245 duart */
/* #define MCR_DMA_EN 0x04 noton 8245 duart */
/* #define MCR_TX_DFR 0x08 noton 8245 duart */
#define LCR_WLS_MSK 0x03 /* character length slect mask*/
#define LCR_WLS_5 0x00 /* 5 bit character length */
#define LCR_WLS_6 0x01 /* 6 bit character length */
#define LCR_WLS_7 0x02 /* 7 bit character length */
#define LCR_WLS_8 0x03 /* 8 bit character length */
#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
#define LCR_PEN 0x08 /* Parity eneble*/
#define LCR_EPS 0x10 /* Even Parity Select*/
#define LCR_STKP 0x20 /* Stick Parity*/
#define LCR_SBRK 0x40 /* Set Break*/
#define LCR_BKSE 0x80 /* Bank select enable - aka DLAB on 8245 */
#define LCR_WLS_MSK 0x03 /* character length slect mask */
#define LCR_WLS_5 0x00 /* 5 bit character length */
#define LCR_WLS_6 0x01 /* 6 bit character length */
#define LCR_WLS_7 0x02 /* 7 bit character length */
#define LCR_WLS_8 0x03 /* 8 bit character length */
#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
#define LCR_PEN 0x08 /* Parity eneble */
#define LCR_EPS 0x10 /* Even Parity Select */
#define LCR_STKP 0x20 /* Stick Parity */
#define LCR_SBRK 0x40 /* Set Break */
#define LCR_BKSE 0x80 /* Bank select enable - aka DLAB on 8245 */
#define LSR_DR 0x01 /* Data ready */
#define LSR_OE 0x02 /* Overrun */
#define LSR_PE 0x04 /* Parity error */
#define LSR_FE 0x08 /* Framing error */
#define LSR_BI 0x10 /* Break */
#define LSR_THRE 0x20 /* Xmit holding register empty */
#define LSR_TEMT 0x40 /* Xmitter empty */
#define LSR_ERR 0x80 /* Error */
#define LSR_DR 0x01 /* Data ready */
#define LSR_OE 0x02 /* Overrun */
#define LSR_PE 0x04 /* Parity error */
#define LSR_FE 0x08 /* Framing error */
#define LSR_BI 0x10 /* Break */
#define LSR_THRE 0x20 /* Xmit holding register empty */
#define LSR_TEMT 0x40 /* Xmitter empty */
#define LSR_ERR 0x80 /* Error */
/* useful defaults for LCR*/
#define LCR_8N1 0x03
volatile struct NS16550 * NS16550_init(int chan, int baud_divisor);
void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c);
unsigned char NS16550_getc(volatile struct NS16550 *com_port);
int NS16550_tstc(volatile struct NS16550 *com_port);
void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor);
volatile struct NS16550 *NS16550_init (int chan, int baud_divisor);
void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c);
unsigned char NS16550_getc (volatile struct NS16550 *com_port);
int NS16550_tstc (volatile struct NS16550 *com_port);
void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor);
......@@ -43,152 +43,166 @@
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { 0, 0, 0, 0, 0, 0 },
/* PA30 */ { 0, 0, 0, 0, 0, 0 },
/* PA29 */ { 0, 0, 0, 0, 0, 0 },
/* PA28 */ { 0, 0, 0, 0, 0, 0 },
/* PA27 */ { 0, 0, 0, 0, 0, 0 },
/* PA26 */ { 0, 0, 0, 0, 0, 0 },
/* PA25 */ { 0, 0, 0, 0, 0, 0 },
/* PA24 */ { 0, 0, 0, 0, 0, 0 },
/* PA23 */ { 0, 0, 0, 0, 0, 0 },
/* PA22 */ { 0, 0, 0, 0, 0, 0 },
/* PA21 */ { 0, 0, 0, 0, 0, 0 },
/* PA20 */ { 0, 0, 0, 0, 0, 0 },
/* PA19 */ { 0, 0, 0, 0, 0, 0 },
/* PA18 */ { 0, 0, 0, 0, 0, 0 },
/* PA17 */ { 0, 0, 0, 0, 0, 0 },
/* PA16 */ { 0, 0, 0, 0, 0, 0 },
/* PA15 */ { 0, 0, 0, 0, 0, 0 },
/* PA14 */ { 0, 0, 0, 0, 0, 0 },
/* PA13 */ { 0, 0, 0, 0, 0, 0 },
/* PA12 */ { 0, 0, 0, 0, 0, 0 },
/* PA11 */ { 0, 0, 0, 0, 0, 0 },
/* PA10 */ { 0, 0, 0, 0, 0, 0 },
/* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
/* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
/* PA7 */ { 0, 0, 0, 0, 0, 0 },
/* PA6 */ { 0, 0, 0, 0, 0, 0 },
/* PA5 */ { 0, 0, 0, 0, 0, 0 },
/* PA4 */ { 0, 0, 0, 0, 0, 0 },
/* PA3 */ { 0, 0, 0, 0, 0, 0 },
/* PA2 */ { 0, 0, 0, 0, 0, 0 },
/* PA1 */ { 0, 0, 0, 0, 0, 0 },
/* PA0 */ { 0, 0, 0, 0, 0, 0 }
},
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 0, 0, 0, 0, 0, 0 },
/* PB30 */ { 0, 0, 0, 0, 0, 0 },
/* PB29 */ { 0, 0, 0, 0, 0, 0 },
/* PB28 */ { 0, 0, 0, 0, 0, 0 },
/* PB27 */ { 0, 0, 0, 0, 0, 0 },
/* PB26 */ { 0, 0, 0, 0, 0, 0 },
/* PB25 */ { 0, 0, 0, 0, 0, 0 },
/* PB24 */ { 0, 0, 0, 0, 0, 0 },
/* PB23 */ { 0, 0, 0, 0, 0, 0 },
/* PB22 */ { 0, 0, 0, 0, 0, 0 },
/* PB21 */ { 0, 0, 0, 0, 0, 0 },
/* PB20 */ { 0, 0, 0, 0, 0, 0 },
/* PB19 */ { 0, 0, 0, 0, 0, 0 },
/* PB18 */ { 0, 0, 0, 0, 0, 0 },
/* PB17 */ { 0, 0, 0, 0, 0, 0 },
/* PB16 */ { 0, 0, 0, 0, 0, 0 },
/* PB15 */ { 0, 0, 0, 0, 0, 0 },
/* PB14 */ { 0, 0, 0, 0, 0, 0 },
/* PB13 */ { 0, 0, 0, 0, 0, 0 },
/* PB12 */ { 0, 0, 0, 0, 0, 0 },
/* PB11 */ { 0, 0, 0, 0, 0, 0 },
/* PB10 */ { 0, 0, 0, 0, 0, 0 },
/* PB9 */ { 0, 0, 0, 0, 0, 0 },
/* PB8 */ { 0, 0, 0, 0, 0, 0 },
/* PB7 */ { 0, 0, 0, 0, 0, 0 },
/* PB6 */ { 0, 0, 0, 0, 0, 0 },
/* PB5 */ { 0, 0, 0, 0, 0, 0 },
/* PB4 */ { 0, 0, 0, 0, 0, 0 },
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
},
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 0, 0, 0 },
/* PC30 */ { 0, 0, 0, 0, 0, 0 },
/* PC29 */ { 0, 0, 0, 0, 0, 0 },
/* PC28 */ { 0, 0, 0, 0, 0, 0 },
/* PC27 */ { 0, 0, 0, 0, 0, 0 },
/* PC26 */ { 0, 0, 0, 0, 0, 0 },
/* PC25 */ { 0, 0, 0, 0, 0, 0 },
/* PC24 */ { 0, 0, 0, 0, 0, 0 },
/* PC23 */ { 0, 0, 0, 0, 0, 0 },
/* PC22 */ { 0, 0, 0, 0, 0, 0 },
/* PC21 */ { 0, 0, 0, 0, 0, 0 },
/* PC20 */ { 0, 0, 0, 0, 0, 0 },
/* PC19 */ { 0, 0, 0, 0, 0, 0 },
/* PC18 */ { 0, 0, 0, 0, 0, 0 },
/* PC17 */ { 0, 0, 0, 0, 0, 0 },
/* PC16 */ { 0, 0, 0, 0, 0, 0 },
/* PC15 */ { 0, 0, 0, 0, 0, 0 },
/* PC14 */ { 0, 0, 0, 0, 0, 0 },
/* PC13 */ { 0, 0, 0, 0, 0, 0 },
/* PC12 */ { 0, 0, 0, 0, 0, 0 },
/* PC11 */ { 0, 0, 0, 0, 0, 0 },
/* PC10 */ { 0, 0, 0, 0, 0, 0 },
/* PC9 */ { 0, 0, 0, 0, 0, 0 },
/* PC8 */ { 0, 0, 0, 0, 0, 0 },
/* PC7 */ { 0, 0, 0, 0, 0, 0 },
/* PC6 */ { 0, 0, 0, 0, 0, 0 },
/* PC5 */ { 0, 0, 0, 0, 0, 0 },
/* PC4 */ { 0, 0, 0, 0, 0, 0 },
/* PC3 */ { 0, 0, 0, 0, 0, 0 },
/* PC2 */ { 0, 0, 0, 0, 0, 0 },
/* PC1 */ { 0, 0, 0, 0, 0, 0 },
/* PC0 */ { 0, 0, 0, 0, 0, 0 }
},
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ { 0, 0, 0, 0, 0, 0 },
/* PD30 */ { 0, 0, 0, 0, 0, 0 },
/* PD29 */ { 0, 0, 0, 0, 0, 0 },
/* PD28 */ { 0, 0, 0, 0, 0, 0 },
/* PD27 */ { 0, 0, 0, 0, 0, 0 },
/* PD26 */ { 0, 0, 0, 0, 0, 0 },
/* PD25 */ { 0, 0, 0, 0, 0, 0 },
/* PD24 */ { 0, 0, 0, 0, 0, 0 },
/* PD23 */ { 0, 0, 0, 0, 0, 0 },
/* PD22 */ { 0, 0, 0, 0, 0, 0 },
/* PD21 */ { 0, 0, 0, 0, 0, 0 },
/* PD20 */ { 0, 0, 0, 0, 0, 0 },
/* PD19 */ { 0, 0, 0, 0, 0, 0 },
/* PD18 */ { 0, 0, 0, 0, 0, 0 },
/* PD17 */ { 0, 0, 0, 0, 0, 0 },
/* PD16 */ { 0, 0, 0, 0, 0, 0 },
/* PD15 */ { 1, 1, 1, 0, 0, 0 }, /* I2C SDA */
/* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C SCL */
/* PD13 */ { 0, 0, 0, 0, 0, 0 },
/* PD12 */ { 0, 0, 0, 0, 0, 0 },
/* PD11 */ { 0, 0, 0, 0, 0, 0 },
/* PD10 */ { 0, 0, 0, 0, 0, 0 },
/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
/* PD7 */ { 0, 0, 0, 0, 0, 0 },
/* PD6 */ { 0, 0, 0, 0, 0, 0 },
/* PD5 */ { 0, 0, 0, 0, 0, 0 },
/* PD4 */ { 0, 0, 0, 0, 0, 0 },
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
}
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ {0, 0, 0, 0, 0, 0},
/* PA30 */ {0, 0, 0, 0, 0, 0},
/* PA29 */ {0, 0, 0, 0, 0, 0},
/* PA28 */ {0, 0, 0, 0, 0, 0},
/* PA27 */ {0, 0, 0, 0, 0, 0},
/* PA26 */ {0, 0, 0, 0, 0, 0},
/* PA25 */ {0, 0, 0, 0, 0, 0},
/* PA24 */ {0, 0, 0, 0, 0, 0},
/* PA23 */ {0, 0, 0, 0, 0, 0},
/* PA22 */ {0, 0, 0, 0, 0, 0},
/* PA21 */ {0, 0, 0, 0, 0, 0},
/* PA20 */ {0, 0, 0, 0, 0, 0},
/* PA19 */ {0, 0, 0, 0, 0, 0},
/* PA18 */ {0, 0, 0, 0, 0, 0},
/* PA17 */ {0, 0, 0, 0, 0, 0},
/* PA16 */ {0, 0, 0, 0, 0, 0},
/* PA15 */ {0, 0, 0, 0, 0, 0},
/* PA14 */ {0, 0, 0, 0, 0, 0},
/* PA13 */ {0, 0, 0, 0, 0, 0},
/* PA12 */ {0, 0, 0, 0, 0, 0},
/* PA11 */ {0, 0, 0, 0, 0, 0},
/* PA10 */ {0, 0, 0, 0, 0, 0},
/* PA9 */ {1, 1, 0, 1, 0, 0},
/* SMC2 TXD */
/* PA8 */ {1, 1, 0, 0, 0, 0},
/* SMC2 RXD */
/* PA7 */ {0, 0, 0, 0, 0, 0},
/* PA6 */ {0, 0, 0, 0, 0, 0},
/* PA5 */ {0, 0, 0, 0, 0, 0},
/* PA4 */ {0, 0, 0, 0, 0, 0},
/* PA3 */ {0, 0, 0, 0, 0, 0},
/* PA2 */ {0, 0, 0, 0, 0, 0},
/* PA1 */ {0, 0, 0, 0, 0, 0},
/* PA0 */ {0, 0, 0, 0, 0, 0}
},
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ {0, 0, 0, 0, 0, 0},
/* PB30 */ {0, 0, 0, 0, 0, 0},
/* PB29 */ {0, 0, 0, 0, 0, 0},
/* PB28 */ {0, 0, 0, 0, 0, 0},
/* PB27 */ {0, 0, 0, 0, 0, 0},
/* PB26 */ {0, 0, 0, 0, 0, 0},
/* PB25 */ {0, 0, 0, 0, 0, 0},
/* PB24 */ {0, 0, 0, 0, 0, 0},
/* PB23 */ {0, 0, 0, 0, 0, 0},
/* PB22 */ {0, 0, 0, 0, 0, 0},
/* PB21 */ {0, 0, 0, 0, 0, 0},
/* PB20 */ {0, 0, 0, 0, 0, 0},
/* PB19 */ {0, 0, 0, 0, 0, 0},
/* PB18 */ {0, 0, 0, 0, 0, 0},
/* PB17 */ {0, 0, 0, 0, 0, 0},
/* PB16 */ {0, 0, 0, 0, 0, 0},
/* PB15 */ {0, 0, 0, 0, 0, 0},
/* PB14 */ {0, 0, 0, 0, 0, 0},
/* PB13 */ {0, 0, 0, 0, 0, 0},
/* PB12 */ {0, 0, 0, 0, 0, 0},
/* PB11 */ {0, 0, 0, 0, 0, 0},
/* PB10 */ {0, 0, 0, 0, 0, 0},
/* PB9 */ {0, 0, 0, 0, 0, 0},
/* PB8 */ {0, 0, 0, 0, 0, 0},
/* PB7 */ {0, 0, 0, 0, 0, 0},
/* PB6 */ {0, 0, 0, 0, 0, 0},
/* PB5 */ {0, 0, 0, 0, 0, 0},
/* PB4 */ {0, 0, 0, 0, 0, 0},
/* PB3 */ {0, 0, 0, 0, 0, 0},
/* pin doesn't exist */
/* PB2 */ {0, 0, 0, 0, 0, 0},
/* pin doesn't exist */
/* PB1 */ {0, 0, 0, 0, 0, 0},
/* pin doesn't exist */
/* PB0 */ {0, 0, 0, 0, 0, 0}
/* pin doesn't exist */
},
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ {0, 0, 0, 0, 0, 0},
/* PC30 */ {0, 0, 0, 0, 0, 0},
/* PC29 */ {0, 0, 0, 0, 0, 0},
/* PC28 */ {0, 0, 0, 0, 0, 0},
/* PC27 */ {0, 0, 0, 0, 0, 0},
/* PC26 */ {0, 0, 0, 0, 0, 0},
/* PC25 */ {0, 0, 0, 0, 0, 0},
/* PC24 */ {0, 0, 0, 0, 0, 0},
/* PC23 */ {0, 0, 0, 0, 0, 0},
/* PC22 */ {0, 0, 0, 0, 0, 0},
/* PC21 */ {0, 0, 0, 0, 0, 0},
/* PC20 */ {0, 0, 0, 0, 0, 0},
/* PC19 */ {0, 0, 0, 0, 0, 0},
/* PC18 */ {0, 0, 0, 0, 0, 0},
/* PC17 */ {0, 0, 0, 0, 0, 0},
/* PC16 */ {0, 0, 0, 0, 0, 0},
/* PC15 */ {0, 0, 0, 0, 0, 0},
/* PC14 */ {0, 0, 0, 0, 0, 0},
/* PC13 */ {0, 0, 0, 0, 0, 0},
/* PC12 */ {0, 0, 0, 0, 0, 0},
/* PC11 */ {0, 0, 0, 0, 0, 0},
/* PC10 */ {0, 0, 0, 0, 0, 0},
/* PC9 */ {0, 0, 0, 0, 0, 0},
/* PC8 */ {0, 0, 0, 0, 0, 0},
/* PC7 */ {0, 0, 0, 0, 0, 0},
/* PC6 */ {0, 0, 0, 0, 0, 0},
/* PC5 */ {0, 0, 0, 0, 0, 0},
/* PC4 */ {0, 0, 0, 0, 0, 0},
/* PC3 */ {0, 0, 0, 0, 0, 0},
/* PC2 */ {0, 0, 0, 0, 0, 0},
/* PC1 */ {0, 0, 0, 0, 0, 0},
/* PC0 */ {0, 0, 0, 0, 0, 0}
},
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ {0, 0, 0, 0, 0, 0},
/* PD30 */ {0, 0, 0, 0, 0, 0},
/* PD29 */ {0, 0, 0, 0, 0, 0},
/* PD28 */ {0, 0, 0, 0, 0, 0},
/* PD27 */ {0, 0, 0, 0, 0, 0},
/* PD26 */ {0, 0, 0, 0, 0, 0},
/* PD25 */ {0, 0, 0, 0, 0, 0},
/* PD24 */ {0, 0, 0, 0, 0, 0},
/* PD23 */ {0, 0, 0, 0, 0, 0},
/* PD22 */ {0, 0, 0, 0, 0, 0},
/* PD21 */ {0, 0, 0, 0, 0, 0},
/* PD20 */ {0, 0, 0, 0, 0, 0},
/* PD19 */ {0, 0, 0, 0, 0, 0},
/* PD18 */ {0, 0, 0, 0, 0, 0},
/* PD17 */ {0, 0, 0, 0, 0, 0},
/* PD16 */ {0, 0, 0, 0, 0, 0},
/* PD15 */ {1, 1, 1, 0, 0, 0},
/* I2C SDA */
/* PD14 */ {1, 1, 1, 0, 0, 0},
/* I2C SCL */
/* PD13 */ {0, 0, 0, 0, 0, 0},
/* PD12 */ {0, 0, 0, 0, 0, 0},
/* PD11 */ {0, 0, 0, 0, 0, 0},
/* PD10 */ {0, 0, 0, 0, 0, 0},
/* PD9 */ {1, 1, 0, 1, 0, 0},
/* SMC1 TXD */
/* PD8 */ {1, 1, 0, 0, 0, 0},
/* SMC1 RXD */
/* PD7 */ {0, 0, 0, 0, 0, 0},
/* PD6 */ {0, 0, 0, 0, 0, 0},
/* PD5 */ {0, 0, 0, 0, 0, 0},
/* PD4 */ {0, 0, 0, 0, 0, 0},
/* PD3 */ {0, 0, 0, 0, 0, 0},
/* pin doesn't exist */
/* PD2 */ {0, 0, 0, 0, 0, 0},
/* pin doesn't exist */
/* PD1 */ {0, 0, 0, 0, 0, 0},
/* pin doesn't exist */
/* PD0 */ {0, 0, 0, 0, 0, 0}
/* pin doesn't exist */
}
};
#endif /* CONFIG_8260 */
#endif /* CONFIG_8260 */
/* ------------------------------------------------------------------------- */
......@@ -196,12 +210,11 @@ const iop_conf_t iop_conf_tab[4][32] = {
* Check Board Identity:
*/
int
checkboard(void)
int checkboard (void)
{
puts ("Board: Cogent " COGENT_MOTHERBOARD " motherboard with a "
COGENT_CPU_MODULE " CPU Module\n");
return (0);
puts ("Board: Cogent " COGENT_MOTHERBOARD " motherboard with a "
COGENT_CPU_MODULE " CPU Module\n");
return (0);
}
/* ------------------------------------------------------------------------- */
......@@ -213,46 +226,44 @@ checkboard(void)
int misc_init_f (void)
{
printf ("DIPSW: ");
dipsw_init();
return (0);
printf ("DIPSW: ");
dipsw_init ();
return (0);
}
/* ------------------------------------------------------------------------- */
long int
initdram(int board_type)
long int initdram (int board_type)
{
#if CONFIG_CMA111
return (32L * 1024L * 1024L);
return (32L * 1024L * 1024L);
#else
unsigned char dipsw_val;
int dual, size0, size1;
long int memsize;
dipsw_val = dipsw_cooked();
dual = dipsw_val & 0x01;
size0 = (dipsw_val & 0x08) >> 3;
size1 = (dipsw_val & 0x04) >> 2;
if (size0)
if (size1)
memsize = 16L * 1024L * 1024L;
else
memsize = 1L * 1024L * 1024L;
else
if (size1)
memsize = 4L * 1024L * 1024L;
unsigned char dipsw_val;
int dual, size0, size1;
long int memsize;
dipsw_val = dipsw_cooked ();
dual = dipsw_val & 0x01;
size0 = (dipsw_val & 0x08) >> 3;
size1 = (dipsw_val & 0x04) >> 2;
if (size0)
if (size1)
memsize = 16L * 1024L * 1024L;
else
memsize = 1L * 1024L * 1024L;
else if (size1)
memsize = 4L * 1024L * 1024L;
else {
printf("[Illegal dip switch settings - assuming 16Mbyte SIMMs] ");
memsize = 16L * 1024L * 1024L; /* shouldn't happen - guess 16M */
printf ("[Illegal dip switch settings - assuming 16Mbyte SIMMs] ");
memsize = 16L * 1024L * 1024L; /* shouldn't happen - guess 16M */
}
if (dual)
memsize *= 2L;
if (dual)
memsize *= 2L;
return (memsize);
return (memsize);
#endif
}
......@@ -265,21 +276,21 @@ initdram(int board_type)
int misc_init_r (void)
{
printf ("LCD: ");
lcd_init();
printf ("LCD: ");
lcd_init ();
#if 0
printf ("RTC: ");
rtc_init();
printf ("RTC: ");
rtc_init ();
printf ("PAR: ");
par_init();
printf ("PAR: ");
par_init ();
printf ("KBM: ");
kbm_init();
printf ("KBM: ");
kbm_init ();
printf ("PCI: ");
pci_init();
printf ("PCI: ");
pci_init ();
#endif
return (0);
return (0);
}
......@@ -37,17 +37,18 @@
*/
ulong bab7xx_get_bus_freq (void)
{
/*
* The GPIO Port 1 on BAB7xx reflects the bus speed.
*/
volatile struct GPIO *gpio = (struct GPIO *)(CFG_ISA_IO + CFG_NS87308_GPIO_BASE);
/*
* The GPIO Port 1 on BAB7xx reflects the bus speed.
*/
volatile struct GPIO *gpio =
(struct GPIO *) (CFG_ISA_IO + CFG_NS87308_GPIO_BASE);
unsigned char data = gpio->dta1;
unsigned char data = gpio->dta1;
if (data & 0x02)
return 66666666;
if (data & 0x02)
return 66666666;
return 83333333;
return 83333333;
}
/*---------------------------------------------------------------------------*/
......@@ -57,24 +58,26 @@ ulong bab7xx_get_bus_freq (void)
*/
ulong bab7xx_get_gclk_freq (void)
{
static const int pllratio_to_factor[] = {
00, 75, 70, 00, 20, 65, 100, 45, 30, 55, 40, 50, 80, 60, 35, 00,
};
static const int pllratio_to_factor[] = {
00, 75, 70, 00, 20, 65, 100, 45, 30, 55, 40, 50, 80, 60, 35,
00,
};
return pllratio_to_factor[get_hid1 () >> 28] * (bab7xx_get_bus_freq() / 10);
return pllratio_to_factor[get_hid1 () >> 28] *
(bab7xx_get_bus_freq () / 10);
}
/*----------------------------------------------------------------------------*/
int checkcpu (void)
{
uint pvr = get_pvr();
uint pvr = get_pvr ();
printf ("MPC7xx V%d.%d",(pvr >> 8) & 0xFF, pvr & 0xFF);
printf (" at %ld / %ld MHz\n", bab7xx_get_gclk_freq()/1000000,
bab7xx_get_bus_freq()/1000000);
printf ("MPC7xx V%d.%d", (pvr >> 8) & 0xFF, pvr & 0xFF);
printf (" at %ld / %ld MHz\n", bab7xx_get_gclk_freq () / 1000000,
bab7xx_get_bus_freq () / 1000000);
return (0);
return (0);
}
/* ------------------------------------------------------------------------- */
......@@ -82,20 +85,20 @@ int checkcpu (void)
int checkboard (void)
{
#ifdef CFG_ADDRESS_MAP_A
puts ("Board: ELTEC BAB7xx PReP\n");
puts ("Board: ELTEC BAB7xx PReP\n");
#else
puts ("Board: ELTEC BAB7xx CHRP\n");
puts ("Board: ELTEC BAB7xx CHRP\n");
#endif
return (0);
return (0);
}
/* ------------------------------------------------------------------------- */
int checkflash (void)
{
/* TODO: XXX XXX XXX */
printf ("2 MB ## Test not implemented yet ##\n");
return (0);
/* TODO: XXX XXX XXX */
printf ("2 MB ## Test not implemented yet ##\n");
return (0);
}
/* ------------------------------------------------------------------------- */
......@@ -103,77 +106,75 @@ int checkflash (void)
static unsigned int mpc106_read_cfg_dword (unsigned int reg)
{
unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC);
unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC);
out32r(MPC106_REG_ADDR, reg_addr);
out32r (MPC106_REG_ADDR, reg_addr);
return (in32r(MPC106_REG_DATA | (reg & 0x3)));
return (in32r (MPC106_REG_DATA | (reg & 0x3)));
}
/* ------------------------------------------------------------------------- */
long int dram_size (int board_type)
{
/* No actual initialisation to do - done when setting up
* PICRs MCCRs ME/SARs etc in ram_init.S.
*/
/* No actual initialisation to do - done when setting up
* PICRs MCCRs ME/SARs etc in ram_init.S.
*/
register unsigned long i, msar1, mear1, memSize;
register unsigned long i, msar1, mear1, memSize;
#if defined(CFG_MEMTEST)
register unsigned long reg;
register unsigned long reg;
printf("Testing DRAM\n");
printf ("Testing DRAM\n");
/* write each mem addr with it's address */
for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg+=4)
*reg = reg;
/* write each mem addr with it's address */
for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4)
*reg = reg;
for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg+=4)
{
if (*reg != reg)
return -1;
}
for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) {
if (*reg != reg)
return -1;
}
#endif
/*
* Since MPC106 memory controller chip has already been set to
* control all memory, just read and interpret its memory boundery register.
*/
memSize = 0;
msar1 = mpc106_read_cfg_dword(MPC106_MSAR1);
mear1 = mpc106_read_cfg_dword(MPC106_MEAR1);
i = mpc106_read_cfg_dword(MPC106_MBER) & 0xf;
do
{
if (i & 0x01) /* is bank enabled ? */
memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1;
msar1 >>= 8;
mear1 >>= 8;
i >>= 1;
} while (i);
return (memSize * 0x100000);
/*
* Since MPC106 memory controller chip has already been set to
* control all memory, just read and interpret its memory boundery register.
*/
memSize = 0;
msar1 = mpc106_read_cfg_dword (MPC106_MSAR1);
mear1 = mpc106_read_cfg_dword (MPC106_MEAR1);
i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf;
do {
if (i & 0x01) /* is bank enabled ? */
memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1;
msar1 >>= 8;
mear1 >>= 8;
i >>= 1;
} while (i);
return (memSize * 0x100000);
}
/* ------------------------------------------------------------------------- */
long int initdram(int board_type)
long int initdram (int board_type)
{
return dram_size(board_type);
return dram_size (board_type);
}
/* ------------------------------------------------------------------------- */
void after_reloc (ulong dest_addr)
{
DECLARE_GLOBAL_DATA_PTR;
DECLARE_GLOBAL_DATA_PTR;
/*
* Jump to the main U-Boot board init code
*/
board_init_r((gd_t *)gd, dest_addr);
/*
* Jump to the main U-Boot board init code
*/
board_init_r ((gd_t *) gd, dest_addr);
}
/* ------------------------------------------------------------------------- */
......@@ -182,14 +183,13 @@ void after_reloc (ulong dest_addr)
* do_reset is done here because in this case it is board specific, since the
* 7xx CPUs can only be reset by external HW (the RTC in this case).
*/
void
do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
void do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
#if defined(CONFIG_RTC_MK48T59)
/* trigger watchdog immediately */
rtc_set_watchdog(1, RTC_WD_RB_16TH);
/* trigger watchdog immediately */
rtc_set_watchdog (1, RTC_WD_RB_16TH);
#else
#error "You must define the macro CONFIG_RTC_MK48T59."
#error "You must define the macro CONFIG_RTC_MK48T59."
#endif
}
......@@ -200,16 +200,16 @@ do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
* Since the 7xx CPUs don't have an internal watchdog, this function is
* board specific. We use the RTC here.
*/
void watchdog_reset(void)
void watchdog_reset (void)
{
#if defined(CONFIG_RTC_MK48T59)
/* we use a 32 sec watchdog timer */
rtc_set_watchdog(8, RTC_WD_RB_4);
/* we use a 32 sec watchdog timer */
rtc_set_watchdog (8, RTC_WD_RB_4);
#else
#error "You must define the macro CONFIG_RTC_MK48T59."
#error "You must define the macro CONFIG_RTC_MK48T59."
#endif
}
#endif /* CONFIG_WATCHDOG */
#endif /* CONFIG_WATCHDOG */
/* ------------------------------------------------------------------------- */
......@@ -218,29 +218,28 @@ extern GraphicDevice smi;
void video_get_info_str (int line_number, char *info)
{
/* init video info strings for graphic console */
switch (line_number)
{
case 1:
sprintf (info," MPC7xx V%d.%d at %ld / %ld MHz",
(get_pvr() >> 8) & 0xFF,
get_pvr() & 0xFF,
bab7xx_get_gclk_freq()/1000000,
bab7xx_get_bus_freq()/1000000);
/* init video info strings for graphic console */
switch (line_number) {
case 1:
sprintf (info, " MPC7xx V%d.%d at %ld / %ld MHz",
(get_pvr () >> 8) & 0xFF,
get_pvr () & 0xFF,
bab7xx_get_gclk_freq () / 1000000,
bab7xx_get_bus_freq () / 1000000);
return;
case 2:
sprintf (info,
" ELTEC BAB7xx with %ld MB DRAM and %ld MB FLASH",
dram_size (0) / 0x100000, flash_init () / 0x100000);
return;
case 3:
sprintf (info, " %s", smi.modeIdent);
return;
}
/* no more info lines */
*info = 0;
return;
case 2:
sprintf (info, " ELTEC BAB7xx with %ld MB DRAM and %ld MB FLASH",
dram_size(0)/0x100000,
flash_init()/0x100000);
return;
case 3:
sprintf (info, " %s", smi.modeIdent);
return;
}
/* no more info lines */
*info = 0;
return;
}
#endif
......
......@@ -31,32 +31,32 @@
/* imports */
extern char console_buffer[CFG_CBSIZE];
extern int l2_cache_enable (int l2control);
extern int eepro100_write_eeprom (struct eth_device* dev, int location,
int addr_len, unsigned short data);
extern int read_eeprom (struct eth_device* dev, int location, int addr_len);
extern int eepro100_write_eeprom (struct eth_device *dev, int location,
int addr_len, unsigned short data);
extern int read_eeprom (struct eth_device *dev, int location, int addr_len);
/*----------------------------------------------------------------------------*/
/*
* read/write to nvram is only byte access
*/
void *nvram_read(void *dest, const long src, size_t count)
void *nvram_read (void *dest, const long src, size_t count)
{
uchar *d = (uchar *) dest;
uchar *s = (uchar *) (CFG_ENV_MAP_ADRS + src);
uchar *d = (uchar *) dest;
uchar *s = (uchar *) (CFG_ENV_MAP_ADRS + src);
while (count--)
*d++ = *s++;
while (count--)
*d++ = *s++;
return dest;
return dest;
}
void nvram_write(long dest, const void *src, size_t count)
void nvram_write (long dest, const void *src, size_t count)
{
uchar *d = (uchar *) (CFG_ENV_MAP_ADRS + dest);
uchar *s = (uchar *) src;
uchar *d = (uchar *) (CFG_ENV_MAP_ADRS + dest);
uchar *s = (uchar *) src;
while (count--)
*d++ = *s++;
while (count--)
*d++ = *s++;
}
/*----------------------------------------------------------------------------*/
......@@ -67,192 +67,199 @@ void nvram_write(long dest, const void *src, size_t count)
*/
int misc_init_r (void)
{
revinfo eerev;
u_char *ptr;
u_int i, l, initSrom, copyNv;
char buf[256];
char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
0, 0, 0, 0, 10, 11, 12, 13, 14, 15 };
/* Clock setting for MPC107 i2c */
mpc107_i2c_init (MPC107_EUMB_ADDR, 0x2b);
/* Reset the EPIC */
out32r (MPC107_EUMB_GCR, 0xa0000000);
while (in32r (MPC107_EUMB_GCR) & 0x80000000); /* Wait for reset to complete */
out32r (MPC107_EUMB_GCR, 0x20000000); /* Put into into mixed mode */
while (in32r (MPC107_EUMB_IACKR) != 0xff); /* Clear all pending interrupts */
/*
* Check/Remake revision info
*/
initSrom = 0;
copyNv = 0;
/* read out current revision srom contens */
mpc107_srom_load (0x0000, (u_char*)&eerev, sizeof(revinfo),
SECOND_DEVICE, FIRST_BLOCK);
/* read out current nvram shadow image */
nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE);
if (strcmp (eerev.magic, "ELTEC") != 0)
{
/* srom is not initialized -> create a default revision info */
for (i = 0, ptr = (u_char *)&eerev; i < sizeof(revinfo); i++)
*ptr++ = 0x00;
strcpy(eerev.magic, "ELTEC");
eerev.revrev[0] = 1;
eerev.revrev[1] = 0;
eerev.size = 0x00E0;
eerev.category[0] = 0x01;
/* node id from dead e128 as default */
eerev.etheraddr[0] = 0x00;
eerev.etheraddr[1] = 0x00;
eerev.etheraddr[2] = 0x5B;
eerev.etheraddr[3] = 0x00;
eerev.etheraddr[4] = 0x2E;
eerev.etheraddr[5] = 0x4D;
/* cache config word for ELPPC */
*(int*)&eerev.res[0] = 0;
initSrom = 1; /* force dialog */
copyNv = 1; /* copy to nvram */
}
if ((copyNv == 0) && (el_srom_checksum((u_char*)&eerev, CFG_SROM_SIZE) !=
el_srom_checksum((u_char*)buf, CFG_SROM_SIZE)))
{
printf ("Invalid revision info copy in nvram !\n");
printf ("Press key:\n <c> to copy current revision info to nvram.\n");
printf (" <r> to reenter revision info.\n");
printf ("=> ");
if (0 != readline (NULL))
{
switch ((char)toupper(console_buffer[0]))
{
case 'C':
copyNv = 1;
break;
case 'R':
copyNv = 1;
initSrom = 1;
break;
}
}
}
if (initSrom)
{
memcpy (buf, &eerev.revision[0][0], 14); /* save all revision info */
printf ("Enter revision number (0-9): %c ", eerev.revision[0][0]);
if (0 != readline (NULL))
{
eerev.revision[0][0] = (char)toupper(console_buffer[0]);
memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */
}
printf ("Enter revision character (A-Z): %c ", eerev.revision[0][1]);
if (1 == readline (NULL))
{
eerev.revision[0][1] = (char)toupper(console_buffer[0]);
revinfo eerev;
u_char *ptr;
u_int i, l, initSrom, copyNv;
char buf[256];
char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
0, 0, 0, 0, 10, 11, 12, 13, 14, 15
};
/* Clock setting for MPC107 i2c */
mpc107_i2c_init (MPC107_EUMB_ADDR, 0x2b);
/* Reset the EPIC */
out32r (MPC107_EUMB_GCR, 0xa0000000);
while (in32r (MPC107_EUMB_GCR) & 0x80000000); /* Wait for reset to complete */
out32r (MPC107_EUMB_GCR, 0x20000000); /* Put into into mixed mode */
while (in32r (MPC107_EUMB_IACKR) != 0xff); /* Clear all pending interrupts */
/*
* Check/Remake revision info
*/
initSrom = 0;
copyNv = 0;
/* read out current revision srom contens */
mpc107_srom_load (0x0000, (u_char *) & eerev, sizeof (revinfo),
SECOND_DEVICE, FIRST_BLOCK);
/* read out current nvram shadow image */
nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE);
if (strcmp (eerev.magic, "ELTEC") != 0) {
/* srom is not initialized -> create a default revision info */
for (i = 0, ptr = (u_char *) & eerev; i < sizeof (revinfo);
i++)
*ptr++ = 0x00;
strcpy (eerev.magic, "ELTEC");
eerev.revrev[0] = 1;
eerev.revrev[1] = 0;
eerev.size = 0x00E0;
eerev.category[0] = 0x01;
/* node id from dead e128 as default */
eerev.etheraddr[0] = 0x00;
eerev.etheraddr[1] = 0x00;
eerev.etheraddr[2] = 0x5B;
eerev.etheraddr[3] = 0x00;
eerev.etheraddr[4] = 0x2E;
eerev.etheraddr[5] = 0x4D;
/* cache config word for ELPPC */
*(int *) &eerev.res[0] = 0;
initSrom = 1; /* force dialog */
copyNv = 1; /* copy to nvram */
}
printf ("Enter board name (V-XXXX-XXXX): %s ", (char *)&eerev.board);
if (11 == readline (NULL))
{
for (i=0; i<11; i++)
eerev.board[i] = (char)toupper(console_buffer[i]);
eerev.board[11] = '\0';
if ((copyNv == 0)
&& (el_srom_checksum ((u_char *) & eerev, CFG_SROM_SIZE) !=
el_srom_checksum ((u_char *) buf, CFG_SROM_SIZE))) {
printf ("Invalid revision info copy in nvram !\n");
printf ("Press key:\n <c> to copy current revision info to nvram.\n");
printf (" <r> to reenter revision info.\n");
printf ("=> ");
if (0 != readline (NULL)) {
switch ((char) toupper (console_buffer[0])) {
case 'C':
copyNv = 1;
break;
case 'R':
copyNv = 1;
initSrom = 1;
break;
}
}
}
printf ("Enter serial number: %s ", (char *)&eerev.serial );
if (6 == readline (NULL))
{
for (i=0; i<6; i++)
eerev.serial[i] = console_buffer[i];
eerev.serial[6] = '\0';
}
printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ",
eerev.etheraddr[0], eerev.etheraddr[1],
eerev.etheraddr[2], eerev.etheraddr[3],
eerev.etheraddr[4], eerev.etheraddr[5]);
if (12 == readline (NULL))
{
for (i=0; i<12; i+=2)
eerev.etheraddr[i>>1] = (char)(16*hex[toupper(console_buffer[i])-'0'] +
hex[toupper(console_buffer[i+1])-'0']);
}
if (initSrom) {
memcpy (buf, &eerev.revision[0][0], 14); /* save all revision info */
printf ("Enter revision number (0-9): %c ",
eerev.revision[0][0]);
if (0 != readline (NULL)) {
eerev.revision[0][0] =
(char) toupper (console_buffer[0]);
memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */
}
printf ("Enter revision character (A-Z): %c ",
eerev.revision[0][1]);
if (1 == readline (NULL)) {
eerev.revision[0][1] =
(char) toupper (console_buffer[0]);
}
printf ("Enter board name (V-XXXX-XXXX): %s ",
(char *) &eerev.board);
if (11 == readline (NULL)) {
for (i = 0; i < 11; i++)
eerev.board[i] =
(char) toupper (console_buffer[i]);
eerev.board[11] = '\0';
}
printf ("Enter serial number: %s ", (char *) &eerev.serial);
if (6 == readline (NULL)) {
for (i = 0; i < 6; i++)
eerev.serial[i] = console_buffer[i];
eerev.serial[6] = '\0';
}
printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", eerev.etheraddr[0], eerev.etheraddr[1], eerev.etheraddr[2], eerev.etheraddr[3], eerev.etheraddr[4], eerev.etheraddr[5]);
if (12 == readline (NULL)) {
for (i = 0; i < 12; i += 2)
eerev.etheraddr[i >> 1] =
(char) (16 *
hex[toupper
(console_buffer[i]) -
'0'] +
hex[toupper
(console_buffer[i + 1]) -
'0']);
}
l = strlen ((char *) &eerev.text);
printf ("Add to text section (max 64 chr): %s ",
(char *) &eerev.text);
if (0 != readline (NULL)) {
for (i = l; i < 63; i++)
eerev.text[i] = console_buffer[i - l];
eerev.text[63] = '\0';
}
/* prepare network eeprom */
memset (buf, 0, 128);
buf[0] = eerev.etheraddr[1];
buf[1] = eerev.etheraddr[0];
buf[2] = eerev.etheraddr[3];
buf[3] = eerev.etheraddr[2];
buf[4] = eerev.etheraddr[5];
buf[5] = eerev.etheraddr[4];
*(unsigned short *) &buf[20] = 0x48B2;
*(unsigned short *) &buf[22] = 0x0004;
*(unsigned short *) &buf[24] = 0x1433;
printf ("\nSRom: Writing i82559 info ........ ");
if (eepro100_srom_store ((unsigned short *) buf) == -1)
printf ("FAILED\n");
else
printf ("OK\n");
/* update CRC */
eerev.crc =
el_srom_checksum ((u_char *) eerev.board, eerev.size);
/* write new values */
printf ("\nSRom: Writing revision info ...... ");
if (mpc107_srom_store
((BLOCK_SIZE - sizeof (revinfo)), (u_char *) & eerev,
sizeof (revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1)
printf ("FAILED\n\n");
else
printf ("OK\n\n");
/* write new values as shadow image to nvram */
nvram_write (CFG_NV_SROM_COPY_ADDR, (void *) &eerev,
CFG_SROM_SIZE);
l = strlen ((char *)&eerev.text);
printf("Add to text section (max 64 chr): %s ", (char *)&eerev.text );
if (0 != readline (NULL))
{
for (i = l; i<63; i++)
eerev.text[i] = console_buffer[i-l];
eerev.text[63] = '\0';
}
/* prepare network eeprom */
memset (buf, 0, 128);
buf[0] = eerev.etheraddr[1];
buf[1] = eerev.etheraddr[0];
buf[2] = eerev.etheraddr[3];
buf[3] = eerev.etheraddr[2];
buf[4] = eerev.etheraddr[5];
buf[5] = eerev.etheraddr[4];
*(unsigned short *)&buf[20] = 0x48B2;
*(unsigned short *)&buf[22] = 0x0004;
*(unsigned short *)&buf[24] = 0x1433;
printf("\nSRom: Writing i82559 info ........ ");
if (eepro100_srom_store ((unsigned short *)buf) == -1)
printf("FAILED\n");
else
printf("OK\n");
/* update CRC */
eerev.crc = el_srom_checksum((u_char *)eerev.board, eerev.size);
/* write new values */
printf("\nSRom: Writing revision info ...... ");
if (mpc107_srom_store((BLOCK_SIZE-sizeof(revinfo)), (u_char *)&eerev,
sizeof(revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1)
printf("FAILED\n\n");
else
printf("OK\n\n");
/* write new values as shadow image to nvram */
nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE);
} /*if (initSrom) */
/* copy current values as shadow image to nvram */
if (initSrom == 0 && copyNv == 1)
nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE);
/* update environment */
sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
eerev.etheraddr[0], eerev.etheraddr[1],
eerev.etheraddr[2], eerev.etheraddr[3],
eerev.etheraddr[4], eerev.etheraddr[5]);
setenv ("ethaddr", buf);
/* set serial console as default */
if ((ptr = getenv ("console")) == NULL)
setenv ("console", "serial");
/* print actual board identification */
printf("Ident: %s Ser %s Rev %c%c\n",
eerev.board, (char *)&eerev.serial,
eerev.revision[0][0], eerev.revision[0][1]);
return (0);
/*if (initSrom) */
/* copy current values as shadow image to nvram */
if (initSrom == 0 && copyNv == 1)
nvram_write (CFG_NV_SROM_COPY_ADDR, (void *) &eerev,
CFG_SROM_SIZE);
/* update environment */
sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
eerev.etheraddr[0], eerev.etheraddr[1],
eerev.etheraddr[2], eerev.etheraddr[3],
eerev.etheraddr[4], eerev.etheraddr[5]);
setenv ("ethaddr", buf);
/* set serial console as default */
if ((ptr = getenv ("console")) == NULL)
setenv ("console", "serial");
/* print actual board identification */
printf ("Ident: %s Ser %s Rev %c%c\n",
eerev.board, (char *) &eerev.serial,
eerev.revision[0][0], eerev.revision[0][1]);
return (0);
}
/*----------------------------------------------------------------------------*/
此差异已折叠。
......@@ -190,21 +190,22 @@ const iop_conf_t iop_conf_tab[4][32] = {
*/
int board_early_init_f (void)
{
volatile t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
memctl->memc_br4 = CFG_BR4_PRELIM;
memctl->memc_or4 = CFG_OR4_PRELIM;
regs->bcsr1 = 0x62; /* to enable terminal on SMC1 */
regs->bcsr2 = 0x30; /* enable NVRAM and writing FLASH */
return 0;
volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
memctl->memc_br4 = CFG_BR4_PRELIM;
memctl->memc_or4 = CFG_OR4_PRELIM;
regs->bcsr1 = 0x62; /* to enable terminal on SMC1 */
regs->bcsr2 = 0x30; /* enable NVRAM and writing FLASH */
return 0;
}
void
reset_phy(void)
void reset_phy (void)
{
volatile t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
regs->bcsr4 = 0xC0;
volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
regs->bcsr4 = 0xC0;
}
/*
......@@ -213,15 +214,21 @@ reset_phy(void)
* Thats why its a static interpretation ...
*/
int
checkboard(void)
int checkboard (void)
{
volatile t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
uint major=0, minor=0;
volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
uint major = 0, minor = 0;
switch (regs->bcsr0) {
case 0x02: major = 1; break;
case 0x03: major = 1; minor = 1; break;
default: break;
case 0x02:
major = 1;
break;
case 0x03:
major = 1;
minor = 1;
break;
default:
break;
}
printf ("Board: Embedded Planet EP8260, Revision %d.%d\n",
major, minor);
......@@ -232,13 +239,13 @@ checkboard(void)
/* ------------------------------------------------------------------------- */
long int
initdram(int board_type)
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
volatile uchar c = 0;
volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE) + 0x110;
volatile uchar *ramaddr = (uchar *) (CFG_SDRAM_BASE) + 0x110;
/*
ulong psdmr = CFG_PSDMR;
#ifdef CFG_LSDRAM
......@@ -288,7 +295,7 @@ initdram(int board_type)
#ifndef CFG_RAMBOOT
#ifdef CFG_LSDRAM
size += CFG_SDRAM1_SIZE;
ramaddr = (uchar *)(CFG_SDRAM1_BASE) + 0x8c;
ramaddr = (uchar *) (CFG_SDRAM1_BASE) + 0x8c;
memctl->memc_lsrt = CFG_LSRT;
memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_PREA;
......
indent: Standard input:27: Warning:old style assignment ambiguity in "=*". Assuming "= *"
#ifdef ECC_TEST
static inline void ecc_off(void)
static inline void ecc_off (void)
{
*(volatile int *)(INTERNAL_REG_BASE_ADDR+0x4b4) &= ~0x00200000;
*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000;
}
static inline void ecc_on(void)
static inline void ecc_on (void)
{
*(volatile int *)(INTERNAL_REG_BASE_ADDR+0x4b4) |= 0x00200000;
*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000;
}
static int putshex(const char *buf, int len)
static int putshex (const char *buf, int len)
{
int i;
for (i=0;i<len;i++) {
printf("%02x", buf[i]);
}
return 0;
int i;
for (i = 0; i < len; i++) {
printf ("%02x", buf[i]);
}
return 0;
}
static int char_memcpy(void *d, const void *s, int len)
static int char_memcpy (void *d, const void *s, int len)
{
int i;
char *cd=d;
const char *cs=s;
for(i=0;i<len;i++) {
*(cd++)=*(cs++);
}
return 0;
int i;
char *cd = d;
const char *cs = s;
for (i = 0; i < len; i++) {
*(cd++) = *(cs++);
}
return 0;
}
static int memory_test(char *buf)
static int memory_test (char *buf)
{
const char src[][16]={
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01},
{0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02},
{0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04},
{0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08},
{0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10},
{0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20},
{0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
{0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80},
{0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55},
{0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa},
{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}
};
const int foo[] = {0};
int i,j,a;
const char src[][16] = {
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01},
{0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
0x02, 0x02, 0x02, 0x02, 0x02, 0x02},
{0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
0x04, 0x04, 0x04, 0x04, 0x04, 0x04},
{0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
0x08, 0x08, 0x08, 0x08, 0x08, 0x08},
{0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
0x10, 0x10, 0x10, 0x10, 0x10, 0x10},
{0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20},
{0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
0x40, 0x40, 0x40, 0x40, 0x40, 0x40},
{0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
0x80, 0x80, 0x80, 0x80, 0x80, 0x80},
{0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
0x55, 0x55, 0x55, 0x55, 0x55, 0x55},
{0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa},
{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
};
const int foo[] = { 0 };
int i, j, a;
printf("\ntest @ %d %p\n", foo[0], buf);
for(i=0;i<12;i++) {
for(a=0;a<8;a++) {
const char *s=src[i]+a;
int align=(unsigned)(s)&0x7;
/* ecc_off(); */
memcpy(buf,s,8);
/* ecc_on(); */
putshex(s,8);
if(memcmp(buf,s,8)) {
putc('\n');
putshex(buf,8);
printf(" [FAIL] (%p) align=%d\n", s, align);
for(j=0;j<8;j++) {
s[j]==buf[j]?puts(" "):printf("%02x", (s[j])^(buf[j]));
}
putc('\n');
} else {
printf(" [PASS] (%p) align=%d\n", s, align);
}
/* ecc_off(); */
char_memcpy(buf,s,8);
/* ecc_on(); */
putshex(s,8);
if(memcmp(buf,s,8)) {
putc('\n');
putshex(buf,8);
printf(" [FAIL] (%p) align=%d\n", s, align);
for(j=0;j<8;j++) {
s[j]==buf[j]?puts(" "):printf("%02x", (s[j])^(buf[j]));
printf ("\ntest @ %d %p\n", foo[0], buf);
for (i = 0; i < 12; i++) {
for (a = 0; a < 8; a++) {
const char *s = src[i] + a;
int align = (unsigned) (s) & 0x7;
/* ecc_off(); */
memcpy (buf, s, 8);
/* ecc_on(); */
putshex (s, 8);
if (memcmp (buf, s, 8)) {
putc ('\n');
putshex (buf, 8);
printf (" [FAIL] (%p) align=%d\n", s, align);
for (j = 0; j < 8; j++) {
s[j] == buf[j] ? puts (" ") :
printf ("%02x",
(s[j]) ^ (buf[j]));
}
putc ('\n');
} else {
printf (" [PASS] (%p) align=%d\n", s, align);
}
/* ecc_off(); */
char_memcpy (buf, s, 8);
/* ecc_on(); */
putshex (s, 8);
if (memcmp (buf, s, 8)) {
putc ('\n');
putshex (buf, 8);
printf (" [FAIL] (%p) align=%d\n", s, align);
for (j = 0; j < 8; j++) {
s[j] == buf[j] ? puts (" ") :
printf ("%02x",
(s[j]) ^ (buf[j]));
}
putc ('\n');
} else {
printf (" [PASS] (%p) align=%d\n", s, align);
}
}
putc('\n');
} else {
printf(" [PASS] (%p) align=%d\n", s, align);
}
}
}
return 0;
return 0;
}
#endif
......@@ -13,66 +13,68 @@
#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
static u32 addressTableHashMode[ GAL_ETH_DEVS ] = { 0, };
static u32 addressTableHashSize[ GAL_ETH_DEVS ] = { 0, };
static addrTblEntry *addressTableBase[ GAL_ETH_DEVS ] = { 0, };
static void *realAddrTableBase[ GAL_ETH_DEVS ] = { 0, };
static const u32 hashLength[ 2 ] = {
(0x8000), /* 8K * 4 entries */
(0x8000/16), /* 512 * 4 entries */
static u32 addressTableHashMode[GAL_ETH_DEVS] = { 0, };
static u32 addressTableHashSize[GAL_ETH_DEVS] = { 0, };
static addrTblEntry *addressTableBase[GAL_ETH_DEVS] = { 0, };
static void *realAddrTableBase[GAL_ETH_DEVS] = { 0, };
static const u32 hashLength[2] = {
(0x8000), /* 8K * 4 entries */
(0x8000 / 16), /* 512 * 4 entries */
};
/* Initialize the address table for a port, if needed */
unsigned int initAddressTable( u32 port, u32 hashMode, u32 hashSizeSelector)
unsigned int initAddressTable (u32 port, u32 hashMode, u32 hashSizeSelector)
{
unsigned int tableBase;
unsigned int tableBase;
if( port < 0 || port >= GAL_ETH_DEVS ) {
printf("%s: Invalid port number %d\n", __FUNCTION__, port );
if (port < 0 || port >= GAL_ETH_DEVS) {
printf ("%s: Invalid port number %d\n", __FUNCTION__, port);
return 0;
}
if (hashMode > 1) {
printf("%s: Invalid Hash Mode %d\n", __FUNCTION__, port );
printf ("%s: Invalid Hash Mode %d\n", __FUNCTION__, port);
return 0;
}
if ( realAddrTableBase[port] &&
( addressTableHashSize[port] != hashSizeSelector )) {
if (realAddrTableBase[port] &&
(addressTableHashSize[port] != hashSizeSelector)) {
/* we have been here before,
* but now we want a different sized table
*/
free( realAddrTableBase[port] );
free (realAddrTableBase[port]);
realAddrTableBase[port] = 0;
addressTableBase[port] = 0;
}
tableBase = (unsigned int)addressTableBase[port];
tableBase = (unsigned int) addressTableBase[port];
/* we get called for every probe, so only do this once */
if ( !tableBase ) {
int bytes = hashLength[hashSizeSelector] * sizeof(addrTblEntry);
if (!tableBase) {
int bytes =
hashLength[hashSizeSelector] * sizeof (addrTblEntry);
tableBase = (unsigned int)realAddrTableBase[port] = malloc(bytes+64);
tableBase = (unsigned int) realAddrTableBase[port] =
malloc (bytes + 64);
if(!tableBase)
{
printf("%s: alloc memory failed \n", __FUNCTION__);
if (!tableBase) {
printf ("%s: alloc memory failed \n", __FUNCTION__);
return 0;
}
/* align to octal byte */
if(tableBase&63) tableBase=(tableBase+63) & ~63;
/* align to octal byte */
if (tableBase & 63)
tableBase = (tableBase + 63) & ~63;
addressTableHashMode[port] = hashMode;
addressTableHashSize[port] = hashSizeSelector;
addressTableBase[port] = (addrTblEntry *)tableBase;
addressTableHashMode[port] = hashMode;
addressTableHashSize[port] = hashSizeSelector;
addressTableBase[port] = (addrTblEntry *) tableBase;
memset((void *)tableBase,0,bytes);
memset ((void *) tableBase, 0, bytes);
}
return tableBase;
return tableBase;
}
/*
......@@ -87,61 +89,61 @@ unsigned int initAddressTable( u32 port, u32 hashMode, u32 hashSizeSelector)
* Outputs
* return the calculated entry.
*/
u32
hashTableFunction( u32 macH, u32 macL, u32 HashSize, u32 hash_mode)
u32 hashTableFunction (u32 macH, u32 macL, u32 HashSize, u32 hash_mode)
{
u32 hashResult;
u32 addrH;
u32 addrL;
u32 addr0;
u32 addr1;
u32 addr2;
u32 addr3;
u32 addrHSwapped;
u32 addrLSwapped;
addrH = NIBBLE_SWAPPING_16_BIT( macH );
addrL = NIBBLE_SWAPPING_32_BIT( macL );
addrHSwapped = FLIP_4_BITS( addrH & 0xf )
+ ((FLIP_4_BITS( (addrH >> 4) & 0xf)) << 4)
+ ((FLIP_4_BITS( (addrH >> 8) & 0xf)) << 8)
+ ((FLIP_4_BITS( (addrH >> 12) & 0xf)) << 12);
addrLSwapped = FLIP_4_BITS( addrL & 0xf )
+ ((FLIP_4_BITS( (addrL >> 4) & 0xf)) << 4)
+ ((FLIP_4_BITS( (addrL >> 8) & 0xf)) << 8)
+ ((FLIP_4_BITS( (addrL >> 12) & 0xf)) << 12)
+ ((FLIP_4_BITS( (addrL >> 16) & 0xf)) << 16)
+ ((FLIP_4_BITS( (addrL >> 20) & 0xf)) << 20)
+ ((FLIP_4_BITS( (addrL >> 24) & 0xf)) << 24)
+ ((FLIP_4_BITS( (addrL >> 28) & 0xf)) << 28);
addrH = addrHSwapped;
addrL = addrLSwapped;
if( hash_mode == 0 ) {
addr0 = (addrL >> 2) & 0x03f;
addr1 = (addrL & 0x003) | ((addrL >> 8) & 0x7f) << 2;
addr2 = (addrL >> 15) & 0x1ff;
addr3 = ((addrL >> 24) & 0x0ff) | ((addrH & 1) << 8);
} else {
addr0 = FLIP_6_BITS( addrL & 0x03f );
addr1 = FLIP_9_BITS( ((addrL >> 6) & 0x1ff));
addr2 = FLIP_9_BITS( (addrL >> 15) & 0x1ff);
addr3 = FLIP_9_BITS( (((addrL >> 24) & 0x0ff) | ((addrH & 0x1) << 8)));
}
hashResult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
if( HashSize == _8K_TABLE ) {
hashResult = hashResult & 0xffff;
} else {
hashResult = hashResult & 0x07ff;
}
return( hashResult );
u32 hashResult;
u32 addrH;
u32 addrL;
u32 addr0;
u32 addr1;
u32 addr2;
u32 addr3;
u32 addrHSwapped;
u32 addrLSwapped;
addrH = NIBBLE_SWAPPING_16_BIT (macH);
addrL = NIBBLE_SWAPPING_32_BIT (macL);
addrHSwapped = FLIP_4_BITS (addrH & 0xf)
+ ((FLIP_4_BITS ((addrH >> 4) & 0xf)) << 4)
+ ((FLIP_4_BITS ((addrH >> 8) & 0xf)) << 8)
+ ((FLIP_4_BITS ((addrH >> 12) & 0xf)) << 12);
addrLSwapped = FLIP_4_BITS (addrL & 0xf)
+ ((FLIP_4_BITS ((addrL >> 4) & 0xf)) << 4)
+ ((FLIP_4_BITS ((addrL >> 8) & 0xf)) << 8)
+ ((FLIP_4_BITS ((addrL >> 12) & 0xf)) << 12)
+ ((FLIP_4_BITS ((addrL >> 16) & 0xf)) << 16)
+ ((FLIP_4_BITS ((addrL >> 20) & 0xf)) << 20)
+ ((FLIP_4_BITS ((addrL >> 24) & 0xf)) << 24)
+ ((FLIP_4_BITS ((addrL >> 28) & 0xf)) << 28);
addrH = addrHSwapped;
addrL = addrLSwapped;
if (hash_mode == 0) {
addr0 = (addrL >> 2) & 0x03f;
addr1 = (addrL & 0x003) | ((addrL >> 8) & 0x7f) << 2;
addr2 = (addrL >> 15) & 0x1ff;
addr3 = ((addrL >> 24) & 0x0ff) | ((addrH & 1) << 8);
} else {
addr0 = FLIP_6_BITS (addrL & 0x03f);
addr1 = FLIP_9_BITS (((addrL >> 6) & 0x1ff));
addr2 = FLIP_9_BITS ((addrL >> 15) & 0x1ff);
addr3 = FLIP_9_BITS ((((addrL >> 24) & 0x0ff) |
((addrH & 0x1) << 8)));
}
hashResult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
if (HashSize == _8K_TABLE) {
hashResult = hashResult & 0xffff;
} else {
hashResult = hashResult & 0x07ff;
}
return (hashResult);
}
......@@ -160,66 +162,59 @@ hashTableFunction( u32 macH, u32 macL, u32 HashSize, u32 hash_mode)
* TRUE if success.
* FALSE if table full
*/
int
addAddressTableEntry(
u32 port,
u32 macH,
u32 macL,
u32 rd,
u32 skip )
int addAddressTableEntry (u32 port, u32 macH, u32 macL, u32 rd, u32 skip)
{
addrTblEntry *entry;
u32 newHi;
u32 newLo;
u32 i;
newLo = (((macH >> 4) & 0xf) << 15)
| (((macH >> 0) & 0xf) << 11)
| (((macH >> 12) & 0xf) << 7)
| (((macH >> 8) & 0xf) << 3)
| (((macL >> 20) & 0x1) << 31)
| (((macL >> 16) & 0xf) << 27)
| (((macL >> 28) & 0xf) << 23)
| (((macL >> 24) & 0xf) << 19)
| (skip << SKIP_BIT) | (rd << 2) | VALID;
newHi = (((macL >> 4) & 0xf) << 15)
| (((macL >> 0) & 0xf) << 11)
| (((macL >> 12) & 0xf) << 7)
| (((macL >> 8) & 0xf) << 3)
| (((macL >> 21) & 0x7) << 0);
/*
* Pick the appropriate table, start scanning for free/reusable
* entries at the index obtained by hashing the specified MAC address
*/
entry = addressTableBase[port];
entry += hashTableFunction( macH, macL, addressTableHashSize[port],
addressTableHashMode[port] );
for( i = 0; i < HOP_NUMBER; i++, entry++ ) {
if( !(entry->lo & VALID) /*|| (entry->lo & SKIP)*/ ) {
break;
} else { /* if same address put in same position */
if( ((entry->lo & 0xfffffff8) == (newLo & 0xfffffff8))
&& (entry->hi == newHi) )
{
break;
}
addrTblEntry *entry;
u32 newHi;
u32 newLo;
u32 i;
newLo = (((macH >> 4) & 0xf) << 15)
| (((macH >> 0) & 0xf) << 11)
| (((macH >> 12) & 0xf) << 7)
| (((macH >> 8) & 0xf) << 3)
| (((macL >> 20) & 0x1) << 31)
| (((macL >> 16) & 0xf) << 27)
| (((macL >> 28) & 0xf) << 23)
| (((macL >> 24) & 0xf) << 19)
| (skip << SKIP_BIT) | (rd << 2) | VALID;
newHi = (((macL >> 4) & 0xf) << 15)
| (((macL >> 0) & 0xf) << 11)
| (((macL >> 12) & 0xf) << 7)
| (((macL >> 8) & 0xf) << 3)
| (((macL >> 21) & 0x7) << 0);
/*
* Pick the appropriate table, start scanning for free/reusable
* entries at the index obtained by hashing the specified MAC address
*/
entry = addressTableBase[port];
entry += hashTableFunction (macH, macL, addressTableHashSize[port],
addressTableHashMode[port]);
for (i = 0; i < HOP_NUMBER; i++, entry++) {
if (!(entry->lo & VALID) /*|| (entry->lo & SKIP) */ ) {
break;
} else { /* if same address put in same position */
if (((entry->lo & 0xfffffff8) == (newLo & 0xfffffff8))
&& (entry->hi == newHi)) {
break;
}
}
}
if (i == HOP_NUMBER) {
PRINTF ("addGT64260addressTableEntry: table section is full\n");
return (FALSE);
}
}
if( i == HOP_NUMBER ) {
PRINTF( "addGT64260addressTableEntry: table section is full\n" );
return( FALSE );
}
/*
* Update the selected entry
*/
entry->hi = newHi;
entry->lo = newLo;
DCACHE_FLUSH_N_SYNC( (u32)entry, MAC_ENTRY_SIZE );
return( TRUE );
/*
* Update the selected entry
*/
entry->hi = newHi;
entry->lo = newLo;
DCACHE_FLUSH_N_SYNC ((u32) entry, MAC_ENTRY_SIZE);
return (TRUE);
}
#endif /* CONFIG_GT_USE_MAC_HASH_TABLE */
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......@@ -2,33 +2,33 @@
#define OUT_PENDING 2
enum {
ZUMA_MBOXMSG_DONE,
ZUMA_MBOXMSG_MACL,
ZUMA_MBOXMSG_MACH,
ZUMA_MBOXMSG_IP,
ZUMA_MBOXMSG_SLOT,
ZUMA_MBOXMSG_RESET,
ZUMA_MBOXMSG_BAUD,
ZUMA_MBOXMSG_START,
ZUMA_MBOXMSG_ENG_PRV_MACL,
ZUMA_MBOXMSG_ENG_PRV_MACH,
ZUMA_MBOXMSG_DONE,
ZUMA_MBOXMSG_MACL,
ZUMA_MBOXMSG_MACH,
ZUMA_MBOXMSG_IP,
ZUMA_MBOXMSG_SLOT,
ZUMA_MBOXMSG_RESET,
ZUMA_MBOXMSG_BAUD,
ZUMA_MBOXMSG_START,
ZUMA_MBOXMSG_ENG_PRV_MACL,
ZUMA_MBOXMSG_ENG_PRV_MACH,
MBOXMSG_LAST
MBOXMSG_LAST
};
struct zuma_mailbox_info {
unsigned char acc_mac[6];
unsigned char prv_mac[6];
unsigned int ip;
unsigned int slot_bac;
unsigned int console_baud;
unsigned int debug_baud;
unsigned char acc_mac[6];
unsigned char prv_mac[6];
unsigned int ip;
unsigned int slot_bac;
unsigned int console_baud;
unsigned int debug_baud;
};
struct _zuma_mbox_dev {
pci_dev_t dev;
PBB_DMA_REG_MAP *sip;
struct zuma_mailbox_info mailbox;
pci_dev_t dev;
PBB_DMA_REG_MAP *sip;
struct zuma_mailbox_info mailbox;
};
#define zuma_prv_mac zuma_mbox_dev.mailbox.prv_mac
......@@ -40,4 +40,4 @@ struct _zuma_mbox_dev {
extern struct _zuma_mbox_dev zuma_mbox_dev;
extern int zuma_mbox_init(void);
extern int zuma_mbox_init (void);
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......@@ -28,7 +28,7 @@ LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $^
$(AR) crv $@ $(OBJS)
#########################################################################
......
......@@ -22,4 +22,4 @@
# MA 02111-1307 USA
#
TEXT_BASE = 0x3e0000
TEXT_BASE = 0xffe00000
......@@ -22,14 +22,31 @@
*/
#include <common.h>
#include <asm/m5272.h>
#include <asm/immap_5272.h>
int checkboard (void)
{
puts ("MOTOROLA MCF5272C3 Evaluation Board\n");
int checkboard (void) {
puts ("Board: ");
puts("MOTOROLA MCF5272C3 EVB\n");
return 0;
}
};
long int initdram (int board_type) {
volatile sdramctrl_t * sdp = (sdramctrl_t *)(CFG_MBAR + MCFSIM_SDCR);
sdp->sdram_sdtr = 0xf539;
sdp->sdram_sdcr = 0x4211;
/* Dummy write to start SDRAM */
*((volatile unsigned long *)0) = 0;
return CFG_SDRAM_SIZE * 1024 * 1024;
};
int testdram (void) {
/* TODO: XXX XXX XXX */
printf ("DRAM test not implemented!\n");
long int initdram (int board_type)
{
return 0x400000;
return (0);
}
/*
* (C) Copyright 2000-2003
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
......@@ -22,7 +22,7 @@
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
......@@ -56,15 +56,14 @@ SECTIONS
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/coldfire/start.o (.text)
common/dlmalloc.o (.text)
lib_generic/string.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
cpu/mcf52x2/start.o (.text)
lib_m68k/traps.o (.text)
cpu/mcf52x2/interrupts.o (.text)
common/dlmalloc.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset; */
common/environment.o(.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
......@@ -85,9 +84,12 @@ SECTIONS
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
......@@ -108,6 +110,11 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
......
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......@@ -28,7 +28,7 @@ LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $^
$(AR) crv $@ $(OBJS)
#########################################################################
......
......@@ -22,4 +22,4 @@
# MA 02111-1307 USA
#
TEXT_BASE = 0x3e0000
TEXT_BASE = 0x20000
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......@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := ppmc8260.o strataflash.o
OBJS := ppmc8260.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
......
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......@@ -54,7 +54,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
unsigned short data;
int rcode = 0;
#ifdef CONFIG_8xx
#if defined(CONFIG_8xx) || defined(CONFIG_MCF52x2)
mii_init ();
#endif
......
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#ifndef _M68K_BYTEORDER_H
#define _M68K_BYTEORDER_H
#include <asm/types.h>
#include <linux/byteorder/big_endian.h>
#endif /* _M68K_BYTEORDER_H */
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