Merge branch 'master' of git://git.denx.de/u-boot-sh

* 'master' of git://git.denx.de/u-boot-sh:
  sh: add calling mmc_initialize in board.c
  sh: sh7757lcr: Add KEEP order to start.o section
  usb: r8a66597: Fix argument mistake of inl
  sh: Clean up rsk7264 board settings
  sh: sh2a: Add sh2a optimize to config.mk
  sh: Fix rsk7203 alignment problem
  sh: Add support for SH2A freestanding build
  sh: Add Renesas rsk7264 board

MAINTAINERS

@@ -142,6 +142,10 @@ Alex Dubov <oakad@yahoo.com>
 
 	mpq101		MPC8548
 
+Phil Edworthy <phil.edworthy@renesas.com>
+
+	rsk7264		SH7264
+
 Dirk Eibach <eibach@gdsys.de>
 
 	devconcenter	PPC460EX

arch/sh/cpu/sh2/config.mk

@@ -23,6 +23,11 @@
 #
 ENDIANNESS += -EB
 
+ifdef CONFIG_SH2A
+PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb -mno-fdpic -ffreestanding
+else # SH2
 PLATFORM_CPPFLAGS += -m3e -mb
+endif
+
 PLATFORM_RELFLAGS += -ffixed-r13
 PLATFORM_LDFLAGS += $(ENDIANNESS)

arch/sh/cpu/sh2/cpu.c

@@ -33,6 +33,9 @@
 #define scif0_enable() do {\
 		writeb(readb(STBCR4) & ~0x80, STBCR4);\
 	} while (0)
+#define scif3_enable() do {\
+		writeb(readb(STBCR4) & ~0x10, STBCR4);\
+	} while (0)
 
 int checkcpu(void)
 {
@@ -47,7 +50,11 @@ int checkcpu(void)
 int cpu_init(void)
 {
 	/* SCIF enable */
+#if defined(CONFIG_CONS_SCIF3)
+	scif3_enable();
+#else
 	scif0_enable();
+#endif
 	/* CMT clock enable */
 	cmt_clock_enable() ;
 	return 0;

arch/sh/include/asm/cpu_sh2.h

@@ -33,6 +33,8 @@
 
 #if defined(CONFIG_CPU_SH7203)
 # include <asm/cpu_sh7203.h>
+#elif defined(CONFIG_CPU_SH7264)
+# include <asm/cpu_sh7264.h>
 #else
 # error "Unknown SH2 variant"
 #endif

arch/sh/include/asm/cpu_sh7264.h

+#ifndef _ASM_CPU_SH7264_H_
+#define _ASM_CPU_SH7264_H_
+
+/* Cache */
+#define CCR1		0xFFFC1000
+#define CCR		CCR1
+
+/* PFC */
+#define PACR		0xA4050100
+#define PBCR		0xA4050102
+#define PCCR		0xA4050104
+#define PETCR		0xA4050106
+
+/* Port Data Registers */
+#define PADR		0xA4050120
+#define PBDR		0xA4050122
+#define PCDR		0xA4050124
+
+/* BSC */
+
+/* SDRAM controller */
+
+/* SCIF */
+#define SCSMR_3		0xFFFE9800
+#define SCIF3_BASE	SCSMR_3
+
+/* Timer(CMT) */
+#define CMSTR		0xFFFEC000
+#define CMCSR_0 	0xFFFEC002
+#define CMCNT_0 	0xFFFEC004
+#define CMCOR_0 	0xFFFEC006
+#define CMCSR_1 	0xFFFEC008
+#define CMCNT_1 	0xFFFEC00A
+#define CMCOR_1		0xFFFEC00C
+
+/* On chip oscillator circuits */
+#define FRQCR		0xA415FF80
+#define WTCNT		0xA415FF84
+#define WTCSR		0xA415FF86
+
+#endif	/* _ASM_CPU_SH7264_H_ */

arch/sh/lib/Makefile

@@ -21,8 +21,15 @@
 include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(ARCH).o
+LIBGCC	= $(obj)libgcc.o
 
 SOBJS-y	+=
+GLSOBJS	+= ashiftrt.o
+GLSOBJS	+= ashiftlt.o
+GLSOBJS	+= lshiftrt.o
+GLSOBJS	+= ashldi3.o
+GLSOBJS	+= lshrdi3.o
+GLSOBJS	+= movmem.o
 
 COBJS-y	+= board.o
 COBJS-y	+= bootm.o
@@ -37,10 +44,25 @@ endif
 
 SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+LGOBJS	:= $(addprefix $(obj),$(GLSOBJS)) \
+	   $(addprefix $(obj),$(GLCOBJS))
+
+# Always build libsh.o
+TARGETS	:= $(LIB)
+
+# Build private libgcc only when asked for
+ifdef USE_PRIVATE_LIBGCC
+TARGETS	+= $(LIBGCC)
+endif
+
+all:	$(TARGETS)
 
 $(LIB):	$(obj).depend $(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
 
+$(LIBGCC): $(obj).depend $(LGOBJS)
+	$(call cmd_link_o_target, $(LGOBJS))
+
 #########################################################################
 
 # defines $(obj).depend target

arch/sh/lib/ashiftlt.S

+/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+   2004, 2005, 2006
+   Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file into combinations with other programs,
+and to distribute those combinations without any restriction coming
+from the use of this file.  (The General Public License restrictions
+do apply in other respects; for example, they cover modification of
+the file, and distribution when not linked into a combine
+executable.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+Boston, MA 02110-1301, USA.  */
+
+!! libgcc routines for the Renesas / SuperH SH CPUs.
+!! Contributed by Steve Chamberlain.
+!! sac@cygnus.com
+
+!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
+!! recoded in assembly by Toshiyasu Morita
+!! tm@netcom.com
+
+/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
+   ELF local label prefixes by J"orn Rennecke
+   amylaar@cygnus.com  */
+
+!
+! GLOBAL(ashlsi3)
+!
+! Entry:
+!
+! r4: Value to shift
+! r5: Shifts
+!
+! Exit:
+!
+! r0: Result
+!
+! Destroys:
+!
+! (none)
+!
+	.global	__ashlsi3
+	.align	2
+__ashlsi3:
+	mov	#31,r0
+	and	r0,r5
+	mova	__ashlsi3_table,r0
+	mov.b	@(r0,r5),r5
+#ifdef __sh1__
+	add	r5,r0
+	jmp	@r0
+#else
+	braf	r5
+#endif
+	mov	r4,r0
+
+	.align	2
+__ashlsi3_table:
+	.byte		__ashlsi3_0-__ashlsi3_table
+	.byte		__ashlsi3_1-__ashlsi3_table
+	.byte		__ashlsi3_2-__ashlsi3_table
+	.byte		__ashlsi3_3-__ashlsi3_table
+	.byte		__ashlsi3_4-__ashlsi3_table
+	.byte		__ashlsi3_5-__ashlsi3_table
+	.byte		__ashlsi3_6-__ashlsi3_table
+	.byte		__ashlsi3_7-__ashlsi3_table
+	.byte		__ashlsi3_8-__ashlsi3_table
+	.byte		__ashlsi3_9-__ashlsi3_table
+	.byte		__ashlsi3_10-__ashlsi3_table
+	.byte		__ashlsi3_11-__ashlsi3_table
+	.byte		__ashlsi3_12-__ashlsi3_table
+	.byte		__ashlsi3_13-__ashlsi3_table
+	.byte		__ashlsi3_14-__ashlsi3_table
+	.byte		__ashlsi3_15-__ashlsi3_table
+	.byte		__ashlsi3_16-__ashlsi3_table
+	.byte		__ashlsi3_17-__ashlsi3_table
+	.byte		__ashlsi3_18-__ashlsi3_table
+	.byte		__ashlsi3_19-__ashlsi3_table
+	.byte		__ashlsi3_20-__ashlsi3_table
+	.byte		__ashlsi3_21-__ashlsi3_table
+	.byte		__ashlsi3_22-__ashlsi3_table
+	.byte		__ashlsi3_23-__ashlsi3_table
+	.byte		__ashlsi3_24-__ashlsi3_table
+	.byte		__ashlsi3_25-__ashlsi3_table
+	.byte		__ashlsi3_26-__ashlsi3_table
+	.byte		__ashlsi3_27-__ashlsi3_table
+	.byte		__ashlsi3_28-__ashlsi3_table
+	.byte		__ashlsi3_29-__ashlsi3_table
+	.byte		__ashlsi3_30-__ashlsi3_table
+	.byte		__ashlsi3_31-__ashlsi3_table
+
+__ashlsi3_6:
+	shll2	r0
+__ashlsi3_4:
+	shll2	r0
+__ashlsi3_2:
+	rts
+	shll2	r0
+
+__ashlsi3_7:
+	shll2	r0
+__ashlsi3_5:
+	shll2	r0
+__ashlsi3_3:
+	shll2	r0
+__ashlsi3_1:
+	rts
+	shll	r0
+
+__ashlsi3_14:
+	shll2	r0
+__ashlsi3_12:
+	shll2	r0
+__ashlsi3_10:
+	shll2	r0
+__ashlsi3_8:
+	rts
+	shll8	r0
+
+__ashlsi3_15:
+	shll2	r0
+__ashlsi3_13:
+	shll2	r0
+__ashlsi3_11:
+	shll2	r0
+__ashlsi3_9:
+	shll8	r0
+	rts
+	shll	r0
+
+__ashlsi3_22:
+	shll2	r0
+__ashlsi3_20:
+	shll2	r0
+__ashlsi3_18:
+	shll2	r0
+__ashlsi3_16:
+	rts
+	shll16	r0
+
+__ashlsi3_23:
+	shll2	r0
+__ashlsi3_21:
+	shll2	r0
+__ashlsi3_19:
+	shll2	r0
+__ashlsi3_17:
+	shll16	r0
+	rts
+	shll	r0
+
+__ashlsi3_30:
+	shll2	r0
+__ashlsi3_28:
+	shll2	r0
+__ashlsi3_26:
+	shll2	r0
+__ashlsi3_24:
+	shll16	r0
+	rts
+	shll8	r0
+
+__ashlsi3_31:
+	shll2	r0
+__ashlsi3_29:
+	shll2	r0
+__ashlsi3_27:
+	shll2	r0
+__ashlsi3_25:
+	shll16	r0
+	shll8	r0
+	rts
+	shll	r0
+
+__ashlsi3_0:
+	rts
+	nop

arch/sh/lib/ashiftrt.S

+/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+   2004, 2005, 2006
+   Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file into combinations with other programs,
+and to distribute those combinations without any restriction coming
+from the use of this file.  (The General Public License restrictions
+do apply in other respects; for example, they cover modification of
+the file, and distribution when not linked into a combine
+executable.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+Boston, MA 02110-1301, USA.  */
+
+!! libgcc routines for the Renesas / SuperH SH CPUs.
+!! Contributed by Steve Chamberlain.
+!! sac@cygnus.com
+
+!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
+!! recoded in assembly by Toshiyasu Morita
+!! tm@netcom.com
+
+/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
+   ELF local label prefixes by J"orn Rennecke
+   amylaar@cygnus.com  */
+
+	.global	__ashiftrt_r4_0
+	.global	__ashiftrt_r4_1
+	.global	__ashiftrt_r4_2
+	.global	__ashiftrt_r4_3
+	.global	__ashiftrt_r4_4
+	.global	__ashiftrt_r4_5
+	.global	__ashiftrt_r4_6
+	.global	__ashiftrt_r4_7
+	.global	__ashiftrt_r4_8
+	.global	__ashiftrt_r4_9
+	.global	__ashiftrt_r4_10
+	.global	__ashiftrt_r4_11
+	.global	__ashiftrt_r4_12
+	.global	__ashiftrt_r4_13
+	.global	__ashiftrt_r4_14
+	.global	__ashiftrt_r4_15
+	.global	__ashiftrt_r4_16
+	.global	__ashiftrt_r4_17
+	.global	__ashiftrt_r4_18
+	.global	__ashiftrt_r4_19
+	.global	__ashiftrt_r4_20
+	.global	__ashiftrt_r4_21
+	.global	__ashiftrt_r4_22
+	.global	__ashiftrt_r4_23
+	.global	__ashiftrt_r4_24
+	.global	__ashiftrt_r4_25
+	.global	__ashiftrt_r4_26
+	.global	__ashiftrt_r4_27
+	.global	__ashiftrt_r4_28
+	.global	__ashiftrt_r4_29
+	.global	__ashiftrt_r4_30
+	.global	__ashiftrt_r4_31
+	.global	__ashiftrt_r4_32
+
+	.align	1
+__ashiftrt_r4_32:
+__ashiftrt_r4_31:
+	rotcl	r4
+	rts
+	subc	r4,r4
+__ashiftrt_r4_30:
+	shar	r4
+__ashiftrt_r4_29:
+	shar	r4
+__ashiftrt_r4_28:
+	shar	r4
+__ashiftrt_r4_27:
+	shar	r4
+__ashiftrt_r4_26:
+	shar	r4
+__ashiftrt_r4_25:
+	shar	r4
+__ashiftrt_r4_24:
+	shlr16	r4
+	shlr8	r4
+	rts
+	exts.b	r4,r4
+__ashiftrt_r4_23:
+	shar	r4
+__ashiftrt_r4_22:
+	shar	r4
+__ashiftrt_r4_21:
+	shar	r4
+__ashiftrt_r4_20:
+	shar	r4
+__ashiftrt_r4_19:
+	shar	r4
+__ashiftrt_r4_18:
+	shar	r4
+__ashiftrt_r4_17:
+	shar	r4
+__ashiftrt_r4_16:
+	shlr16	r4
+	rts
+	exts.w	r4,r4
+__ashiftrt_r4_15:
+	shar	r4
+__ashiftrt_r4_14:
+	shar	r4
+__ashiftrt_r4_13:
+	shar	r4
+__ashiftrt_r4_12:
+	shar	r4
+__ashiftrt_r4_11:
+	shar	r4
+__ashiftrt_r4_10:
+	shar	r4
+__ashiftrt_r4_9:
+	shar	r4
+__ashiftrt_r4_8:
+	shar	r4
+__ashiftrt_r4_7:
+	shar	r4
+__ashiftrt_r4_6:
+	shar	r4
+__ashiftrt_r4_5:
+	shar	r4
+__ashiftrt_r4_4:
+	shar	r4
+__ashiftrt_r4_3:
+	shar	r4
+__ashiftrt_r4_2:
+	shar	r4
+__ashiftrt_r4_1:
+	rts
+	shar	r4
+__ashiftrt_r4_0:
+	rts
+	nop

arch/sh/lib/ashldi3.c

+#include "libgcc.h"
+
+long long __ashldi3(long long u, word_type b)
+{
+	DWunion uu, w;
+	word_type bm;
+
+	if (b == 0)
+		return u;
+
+	uu.ll = u;
+	bm = 32 - b;
+
+	if (bm <= 0) {
+		w.s.low = 0;
+		w.s.high = (unsigned int) uu.s.low << -bm;
+	} else {
+		const unsigned int carries = (unsigned int) uu.s.low >> bm;
+
+		w.s.low = (unsigned int) uu.s.low << b;
+		w.s.high = ((unsigned int) uu.s.high << b) | carries;
+	}
+
+	return w.ll;
+}

arch/sh/lib/board.c

@@ -107,6 +107,15 @@ static int sh_net_init(void)
 }
 #endif
 
+#if defined(CONFIG_CMD_MMC)
+static int sh_mmc_init(void)
+{
+	puts("MMC:   ");
+	mmc_initialize(gd->bd);
+	return 0;
+}
+#endif
+
 typedef int (init_fnc_t) (void);
 
 init_fnc_t *init_sequence[] =
@@ -137,6 +146,9 @@ init_fnc_t *init_sequence[] =
 #endif
 #if defined(CONFIG_CMD_NET)
 	sh_net_init,		/* SH specific eth init */
+#endif
+#if defined(CONFIG_CMD_MMC)
+	sh_mmc_init,
 #endif
 	NULL			/* Terminate this list */
 };

arch/sh/lib/libgcc.h

+#ifndef __ASM_LIBGCC_H
+#define __ASM_LIBGCC_H
+
+#include <asm/byteorder.h>
+
+typedef int word_type __attribute__ ((mode (__word__)));
+
+#ifdef __BIG_ENDIAN
+struct DWstruct {
+	int high, low;
+};
+#elif defined(__LITTLE_ENDIAN)
+struct DWstruct {
+	int low, high;
+};
+#else
+#error I feel sick.
+#endif
+
+typedef union {
+	struct DWstruct s;
+	long long ll;
+} DWunion;
+
+#endif /* __ASM_LIBGCC_H */

arch/sh/lib/lshiftrt.S

+/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+   2004, 2005, 2006
+   Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file into combinations with other programs,
+and to distribute those combinations without any restriction coming
+from the use of this file.  (The General Public License restrictions
+do apply in other respects; for example, they cover modification of
+the file, and distribution when not linked into a combine
+executable.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+Boston, MA 02110-1301, USA.  */
+
+!! libgcc routines for the Renesas / SuperH SH CPUs.
+!! Contributed by Steve Chamberlain.
+!! sac@cygnus.com
+
+!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
+!! recoded in assembly by Toshiyasu Morita
+!! tm@netcom.com
+
+/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
+   ELF local label prefixes by J"orn Rennecke
+   amylaar@cygnus.com  */
+
+!
+! __lshrsi3)
+!
+! Entry:
+!
+! r4: Value to shift
+! r5: Shifts
+!
+! Exit:
+!
+! r0: Result
+!
+! Destroys:
+!
+! (none)
+!
+	.global	__lshrsi3
+	.align	2
+__lshrsi3:
+	mov	#31,r0
+	and	r0,r5
+	mova	__lshrsi3_table,r0
+	mov.b	@(r0,r5),r5
+#ifdef __sh1__
+	add	r5,r0
+	jmp	@r0
+#else
+	braf	r5
+#endif
+	mov	r4,r0
+
+	.align	2
+__lshrsi3_table:
+	.byte		__lshrsi3_0-__lshrsi3_table
+	.byte		__lshrsi3_1-__lshrsi3_table
+	.byte		__lshrsi3_2-__lshrsi3_table
+	.byte		__lshrsi3_3-__lshrsi3_table
+	.byte		__lshrsi3_4-__lshrsi3_table
+	.byte		__lshrsi3_5-__lshrsi3_table
+	.byte		__lshrsi3_6-__lshrsi3_table
+	.byte		__lshrsi3_7-__lshrsi3_table
+	.byte		__lshrsi3_8-__lshrsi3_table
+	.byte		__lshrsi3_9-__lshrsi3_table
+	.byte		__lshrsi3_10-__lshrsi3_table
+	.byte		__lshrsi3_11-__lshrsi3_table
+	.byte		__lshrsi3_12-__lshrsi3_table
+	.byte		__lshrsi3_13-__lshrsi3_table
+	.byte		__lshrsi3_14-__lshrsi3_table
+	.byte		__lshrsi3_15-__lshrsi3_table
+	.byte		__lshrsi3_16-__lshrsi3_table
+	.byte		__lshrsi3_17-__lshrsi3_table
+	.byte		__lshrsi3_18-__lshrsi3_table
+	.byte		__lshrsi3_19-__lshrsi3_table
+	.byte		__lshrsi3_20-__lshrsi3_table
+	.byte		__lshrsi3_21-__lshrsi3_table
+	.byte		__lshrsi3_22-__lshrsi3_table
+	.byte		__lshrsi3_23-__lshrsi3_table
+	.byte		__lshrsi3_24-__lshrsi3_table
+	.byte		__lshrsi3_25-__lshrsi3_table
+	.byte		__lshrsi3_26-__lshrsi3_table
+	.byte		__lshrsi3_27-__lshrsi3_table
+	.byte		__lshrsi3_28-__lshrsi3_table
+	.byte		__lshrsi3_29-__lshrsi3_table
+	.byte		__lshrsi3_30-__lshrsi3_table
+	.byte		__lshrsi3_31-__lshrsi3_table
+
+__lshrsi3_6:
+	shlr2	r0
+__lshrsi3_4:
+	shlr2	r0
+__lshrsi3_2:
+	rts
+	shlr2	r0
+
+__lshrsi3_7:
+	shlr2	r0
+__lshrsi3_5:
+	shlr2	r0
+__lshrsi3_3:
+	shlr2	r0
+__lshrsi3_1:
+	rts
+	shlr	r0
+
+__lshrsi3_14:
+	shlr2	r0
+__lshrsi3_12:
+	shlr2	r0
+__lshrsi3_10:
+	shlr2	r0
+__lshrsi3_8:
+	rts
+	shlr8	r0
+
+__lshrsi3_15:
+	shlr2	r0
+__lshrsi3_13:
+	shlr2	r0
+__lshrsi3_11:
+	shlr2	r0
+__lshrsi3_9:
+	shlr8	r0
+	rts
+	shlr	r0
+
+__lshrsi3_22:
+	shlr2	r0
+__lshrsi3_20:
+	shlr2	r0
+__lshrsi3_18:
+	shlr2	r0
+__lshrsi3_16:
+	rts
+	shlr16	r0
+
+__lshrsi3_23:
+	shlr2	r0
+__lshrsi3_21:
+	shlr2	r0
+__lshrsi3_19:
+	shlr2	r0
+__lshrsi3_17:
+	shlr16	r0
+	rts
+	shlr	r0
+
+__lshrsi3_30:
+	shlr2	r0
+__lshrsi3_28:
+	shlr2	r0
+__lshrsi3_26:
+	shlr2	r0
+__lshrsi3_24:
+	shlr16	r0
+	rts
+	shlr8	r0
+
+__lshrsi3_31:
+	shlr2	r0
+__lshrsi3_29:
+	shlr2	r0
+__lshrsi3_27:
+	shlr2	r0
+__lshrsi3_25:
+	shlr16	r0
+	shlr8	r0
+	rts
+	shlr	r0
+
+__lshrsi3_0:
+	rts
+	nop

arch/sh/lib/lshrdi3.c

+#include "libgcc.h"
+
+long long __lshrdi3(long long u, word_type b)
+{
+	DWunion uu, w;
+	word_type bm;
+
+	if (b == 0)
+		return u;
+
+	uu.ll = u;
+	bm = 32 - b;
+
+	if (bm <= 0) {
+		w.s.high = 0;
+		w.s.low = (unsigned int) uu.s.high >> -bm;
+	} else {
+		const unsigned int carries = (unsigned int) uu.s.high << bm;
+
+		w.s.high = (unsigned int) uu.s.high >> b;
+		w.s.low = ((unsigned int) uu.s.low >> b) | carries;
+	}
+
+	return w.ll;
+}

arch/sh/lib/movmem.S

+/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+   2004, 2005, 2006
+   Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file into combinations with other programs,
+and to distribute those combinations without any restriction coming
+from the use of this file.  (The General Public License restrictions
+do apply in other respects; for example, they cover modification of
+the file, and distribution when not linked into a combine
+executable.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+Boston, MA 02110-1301, USA.  */
+
+!! libgcc routines for the Renesas / SuperH SH CPUs.
+!! Contributed by Steve Chamberlain.
+!! sac@cygnus.com
+
+!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
+!! recoded in assembly by Toshiyasu Morita
+!! tm@netcom.com
+
+/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
+   ELF local label prefixes by J"orn Rennecke
+   amylaar@cygnus.com  */
+
+	.text
+	.balign	4
+	.global	__movmem
+	.global __movstr
+	.set __movstr, __movmem
+	/* This would be a lot simpler if r6 contained the byte count
+	   minus 64, and we wouldn't be called here for a byte count of 64.  */
+__movmem:
+	sts.l	pr,@-r15
+	shll2	r6
+	bsr	__movmemSI52+2
+	mov.l	@(48,r5),r0
+	.balign	4
+movmem_loop: /* Reached with rts */
+	mov.l	@(60,r5),r0
+	add	#-64,r6
+	mov.l	r0,@(60,r4)
+	tst	r6,r6
+	mov.l	@(56,r5),r0
+	bt	movmem_done
+	mov.l	r0,@(56,r4)
+	cmp/pl	r6
+	mov.l	@(52,r5),r0
+	add	#64,r5
+	mov.l	r0,@(52,r4)
+	add	#64,r4
+	bt	__movmemSI52
+! done all the large groups, do the remainder
+! jump to movmem+
+	mova	__movmemSI4+4,r0
+	add	r6,r0
+	jmp	@r0
+movmem_done: ! share slot insn, works out aligned.
+	lds.l	@r15+,pr
+	mov.l	r0,@(56,r4)
+	mov.l	@(52,r5),r0
+	rts
+	mov.l	r0,@(52,r4)
+	.balign	4
+
+	.global	__movmemSI64
+	.global __movstrSI64
+	.set	__movstrSI64, __movmemSI64
+__movmemSI64:
+	mov.l	@(60,r5),r0
+	mov.l	r0,@(60,r4)
+	.global	__movmemSI60
+	.global __movstrSI60
+	.set	__movstrSI60, __movmemSI60
+__movmemSI60:
+	mov.l	@(56,r5),r0
+	mov.l	r0,@(56,r4)
+	.global	__movmemSI56
+	.global __movstrSI56
+	.set	__movstrSI56, __movmemSI56
+__movmemSI56:
+	mov.l	@(52,r5),r0
+	mov.l	r0,@(52,r4)
+	.global	__movmemSI52
+	.global __movstrSI52
+	.set	__movstrSI52, __movmemSI52
+__movmemSI52:
+	mov.l	@(48,r5),r0
+	mov.l	r0,@(48,r4)
+	.global	__movmemSI48
+	.global	__movstrSI48
+	.set	__movstrSI48, __movmemSI48
+__movmemSI48:
+	mov.l	@(44,r5),r0
+	mov.l	r0,@(44,r4)
+	.global	__movmemSI44
+	.global	__movstrSI44
+	.set	__movstrSI44, __movmemSI44
+__movmemSI44:
+	mov.l	@(40,r5),r0
+	mov.l	r0,@(40,r4)
+	.global	__movmemSI40
+	.global __movstrSI40
+	.set	__movstrSI40, __movmemSI40
+__movmemSI40:
+	mov.l	@(36,r5),r0
+	mov.l	r0,@(36,r4)
+	.global	__movmemSI36
+	.global	__movstrSI36
+	.set	__movstrSI36, __movmemSI36
+__movmemSI36:
+	mov.l	@(32,r5),r0
+	mov.l	r0,@(32,r4)
+	.global	__movmemSI32
+	.global	__movstrSI32
+	.set	__movstrSI32, __movmemSI32
+__movmemSI32:
+	mov.l	@(28,r5),r0
+	mov.l	r0,@(28,r4)
+	.global	__movmemSI28
+	.global	__movstrSI28
+	.set	__movstrSI28, __movmemSI28
+__movmemSI28:
+	mov.l	@(24,r5),r0
+	mov.l	r0,@(24,r4)
+	.global	__movmemSI24
+	.global	__movstrSI24
+	.set	__movstrSI24, __movmemSI24
+__movmemSI24:
+	mov.l	@(20,r5),r0
+	mov.l	r0,@(20,r4)
+	.global	__movmemSI20
+	.global	__movstrSI20
+	.set	__movstrSI20, __movmemSI20
+__movmemSI20:
+	mov.l	@(16,r5),r0
+	mov.l	r0,@(16,r4)
+	.global	__movmemSI16
+	.global	__movstrSI16
+	.set	__movstrSI16, __movmemSI16
+__movmemSI16:
+	mov.l	@(12,r5),r0
+	mov.l	r0,@(12,r4)
+	.global	__movmemSI12
+	.global	__movstrSI12
+	.set	__movstrSI12, __movmemSI12
+__movmemSI12:
+	mov.l	@(8,r5),r0
+	mov.l	r0,@(8,r4)
+	.global	__movmemSI8
+	.global	__movstrSI8
+	.set	__movstrSI8, __movmemSI8
+__movmemSI8:
+	mov.l	@(4,r5),r0
+	mov.l	r0,@(4,r4)
+	.global	__movmemSI4
+	.global	__movstrSI4
+	.set	__movstrSI4, __movmemSI4
+__movmemSI4:
+	mov.l	@(0,r5),r0
+	rts
+	mov.l	r0,@(0,r4)
+
+	.global	__movmem_i4_even
+	.global	__movstr_i4_even
+	.set	__movstr_i4_even, __movmem_i4_even
+
+	.global	__movmem_i4_odd
+	.global	__movstr_i4_odd
+	.set	__movstr_i4_odd, __movmem_i4_odd
+
+	.global	__movmemSI12_i4
+	.global	__movstrSI12_i4
+	.set	__movstrSI12_i4, __movmemSI12_i4
+
+	.p2align	5
+L_movmem_2mod4_end:
+	mov.l	r0,@(16,r4)
+	rts
+	mov.l	r1,@(20,r4)
+
+	.p2align	2
+
+__movmem_i4_even:
+	mov.l	@r5+,r0
+	bra	L_movmem_start_even
+	mov.l	@r5+,r1
+
+__movmem_i4_odd:
+	mov.l	@r5+,r1
+	add	#-4,r4
+	mov.l	@r5+,r2
+	mov.l	@r5+,r3
+	mov.l	r1,@(4,r4)
+	mov.l	r2,@(8,r4)
+
+L_movmem_loop:
+	mov.l	r3,@(12,r4)
+	dt	r6
+	mov.l	@r5+,r0
+	bt/s	L_movmem_2mod4_end
+	mov.l	@r5+,r1
+	add	#16,r4
+L_movmem_start_even:
+	mov.l	@r5+,r2
+	mov.l	@r5+,r3
+	mov.l	r0,@r4
+	dt	r6
+	mov.l	r1,@(4,r4)
+	bf/s	L_movmem_loop
+	mov.l	r2,@(8,r4)
+	rts
+	mov.l	r3,@(12,r4)
+
+	.p2align	4
+__movmemSI12_i4:
+	mov.l	@r5,r0
+	mov.l	@(4,r5),r1
+	mov.l	@(8,r5),r2
+	mov.l	r0,@r4
+	mov.l	r1,@(4,r4)
+	rts
+	mov.l	r2,@(8,r4)

board/renesas/rsk7203/lowlevel_init.S

@@ -186,6 +186,7 @@ PCCRL2_D:	.word 0x1111
 .align 2
 PCCRL1_A:	.long 0xFFFE3916
 PCCRL1_D:	.word 0x1010
+.align 2
 PDCRL4_A:	.long 0xFFFE3990
 PDCRL4_D:	.word 0x0011
 .align 2

board/renesas/rsk7264/Makefile

+#
+# Copyright (C) 2011 Renesas Electronics Europe Ltd.
+#
+# This file is released under the terms of GPL v2 and any later version.
+# See the file COPYING in the root directory of the source tree for details.
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).o
+
+OBJS	:= rsk7264.o
+SOBJS	:= lowlevel_init.o
+
+LIB	:= $(addprefix $(obj),$(LIB))
+OBJS	:= $(addprefix $(obj),$(OBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend

board/renesas/rsk7264/lowlevel_init.S

+/*
+ * Copyright (C) 2011 Renesas Electronics Europe Ltd.
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu
+ *
+ * Based on board/renesas/rsk7203/lowlevel_init.S
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+	/* Cache setting */
+	write32	CCR1_A ,CCR1_D
+
+	/* io_set_cpg */
+	write8 STBCR3_A, STBCR3_D
+	write8 STBCR4_A, STBCR4_D
+	write8 STBCR5_A, STBCR5_D
+	write8 STBCR6_A, STBCR6_D
+	write8 STBCR7_A, STBCR7_D
+	write8 STBCR8_A, STBCR8_D
+
+	/* ConfigurePortPins */
+
+	/* Leaving LED1 ON for sanity test */
+	write16 PJCR1_A, PJCR1_D1
+	write16 PJCR2_A, PJCR2_D
+	write16 PJIOR0_A, PJIOR0_D1
+	write16 PJDR0_A, PJDR0_D
+	write16 PJPR0_A, PJPR0_D
+
+	/* Configure EN_PIN & RS_PIN */
+	write16 PGCR2_A, PGCR2_D
+	write16 PGIOR0_A, PGIOR0_D
+
+	/* Configure the port pins connected to UART */
+	write16 PJCR1_A, PJCR1_D2
+	write16 PJIOR0_A, PJIOR0_D2
+
+	/* Configure Operating Frequency */
+	write16	WTCSR_A, WTCSR_D0
+	write16	WTCSR_A, WTCSR_D1
+	write16	WTCNT_A, WTCNT_D
+
+	/* Control of RESBANK */
+	write16 IBNR_A, IBNR_D
+	/* Enable SCIF3 module */
+	write16 STBCR4_A, STBCR4_D
+
+	/* Set clock mode*/
+	write16	FRQCR_A, FRQCR_D
+
+	/* Configure Bus And Memory */
+init_bsc_cs0:
+
+pfc_settings:
+	write16 PCCR2_A, PCCR2_D
+	write16 PCCR1_A, PCCR1_D
+	write16 PCCR0_A, PCCR0_D
+
+	write16 PBCR0_A, PBCR0_D
+	write16 PBCR1_A, PBCR1_D
+	write16 PBCR2_A, PBCR2_D
+	write16 PBCR3_A, PBCR3_D
+	write16 PBCR4_A, PBCR4_D
+	write16 PBCR5_A, PBCR5_D
+
+	write16 PDCR0_A, PDCR0_D
+	write16 PDCR1_A, PDCR1_D
+	write16 PDCR2_A, PDCR2_D
+	write16 PDCR3_A, PDCR3_D
+
+	write32 CS0WCR_A, CS0WCR_D
+	write32 CS0BCR_A, CS0BCR_D
+
+init_bsc_cs2:
+	write16	PJCR0_A, PJCR0_D
+	write32	CS2WCR_A, CS2WCR_D
+
+init_sdram:
+	write32	CS3BCR_A, CS3BCR_D
+	write32	CS3WCR_A, CS3WCR_D
+	write32	SDCR_A, SDCR_D
+	write32	RTCOR_A, RTCOR_D
+	write32	RTCSR_A, RTCSR_D
+
+	/* wait 200us */
+	mov.l	REPEAT_D, r3
+	mov	#0, r2
+repeat0:
+	add	#1, r2
+	cmp/hs	r3, r2
+	bf	repeat0
+	nop
+
+	mov.l	SDRAM_MODE, r1
+	mov	#0, r0
+	mov.l	r0, @r1
+
+	nop
+	rts
+
+	.align 4
+
+CCR1_A:		.long CCR1
+CCR1_D:		.long 0x0000090B
+FRQCR_A:	.long 0xFFFE0010
+FRQCR_D:	.word 0x1003
+.align 2
+STBCR3_A:	.long 0xFFFE0408
+STBCR3_D:	.long 0x00000002
+STBCR4_A:	.long 0xFFFE040C
+STBCR4_D:	.word 0x0000
+.align 2
+STBCR5_A:	.long 0xFFFE0410
+STBCR5_D:	.long 0x00000010
+STBCR6_A:	.long 0xFFFE0414
+STBCR6_D:	.long 0x00000002
+STBCR7_A:	.long 0xFFFE0418
+STBCR7_D:	.long 0x0000002A
+STBCR8_A:	.long 0xFFFE041C
+STBCR8_D:	.long 0x0000007E
+PJCR1_A:	.long 0xFFFE390C
+PJCR1_D1:	.word 0x0000
+PJCR1_D2:	.word 0x0022
+PJCR2_A:	.long 0xFFFE390A
+PJCR2_D:	.word 0x0000
+.align 2
+PJIOR0_A:	.long 0xFFFE3912
+PJIOR0_D1:	.word 0x0FC0
+PJIOR0_D2:	.word 0x0FE0
+PJDR0_A:	.long 0xFFFE3916
+PJDR0_D:	.word 0x0FBF
+.align 2
+PJPR0_A:	.long 0xFFFE391A
+PJPR0_D:	.long 0x00000FBF
+PGCR2_A:	.long 0xFFFE38CA
+PGCR2_D:	.word 0x0000
+.align 2
+PGIOR0_A:	.long 0xFFFE38D2
+PGIOR0_D:	.word 0x03F0
+.align 2
+WTCSR_A:	.long 0xFFFE0000
+WTCSR_D0:	.word 0x0000
+WTCSR_D1:	.word 0x0000
+WTCNT_A:	.long 0xFFFE0002
+WTCNT_D:	.word 0x0000
+.align 2
+PCCR0_A:	.long 0xFFFE384E
+PDCR0_A:	.long 0xFFFE386E
+PDCR1_A:	.long 0xFFFE386C
+PDCR2_A:	.long 0xFFFE386A
+PDCR3_A:	.long 0xFFFE3868
+PBCR0_A:	.long 0xFFFE382E
+PBCR1_A:	.long 0xFFFE382C
+PBCR2_A:	.long 0xFFFE382A
+PBCR3_A:	.long 0xFFFE3828
+PBCR4_A:	.long 0xFFFE3826
+PBCR5_A:	.long 0xFFFE3824
+PCCR0_D:	.word 0x1111
+PDCR0_D:	.word 0x1111
+PDCR1_D:	.word 0x1111
+PDCR2_D:	.word 0x1111
+PDCR3_D:	.word 0x1111
+PBCR0_D:	.word 0x1110
+PBCR1_D:	.word 0x1111
+PBCR2_D:	.word 0x1111
+PBCR3_D:	.word 0x1111
+PBCR4_D:	.word 0x1111
+PBCR5_D:	.word 0x0111
+.align 2
+CS0WCR_A:	.long 0xFFFC0028
+CS0WCR_D:	.long 0x00000B41
+CS0BCR_A:	.long 0xFFFC0004
+CS0BCR_D:	.long 0x10000400
+PJCR0_A:	.long 0xFFFE390E
+PJCR0_D:	.word 0x0300
+.align 2
+CS2WCR_A:	.long 0xFFFC0030
+CS2WCR_D:	.long 0x00000B01
+PCCR2_A:	.long 0xFFFE384A
+PCCR2_D:	.word 0x0001
+.align 2
+PCCR1_A:	.long 0xFFFE384C
+PCCR1_D:	.word 0x1111
+.align 2
+CS3BCR_A:	.long 0xFFFC0010
+CS3BCR_D:	.long 0x00004400
+CS3WCR_A:	.long 0xFFFC0034
+CS3WCR_D:	.long 0x0000288A
+SDCR_A:		.long 0xFFFC004C
+SDCR_D:		.long 0x00000812
+RTCOR_A:	.long 0xFFFC0058
+RTCOR_D:	.long 0xA55A0046
+RTCSR_A:	.long 0xFFFC0050
+RTCSR_D:	.long 0xA55A0010
+IBNR_A:		.long 0xFFFE080E
+IBNR_D:	.word 0x0000
+.align 2
+SDRAM_MODE:	.long 0xFFFC5040
+REPEAT_D:	.long 0x00000085

board/renesas/rsk7264/rsk7264.c

+/*
+ * Copyright (C) 2011 Renesas Electronics Europe Ltd.
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu
+ *
+ * Based on u-boot/board/rsk7264/rsk7203.c
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("BOARD: Renesas Technology RSK7264\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+}
+
+/*
+ * The RSK board has the SMSC89218 wired up 'incorrectly'.
+ * Byte-swapping is necessary, and so poor performance is inevitable.
+ * This problem cannot evade by the swap function of CHIP, this can
+ * evade by software Byte-swapping.
+ * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
+ * functions necessary to solve this problem.
+ */
+u32 pkt_data_pull(struct eth_device *dev, u32 addr)
+{
+	volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
+	return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
+				| swab16(*(addr_16 + 1));
+}
+
+void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
+{
+	addr += dev->iobase;
+	*(volatile u16 *)(addr + 2) = swab16((u16)val);
+	*(volatile u16 *)(addr) = swab16((u16)(val >> 16));
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}

board/renesas/sh7757lcr/u-boot.lds

@@ -41,7 +41,7 @@ SECTIONS
 
 	.text :
 	{
-		arch/sh/cpu/sh4/start.o		(.text)
+		KEEP(arch/sh/cpu/sh4/start.o		(.text))
 		*(.spiboot1.text)
 		*(.spiboot2.text)
 		. = ALIGN(8192);

boards.cfg

@@ -868,6 +868,7 @@ xilinx-ppc405-generic_flash  powerpc     ppc4xx      ppc405-generic      xilinx
 xilinx-ppc440-generic        powerpc     ppc4xx      ppc440-generic      xilinx         -           xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1
 xilinx-ppc440-generic_flash  powerpc     ppc4xx      ppc440-generic      xilinx         -           xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC
 rsk7203                      sh          sh2         rsk7203             renesas        -
+rsk7264                      sh          sh2         rsk7264             renesas        -
 mpr2                         sh          sh3         mpr2                -              -
 ms7720se                     sh          sh3         ms7720se            -              -
 shmin                        sh          sh3         shmin               -              -

drivers/serial/serial_sh.h

@@ -177,7 +177,8 @@ struct uart_port {
 #elif defined(CONFIG_CPU_SH7201) || \
 	defined(CONFIG_CPU_SH7203) || \
 	defined(CONFIG_CPU_SH7206) || \
-	defined(CONFIG_CPU_SH7263)
+	defined(CONFIG_CPU_SH7263) || \
+	defined(CONFIG_CPU_SH7264)
 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
@@ -685,6 +686,8 @@ static inline int scbrr_calc(struct uart_port port, int bps, int clk)
 #define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
 #elif defined(__H8300H__) || defined(__H8300S__)
 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
+#elif defined(CONFIG_CPU_SH7264)
+#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps))
 #else /* Generic SH */
 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 #endif

include/configs/rsk7264.h

+/*
+ * Configuation settings for the Renesas RSK2+SH7264 board
+ *
+ * Copyright (C) 2011 Renesas Electronics Europe Ltd.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#ifndef __RSK7264_H
+#define __RSK7264_H
+
+#undef DEBUG
+#define CONFIG_SH		1
+#define CONFIG_SH2		1
+#define CONFIG_SH2A		1
+#define CONFIG_CPU_SH7264	1
+#define CONFIG_RSK7264		1
+
+#ifndef _CONFIG_CMD_DEFAULT_H
+# include <config_cmd_default.h>
+#endif
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTARGS		"console=ttySC3,115200"
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
+
+#define CONFIG_SYS_LONGHELP	1	/* undef to save memory	*/
+#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256	/* Buffer size for input from the Console */
+#define CONFIG_SYS_PBSIZE	256	/* Buffer size for Console output */
+#define CONFIG_SYS_MAXARGS	16	/* max args accepted for monitor commands */
+
+/* Serial */
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_CONS_SCIF3	1
+
+/* Memory */
+/* u-boot relocated to top 256KB of ram */
+#define CONFIG_SYS_TEXT_BASE		0x0CFC0000
+#define CONFIG_SYS_SDRAM_BASE		0x0C000000
+#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
+
+/* Flash */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH 	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_BASE		0x20000000 /* Non-cached */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET	(128 * 1024)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	33333333
+#define CMT_CLK_DIVIDER		32	/* 8 (default), 32, 128 or 512 */
+#define CONFIG_SYS_HZ		(CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
+
+/* Network interface */
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_SMC911X_BASE	0x28000000
+
+#endif	/* __RSK7264_H */