提交 bc493d91 编写于 作者: S Siva Durga Prasad Paladugu 提交者: Michal Simek

net: zynq_gem: Remove check for Versal

This patch removes check for Versal platform
in gem driver as it now supports clock setting
through clock framework.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
上级 95105089
......@@ -463,7 +463,6 @@ static int zynq_gem_init(struct udevice *dev)
break;
}
#if !defined(CONFIG_ARCH_VERSAL)
ret = clk_set_rate(&priv->clk, clk_rate);
if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
dev_err(dev, "failed to set tx clock rate\n");
......@@ -475,9 +474,6 @@ static int zynq_gem_init(struct udevice *dev)
dev_err(dev, "failed to enable tx clock\n");
return ret;
}
#else
debug("requested clk_rate %ld\n", clk_rate);
#endif
setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK);
......
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