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提交 bb656c68 编写于 作者: T Tom Rini
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ppc: Remove sbc8548 boards 

These boards have not been converted to CONFIG_DM_PCI by the deadline and are
also missing conversion to CONFIG_DM.  Remove them.

Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NTom Rini <trini@konsulko.com>
上级 68438623
隐藏空白更改
内联 并排
Showing with 0 addition and 1676 deletion
arch/powerpc/cpu/mpc85xx/Kconfig
浏览文件 @ bb656c68
......@@ -16,10 +16,6 @@ choice
prompt "Target select"
optional
config TARGET_SBC8548
bool "Support sbc8548"
select ARCH_MPC8548
config TARGET_SOCRATES
bool "Support socrates"
select ARCH_MPC8544
......@@ -1303,7 +1299,6 @@ source "board/freescale/t208xqds/Kconfig"
source "board/freescale/t208xrdb/Kconfig"
source "board/freescale/t4rdb/Kconfig"
source "board/keymile/Kconfig"
source "board/sbc8548/Kconfig"
source "board/socrates/Kconfig"
source "board/xes/xpedite520x/Kconfig"
source "board/xes/xpedite537x/Kconfig"
......
board/sbc8548/Kconfig 已删除 100644 → 0
浏览文件 @ 68438623
if TARGET_SBC8548
config SYS_BOARD
default "sbc8548"
config SYS_CONFIG_NAME
default "sbc8548"
endif
board/sbc8548/MAINTAINERS 已删除 100644 → 0
浏览文件 @ 68438623
SBC8548 BOARD
M: Paul Gortmaker <paul.gortmaker@windriver.com>
S: Maintained
F: board/sbc8548/
F: include/configs/sbc8548.h
F: configs/sbc8548_defconfig
F: configs/sbc8548_PCI_33_defconfig
F: configs/sbc8548_PCI_33_PCIE_defconfig
F: configs/sbc8548_PCI_66_defconfig
F: configs/sbc8548_PCI_66_PCIE_defconfig
board/sbc8548/Makefile 已删除 100644 → 0
浏览文件 @ 68438623
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2004-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2007 Wind River Systems Inc <www.windriver.com>.
# Added support for Wind River SBC8548 board
obj-y += sbc8548.o
obj-y += law.o
obj-y += tlb.o
obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
board/sbc8548/README 已删除 100644 → 0
浏览文件 @ 68438623
Intro:
======
The SBC8548 is a stand alone single board computer with a 1GHz
MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz
memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e,
and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC
ethernet connections.
U-Boot Configuration:
=====================
The following possible U-Boot configuration targets are available:
1) sbc8548_config
2) sbc8548_PCI_33_config
3) sbc8548_PCI_66_config
4) sbc8548_PCI_33_PCIE_config
5) sbc8548_PCI_66_PCIE_config
Generally speaking, most people should choose to use #5. Details
of each choice are listed below.
Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot
will be left empty (M66EN high), and so the board will operate with
a base clock of 66MHz. Note that you need both PCI enabled in U-Boot
and linux in order to have functional PCI under linux.
The second enables PCI support and builds for a 33MHz clock rate. Note
that if a 33MHz 32bit card is inserted in the slot, then the whole board
will clock down to a 33MHz base clock instead of the default 66MHz. This
will change the baud clocks and mess up your serial console output if you
were previously running at 66MHz. If you want to use a 33MHz PCI card,
then you should build a U-Boot with a _PCI_33_ config and store this
to flash prior to powering down the board and inserting the 33MHz PCI
card. [The above discussion assumes that the SW2[1-4] has not been changed
to reflect a different CCB:SYSCLK ratio]
The third option builds PCI support in, and leaves the clocking at the
default 66MHz. Options four and five are just repeats of option two
and three, but with PCI-e support enabled as well.
PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx
is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with
a 33MHz PCI configuration is currently untested.)
=> pci 0
Scanning PCI devices on bus 0
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
00.00.00 0x1057 0x0012 Processor 0x20
00.01.00 0x8086 0x1026 Network controller 0x00
=> pci 1
Scanning PCI devices on bus 1
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
01.00.00 0x1957 0x0012 Processor 0x20
=> pci 2
Scanning PCI devices on bus 2
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
02.00.00 0x1148 0x9e00 Network controller 0x00
=>
Memory Size and using SPD:
==========================
The default configuration uses hard coded memory configuration settings
for 256MB of DDR2 @400MHz. It does not by default use the DDR2 SPD
EEPROM data to read what memory is installed.
There is a hardware errata, which causes the older local bus SDRAM
SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so
that the SPD data can not be read reliably. You can test if your
board has the errata fix by running "i2c probe". If you see 0x53
as a valid device, it has been fixed. If you only see 0x50, 0x51
then your board does not have the fix.
You can also visually inspect the board to see if this hardware
fix has been applied:
1) Remove R314 (RES-R0174-033, 1K, 0603). R314 is located on
the back of the PCB behind the DDR SDRAM SODIMM connector.
2) Solder RES-R0174-033 (1K, 0603) resistor from R314 pin 2 pad
to R313 pin 2. Pin 2 for each resistor is the end of the
resistor closest to the CPU.
Boards without the mod will have R314 and R313 in parallel, like "||".
After the mod, they will be touching and form an "L" shape.
If you want to upgrade to larger RAM size, you can simply enable
#define CONFIG_SPD_EEPROM
#define CONFIG_DDR_SPD
in include/configs/sbc8548.h file. (The lines are already there
but listed as #undef).
If you did the i2c test, and your board does not have the errata
fix, then you will have to physically remove the LBC 128MB DIMM
from the board's socket to resolve the above i2c address overlap
issue and allow SPD autodetection of RAM to work.
Updating U-Boot with U-Boot:
============================
Note that versions of U-Boot up to and including 2009.08 had U-Boot stored
at 0xfff8_0000 -> 0xffff_ffff (512k). Currently it is being stored from
0xfffa_0000 -> 0xffff_ffff (384k). If you use an old macro/script to
update U-Boot with U-Boot and it uses the old address, you will render
your board inoperable, and you will require JTAG recovery.
The following steps list how to update with the current address:
tftp u-boot.bin
md 200000 10
protect off all
erase fffa0000 ffffffff
cp.b 200000 fffa0000 60000
md fffa0000 10
protect on all
The "md" steps in the above are just a precautionary step that allow
you to confirm the U-Boot version that was downloaded, and then confirm
that it was copied to flash.
The above assumes that you are using the default board settings which
have U-Boot in the 8MB flash, tied to /CS0.
If you are running the default 8MB /CS0 settings but want to store an
image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled,
(as a backup, etc) then the steps will become:
tftp u-boot.bin
md 200000 10
protect off all
era eff00000 efffffff
cp.b 200000 eff00000 100000
md eff00000 10
protect on all
Finally, if you are running the alternate 64MB /CS0 settings and want
to update the in-use U-Boot image, then (again with CONFIG_SYS_ALT_BOOT
enabled) the steps will become:
tftp u-boot.bin
md 200000 10
protect off all
era fff00000 ffffffff
cp.b 200000 fff00000 100000
md fff00000 10
protect on all
Hardware Reference:
===================
The following contains some summary information on hardware settings
that are relevant to U-Boot, based on the board manual. For the
most up to date and complete details of the board, please request the
reference manual ERG-00327-001.pdf from www.windriver.com
Boot flash:
intel V28F640Jx, 8192x8 (one device) at 0xff80_0000
Sodimm flash:
intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000
Note that this address reflects the default setting for
the JTAG debugging tools, but since the alignment is
rather inconvenient, U-Boot puts it at 0xec00_0000.
Jumpers:
Jumper Name ON OFF
----------------------------------------------------------------
JP12 CS0/CS6 swap see note[*] see note[*]
JP13 SODIMM flash write OK writes disabled
write prot.
JP14 HRESET/TRST joined isolated
JP15 PWR ON when AC pwr use S1 for on/off
JP16 Demo LEDs lit not lit
JP19 PCI mode PCI PCI-X
[*]JP12, when jumpered parallel to the SODIMM, puts the boot flash
onto /CS0 and the SODIMM flash on /CS6 (default). When JP12
is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
SODIMM flash and /CS6 is for the boot flash. Note that in this
alternate setting, you also need to switch SW2.8 to ON.
See the setting CONFIG_SYS_ALT_BOOT if you want to use this setting
and boot U-Boot from the 64MB SODIMM
Switches:
The defaults are marked with a *
Name Desc. ON OFF
------------------------------------------------------------------
S1 Pwr toggle n/a n/a
SW2.1 CFG_SYS_PLL0 1 0*
SW2.2 CFG_SYS_PLL1 1* 0
SW2.3 CFG_SYS_PLL2 1* 0
SW2.4 CFG_SYS_PLL3 1 0*
SW2.5 CFG_CORE_PLL0 1* 0
SW2.6 CFG_CORE_PLL1 1 0*
SW2.7 CFG_CORE_PLL2 1* 0
SW2.8 CFG_ROM_LOC1 1 0*
SW3.1 CFG_HOST_AGT0 1* 0
SW3.2 CFG_HOST_AGT1 1* 0
SW3.3 CFG_HOST_AGT2 1* 0
SW3.4 CFG_IO_PORTS0 1* 0
SW3.5 CFG_IO_PORTS0 1 0*
SW3.6 CFG_IO_PORTS0 1 0*
SerDes CLK(MHz) SW5.1 SW5.2
----------------------------------------------
25 0 0
100* 1 0
125 0 1
200 1 1
SerDes CLK spread SW5.3 SW5.4
----------------------------------------------
+/- 0.25% 0 0
-0.50% 1 0
-0.75% 0 1
No Spread* 1 1
SW4 settings are readable from the EPLD and are currently not used for
any hardware settings (i.e. user configuration switches).
LEDs:
Name Desc. ON OFF
------------------------------------------------------------------
D13 PCI/PCI-X PCI-X PCI
D14 3.3V PWR 3.3V no power
D15 SYSCLK 66MHz 33MHz
Default Memory Map:
start end CS<n> width Desc.
----------------------------------------------------------------------
0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB)
f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB)
f800_0000 f8b0_1fff CS5 - EPLD
fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) [*]
ff80_0000 ffff_ffff CS0 8 Boot flash (8MB)
[*] fb80 represents the default programmed by WR JTAG register files,
but U-Boot places the flash at either ec00 or fc00 based on JP12.
The EPLD on CS5 demuxes the following devices at the following offsets:
offset size width device
--------------------------------------------------------
0 1fff 8 7 segment display LED
10_0000 1fff 4 user switches
30_0000 1fff 4 HW Rev. register
b0_0000 1fff 8 8kB EEPROM
board/sbc8548/ddr.c 已删除 100644 → 0
浏览文件 @ 68438623
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <i2c.h>
#include <linux/delay.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
/*
* Factors to consider for clock adjust:
* - number of chips on bus
* - position of slot
* - DDR1 vs. DDR2?
* - ???
*
* This needs to be determined on a board-by-board basis.
* 0110 3/4 cycle late
* 0111 7/8 cycle late
*/
popts->clk_adjust = 7;
/*
* Factors to consider for CPO:
* - frequency
* - ddr1 vs. ddr2
*/
popts->cpo_override = 10;
/*
* Factors to consider for write data delay:
* - number of DIMMs
*
* 1 = 1/4 clock delay
* 2 = 1/2 clock delay
* 3 = 3/4 clock delay
* 4 = 1 clock delay
* 5 = 5/4 clock delay
* 6 = 3/2 clock delay
*/
popts->write_data_delay = 3;
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
}
#ifdef CONFIG_SPD_EEPROM
/*
* Workaround for hardware errata. An i2c address conflict
* existed on earlier boards; the workaround moved the DDR
* SPD from 0x51 to 0x53. So we try and read 0x53 1st, and
* if that fails, then fall back to reading at 0x51.
*/
void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
{
int ret;
#ifdef ALT_SPD_EEPROM_ADDRESS
if (i2c_address == SPD_EEPROM_ADDRESS) {
ret = i2c_read(ALT_SPD_EEPROM_ADDRESS, 0, 1, (uchar *)spd,
sizeof(generic_spd_eeprom_t));
if (ret == 0)
return; /* Good data at 0x53 */
memset(spd, 0, sizeof(generic_spd_eeprom_t));
}
#endif
ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
sizeof(generic_spd_eeprom_t));
if (ret) {
printf("DDR: failed to read SPD from addr %u\n", i2c_address);
memset(spd, 0, sizeof(generic_spd_eeprom_t));
}
}
#else
/*
* fixed_sdram init -- doesn't use serial presence detect.
* Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
*/
phys_size_t fixed_sdram(void)
{
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
out_be32(&ddr->cs0_bnds, 0x0000007f);
out_be32(&ddr->cs1_bnds, 0x008000ff);
out_be32(&ddr->cs2_bnds, 0x00000000);
out_be32(&ddr->cs3_bnds, 0x00000000);
out_be32(&ddr->cs0_config, 0x80010101);
out_be32(&ddr->cs1_config, 0x80010101);
out_be32(&ddr->cs2_config, 0x00000000);
out_be32(&ddr->cs3_config, 0x00000000);
out_be32(&ddr->timing_cfg_3, 0x00000000);
out_be32(&ddr->timing_cfg_0, 0x00220802);
out_be32(&ddr->timing_cfg_1, 0x38377322);
out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
out_be32(&ddr->sdram_cfg, 0x4300C000);
out_be32(&ddr->sdram_cfg_2, 0x24401000);
out_be32(&ddr->sdram_mode, 0x23C00542);
out_be32(&ddr->sdram_mode_2, 0x00000000);
out_be32(&ddr->sdram_interval, 0x05080100);
out_be32(&ddr->sdram_md_cntl, 0x00000000);
out_be32(&ddr->sdram_data_init, 0x00000000);
out_be32(&ddr->sdram_clk_cntl, 0x03800000);
asm("sync;isync;msync");
udelay(500);
#ifdef CONFIG_DDR_ECC
/* Enable ECC checking */
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
#else
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
#endif
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif
board/sbc8548/law.c 已删除 100644 → 0
浏览文件 @ 68438623
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
/*
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x0fff_ffff DDR 256M
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xa000_0000 0xbfff_ffff PCIe MEM 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
* 0xe200_0000 0xe27f_ffff PCI1 IO 8M
* 0xe280_0000 0xe2ff_ffff PCIe IO 8M
* 0xec00_0000 0xefff_ffff FLASH (2nd bank) 64M
* 0xf000_0000 0xf7ff_ffff SDRAM 128M
* 0xf8b0_0000 0xf80f_ffff EEPROM 1M
* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
*
* If swapped CS0/CS6 via JP12+SW2.8:
* 0xef80_0000 0xefff_ffff FLASH (2nd bank) 8M
* 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M
*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
struct law_entry law_table[] = {
#ifdef CONFIG_SYS_ALT_BOOT
SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
#else
SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
#endif
#ifndef CONFIG_SPD_EEPROM
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
#endif
#ifdef CONFIG_SYS_LBC_SDRAM_BASE
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
#else
/* LBC window - maps 128M 0xf8000000 -> 0xffffffff */
SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
board/sbc8548/sbc8548.c 已删除 100644 → 0
浏览文件 @ 68438623
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
*
* Copyright 2007 Embedded Specialties, Inc.
*
* Copyright 2004, 2007 Freescale Semiconductor.
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*/
#include <common.h>
#include <init.h>
#include <log.h>
#include <net.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <spd_sdram.h>
#include <netdev.h>
#include <tsec.h>
#include <miiphy.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
void local_bus_init(void);
int board_early_init_f (void)
{
return 0;
}
int checkboard (void)
{
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
in_8(rev) >> 4);
/*
* Initialize local bus.
*/
local_bus_init ();
out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
return 0;
}
/*
* Initialize Local Bus
*/
void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
sys_info_t sysinfo;
get_sys_info(&sysinfo);
lbc_mhz = sysinfo.freq_localbus / 1000000;
clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;
debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
out_be32(&gur->lbiuiplldcr1, 0x00078080);
if (clkdiv == 16) {
out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
} else if (clkdiv == 8) {
out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
} else if (clkdiv == 4) {
out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
}
/*
* Local Bus Clock > 83.3 MHz. According to timing
* specifications set LCRR[EADC] to 2 delay cycles.
*/
if (lbc_mhz > 83) {
lcrr &= ~LCRR_EADC;
lcrr |= LCRR_EADC_2;
}
/*
* According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
* disable PLL bypass for Local Bus Clock > 83 MHz.
*/
if (lbc_mhz >= 66)
lcrr &= (~LCRR_DBYP); /* DLL Enabled */
else
lcrr |= LCRR_DBYP; /* DLL Bypass */
out_be32(&lbc->lcrr, lcrr);
asm("sync;isync;msync");
/*
* According to MPC8548ERMAD Rev.1.3 read back LCRR
* and terminate with isync
*/
lcrr = in_be32(&lbc->lcrr);
asm ("isync;");
/* let DLL stabilize */
udelay(500);
out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
}
/*
* Initialize SDRAM memory on the Local Bus.
*/
void lbc_sdram_init(void)
{
#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
uint idx;
const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
puts(" SDRAM: ");
print_size(size, "\n");
/*
* Setup SDRAM Base and Option Registers
*/
set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
asm("msync");
out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
asm("msync");
/*
* Issue PRECHARGE ALL command.
*/
out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
*sdram_addr2 = 0xff;
ppcDcbf((unsigned long) sdram_addr2);
udelay(100);
/*
* Issue 8 AUTO REFRESH commands.
*/
for (idx = 0; idx < 8; idx++) {
out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
*sdram_addr2 = 0xff;
ppcDcbf((unsigned long) sdram_addr2);
udelay(100);
}
/*
* Issue 8 MODE-set command.
*/
out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
*sdram_addr2 = 0xff;
ppcDcbf((unsigned long) sdram_addr2);
udelay(100);
/*
* Issue RFEN command.
*/
out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
*sdram_addr2 = 0xff;
ppcDcbf((unsigned long) sdram_addr2);
udelay(200); /* Overkill. Must wait > 200 bus cycles */
#endif /* enable SDRAM init */
}
#if defined(CONFIG_SYS_DRAM_TEST)
int
testdram(void)
{
uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
uint *p;
printf("Testing DRAM from 0x%08x to 0x%08x\n",
CONFIG_SYS_MEMTEST_START,
CONFIG_SYS_MEMTEST_END);
printf("DRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("DRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("DRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("DRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("DRAM test passed.\n");
return 0;
}
#endif
#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif /* CONFIG_PCI1 */
#ifdef CONFIG_PCI
void
pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int first_free_busno = 0;
#ifdef CONFIG_PCI1
struct fsl_pci_info pci_info;
u32 devdisr = in_be32(&gur->devdisr);
u32 pordevsr = in_be32(&gur->pordevsr);
u32 porpllsr = in_be32(&gur->porpllsr);
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
(pci_32) ? 32 : 64,
(pci_speed == 33000000) ? "33" :
(pci_speed == 66000000) ? "66" : "unknown",
pci_clk_sel ? "sync" : "async",
pci_arb ? "arbiter" : "external-arbiter");
SET_STD_PCI_INFO(pci_info, 1);
set_next_law(pci_info.mem_phys,
law_size_bits(pci_info.mem_size), pci_info.law);
set_next_law(pci_info.io_phys,
law_size_bits(pci_info.io_size), pci_info.law);
first_free_busno = fsl_pci_init_port(&pci_info,
&pci1_hose, first_free_busno);
} else {
printf("PCI: disabled\n");
}
puts("\n");
#else
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
fsl_pcie_init_board(first_free_busno);
}
#endif
int board_eth_init(struct bd_info *bis)
{
tsec_standard_init(bis);
pci_eth_init(bis);
return 0; /* otherwise cpu_eth_init gets run */
}
int last_stage_init(void)
{
return 0;
}
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_FSL_PCI_INIT
FT_FSL_PCI_SETUP;
#endif
return 0;
}
#endif
board/sbc8548/tlb.c 已删除 100644 → 0
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/*
* TLB 0: 64M Non-cacheable, guarded
* 0xfc000000 56M unused
* 0xff800000 8M boot FLASH
* .... or ....
* 0xfc000000 64M user flash
*
* Out of reset this entry is only 4K.
*/
SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_64M, 1),
/*
* TLB 1: 1G Non-cacheable, guarded
* 0x80000000 512M PCI1 MEM
* 0xa0000000 512M PCIe MEM
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1G, 1),
/*
* TLB 2: 64M Non-cacheable, guarded
* 0xe0000000 1M CCSRBAR
* 0xe2000000 8M PCI1 IO
* 0xe2800000 8M PCIe IO
*/
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_64M, 1),
#ifdef CONFIG_SYS_LBC_SDRAM_BASE
/*
* TLB 3: 64M Cacheable, non-guarded
* 0xf0000000 64M LBC SDRAM First half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 3, BOOKE_PAGESZ_64M, 1),
/*
* TLB 4: 64M Cacheable, non-guarded
* 0xf4000000 64M LBC SDRAM Second half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 4, BOOKE_PAGESZ_64M, 1),
#endif
/*
* TLB 5: 16M Cacheable, non-guarded
* 0xf8000000 1M 7-segment LED display
* 0xf8100000 1M User switches
* 0xf8300000 1M Board revision
* 0xf8b00000 1M EEPROM
*/
SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_16M, 1),
#ifndef CONFIG_SYS_ALT_BOOT
/*
* TLB 6: 64M Non-cacheable, guarded
* 0xec000000 64M 64MB user FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
#else
/*
* TLB 6: 4M Non-cacheable, guarded
* 0xef800000 4M 1st 1/2 8MB soldered FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_4M, 1),
/*
* TLB 7: 4M Non-cacheable, guarded
* 0xefc00000 4M 2nd half 8MB soldered FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
CONFIG_SYS_ALT_FLASH + 0x400000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_4M, 1),
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
configs/sbc8548_PCI_33_PCIE_defconfig 已删除 100644 → 0
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CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFFA0000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_SBC8548=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="33,PCIE"
CONFIG_BOOTDELAY=10
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_MISC_INIT_R is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
# CONFIG_CMD_IRQ is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0xFFFE0000
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
configs/sbc8548_PCI_33_defconfig 已删除 100644 → 0
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CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFFA0000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_SBC8548=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="33"
CONFIG_BOOTDELAY=10
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_MISC_INIT_R is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
# CONFIG_CMD_IRQ is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0xFFFE0000
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
configs/sbc8548_PCI_66_PCIE_defconfig 已删除 100644 → 0
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CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFFA0000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_SBC8548=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="66,PCIE"
CONFIG_BOOTDELAY=10
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_MISC_INIT_R is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
# CONFIG_CMD_IRQ is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0xFFFE0000
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
configs/sbc8548_PCI_66_defconfig 已删除 100644 → 0
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CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFFA0000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_SBC8548=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="66"
CONFIG_BOOTDELAY=10
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_MISC_INIT_R is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
# CONFIG_CMD_IRQ is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0xFFFE0000
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
configs/sbc8548_defconfig 已删除 100644 → 0
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CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFFA0000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_SBC8548=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_MISC_INIT_R is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
# CONFIG_CMD_IRQ is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0xFFFE0000
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
include/configs/sbc8548.h 已删除 100644 → 0
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2007,2009 Wind River Systems <www.windriver.com>
* Copyright 2007 Embedded Specialties, Inc.
* Copyright 2004, 2007 Freescale Semiconductor.
*/
/*
* sbc8548 board configuration file
* Please refer to board/sbc8548/README for more info.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <linux/stringify.h>
/*
* Top level Makefile configuration choices
*/
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI1
#endif
#ifdef CONFIG_66
#define CONFIG_SYS_CLK_DIV 1
#endif
#ifdef CONFIG_33
#define CONFIG_SYS_CLK_DIV 2
#endif
#ifdef CONFIG_PCIE
#define CONFIG_PCIE1
#endif
/*
* High Level Configuration Options
*/
/*
* If you want to boot from the SODIMM flash, instead of the soldered
* on flash, set this, and change JP12, SW2:8 accordingly.
*/
#undef CONFIG_SYS_ALT_BOOT
#undef CONFIG_RIO
#ifdef CONFIG_PCI
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#endif
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
/*
* Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
*/
#ifndef CONFIG_SYS_CLK_DIV
#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */
#endif
#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV)
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
/*
* Only possible on E500 Version 2 or newer cores.
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_CCSRBAR 0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
/*
* A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
* to collide, meaning you couldn't reliably read either. So
* physically remove the LBC PC100 SDRAM module from the board
* before enabling the two SPD options below, or check that you
* have the hardware fix on your board via "i2c probe" and looking
* for a device at 0x53.
*/
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_SPD
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
/*
* The hardware fix for the I2C address collision puts the DDR
* SPD at 0x53, but if we are running on an older board w/o the
* fix, it will still be at 0x51. We check 0x53 1st.
*/
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
#define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */
/*
* Make sure required options are set
*/
#ifndef CONFIG_SPD_EEPROM
#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
#define CONFIG_SYS_DDR_CONTROL 0xc300c000
#endif
/*
* FLASH on the Local Bus
* Two banks, one 8MB the other 64MB, using the CFI driver.
* JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
* CS0 the 8MB boot flash, and CS6 the 64MB flash.
*
* Default:
* ec00_0000 efff_ffff 64MB SODIMM
* ff80_0000 ffff_ffff 8MB soldered flash
*
* Alternate:
* ef80_0000 efff_ffff 8MB soldered flash
* fc00_0000 ffff_ffff 64MB SODIMM
*
* BR0_8M:
* Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
* Port Size = 8 bits = BRx[19:20] = 01
* Use GPCM = BRx[24:26] = 000
* Valid = BRx[31] = 1
*
* BR0_64M:
* Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
* Port Size = 32 bits = BRx[19:20] = 11
*
* 0 4 8 12 16 20 24 28
* 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M
* 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M
*/
#define CONFIG_SYS_BR0_8M 0xff800801
#define CONFIG_SYS_BR0_64M 0xfc001801
/*
* BR6_8M:
* Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
* Port Size = 8 bits = BRx[19:20] = 01
* Use GPCM = BRx[24:26] = 000
* Valid = BRx[31] = 1
* BR6_64M:
* Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
* Port Size = 32 bits = BRx[19:20] = 11
*
* 0 4 8 12 16 20 24 28
* 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M
* 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M
*/
#define CONFIG_SYS_BR6_8M 0xef800801
#define CONFIG_SYS_BR6_64M 0xec001801
/*
* OR0_8M:
* Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
* XAM = OR0[17:18] = 11
* CSNT = OR0[20] = 1
* ACS = half cycle delay = OR0[21:22] = 11
* SCY = 6 = OR0[24:27] = 0110
* TRLX = use relaxed timing = OR0[29] = 1
* EAD = use external address latch delay = OR0[31] = 1
*
* OR0_64M:
* Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
*
*
* 0 4 8 12 16 20 24 28
* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M
* 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M
*/
#define CONFIG_SYS_OR0_8M 0xff806e65
#define CONFIG_SYS_OR0_64M 0xfc006e65
/*
* OR6_8M:
* Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
* XAM = OR6[17:18] = 11
* CSNT = OR6[20] = 1
* ACS = half cycle delay = OR6[21:22] = 11
* SCY = 6 = OR6[24:27] = 0110
* TRLX = use relaxed timing = OR6[29] = 1
* EAD = use external address latch delay = OR6[31] = 1
*
* OR6_64M:
* Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
*
* 0 4 8 12 16 20 24 28
* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M
* 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M
*/
#define CONFIG_SYS_OR6_8M 0xff806e65
#define CONFIG_SYS_OR6_64M 0xfc006e65
#ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */
#define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
#define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M
#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M
#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M
#else /* JP12 in alternate position */
#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */
#define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M
#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M
#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M
#endif
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
CONFIG_SYS_ALT_FLASH}
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* CS5 = Local bus peripherals controlled by the EPLD */
#define CONFIG_SYS_BR5_PRELIM 0xf8000801
#define CONFIG_SYS_OR5_PRELIM 0xff006e65
#define CONFIG_SYS_EPLD_BASE 0xf8000000
#define CONFIG_SYS_LED_DISP_BASE 0xf8000000
#define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000
#define CONFIG_SYS_BD_REV 0xf8300000
#define CONFIG_SYS_EEPROM_BASE 0xf8b00000
/*
* SDRAM on the Local Bus (CS3 and CS4)
* Note that most boards have a hardware errata where both the
* LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
* to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
* A hardware workaround is also available, see README.sbc8548 file.
*/
#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
/*
* Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
*
* For BR3, need:
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
* port-size = 32-bits = BR2[19:20] = 11
* no parity checking = BR2[21:22] = 00
* SDRAM for MSEL = BR2[24:26] = 011
* Valid = BR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
*
*/
#define CONFIG_SYS_BR3_PRELIM 0xf0001861
/*
* The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
*
* For OR3, need:
* 64MB mask for AM, OR3[0:7] = 1111 1100
* XAM, OR3[17:18] = 11
* 10 columns OR3[19-21] = 011
* 12 rows OR3[23-25] = 011
* EAD set for extra time OR[31] = 0
*
* 0 4 8 12 16 20 24 28
* 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
*/
#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
/*
* Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
* The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
*
* For BR4, need:
* Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
* port-size = 32-bits = BR2[19:20] = 11
* no parity checking = BR2[21:22] = 00
* SDRAM for MSEL = BR2[24:26] = 011
* Valid = BR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
*
*/
#define CONFIG_SYS_BR4_PRELIM 0xf4001861
/*
* The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
*
* For OR4, need:
* 64MB mask for AM, OR3[0:7] = 1111 1100
* XAM, OR3[17:18] = 11
* 10 columns OR3[19-21] = 011
* 12 rows OR3[23-25] = 011
* EAD set for extra time OR[31] = 0
*
* 0 4 8 12 16 20 24 28
* 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
*/
#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
#define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
/*
* Common settings for all Local Bus SDRAM commands.
*/
#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
| LSDMR_BSMA1516 \
| LSDMR_PRETOACT3 \
| LSDMR_ACTTORW3 \
| LSDMR_BUFCMD \
| LSDMR_BL8 \
| LSDMR_WRC2 \
| LSDMR_CL3 \
)
#define CONFIG_SYS_LBC_LSDMR_PCHALL \
(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
#define CONFIG_SYS_LBC_LSDMR_ARFRSH \
(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_MRW \
(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
#define CONFIG_SYS_LBC_LSDMR_RFEN \
(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN)
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
* For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
* one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM
* flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
* (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right
* thing for MONITOR_LEN in both cases.
*/
#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
/*
* I2C
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
#ifdef CONFIG_PCIE1
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
#endif
#ifdef CONFIG_RIO
/*
* RapidIO MMU
*/
#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
#endif
#if defined(CONFIG_PCI)
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC1"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0x19
#define TSEC2_PHY_ADDR 0x1a
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: eTSEC[0-3] */
#define CONFIG_ETHPRIME "eTSEC0"
#endif /* CONFIG_TSEC_ENET */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#endif
/*
* Environment Configuration
*/
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif
#define CONFIG_IPADDR 192.168.0.55
#define CONFIG_HOSTNAME "sbc8548"
#define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx"
#define CONFIG_BOOTFILE "/uImage"
#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */
#define CONFIG_SERVERIP 192.168.0.2
#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=uRamdisk\0" \
"fdtaddr=1e00000\0" \
"fdtfile=sbc8548.dtb\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
#endif /* __CONFIG_H */
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