Merge tag 'uniphier-v2020.10-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier

UniPhier SoC updates for v2020.10 (2nd)

 - minor code cleanups

 - sync DT with Linux

arch/arm/dts/uniphier-ld11-global.dts

@@ -157,7 +157,7 @@
 };
 
 &mdio {
-	ethphy: ethphy@1 {
+	ethphy: ethernet-phy@1 {
 		reg = <1>;
 	};
 };

arch/arm/dts/uniphier-ld11-ref.dts

@@ -20,7 +20,7 @@
 
 	aliases {
 		serial0 = &serial0;
-		serial1 = &serial1;
+		serial1 = &serialsc;
 		serial2 = &serial2;
 		serial3 = &serial3;
 		i2c0 = &i2c0;
@@ -42,6 +42,10 @@
 	interrupts = <0 8>;
 };
 
+&serialsc {
+	interrupts = <0 8>;
+};
+
 &serial0 {
 	status = "okay";
 };
@@ -76,7 +80,7 @@
 };
 
 &mdio {
-	ethphy: ethphy@1 {
+	ethphy: ethernet-phy@1 {
 		reg = <1>;
 	};
 };

arch/arm/dts/uniphier-ld20-global.dts

@@ -141,7 +141,7 @@
 };
 
 &mdio {
-	ethphy: ethphy@1 {
+	ethphy: ethernet-phy@1 {
 		reg = <1>;
 	};
 };

arch/arm/dts/uniphier-ld20-ref.dts

@@ -20,7 +20,7 @@
 
 	aliases {
 		serial0 = &serial0;
-		serial1 = &serial1;
+		serial1 = &serialsc;
 		serial2 = &serial2;
 		serial3 = &serial3;
 		i2c0 = &i2c0;
@@ -42,6 +42,10 @@
 	interrupts = <0 8>;
 };
 
+&serialsc {
+	interrupts = <0 8>;
+};
+
 &serial0 {
 	status = "okay";
 };
@@ -64,7 +68,7 @@
 };
 
 &mdio {
-	ethphy: ethphy@0 {
+	ethphy: ethernet-phy@0 {
 		reg = <0>;
 	};
 };

arch/arm/dts/uniphier-ld20.dtsi

@@ -955,7 +955,9 @@
 			compatible = "socionext,uniphier-ld20-pcie-phy";
 			reg = <0x66038000 0x4000>;
 			#phy-cells = <0>;
+			clock-names = "link";
 			clocks = <&sys_clk 24>;
+			reset-names = "link";
 			resets = <&sys_rst 24>;
 			socionext,syscon = <&soc_glue>;
 		};

arch/arm/dts/uniphier-ld4-ref.dts

@@ -20,7 +20,7 @@
 
 	aliases {
 		serial0 = &serial0;
-		serial1 = &serial1;
+		serial1 = &serialsc;
 		serial2 = &serial2;
 		serial3 = &serial3;
 		i2c0 = &i2c0;
@@ -39,6 +39,10 @@
 	interrupts = <1 8>;
 };
 
+&serialsc {
+	interrupts = <1 8>;
+};
+
 &serial0 {
 	status = "okay";
 };

arch/arm/dts/uniphier-ld6b-ref.dts

@@ -22,6 +22,7 @@
 		serial0 = &serial0;
 		serial1 = &serial1;
 		serial2 = &serial2;
+		serial3 = &serialsc;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		i2c2 = &i2c2;
@@ -42,6 +43,10 @@
 	interrupts = <4 8>;
 };
 
+&serialsc {
+	interrupts = <4 8>;
+};
+
 &serial0 {
 	status = "okay";
 };
@@ -76,7 +81,7 @@
 };
 
 &mdio {
-	ethphy: ethphy@0 {
+	ethphy: ethernet-phy@0 {
 		reg = <0>;
 	};
 };

arch/arm/dts/uniphier-pinctrl.dtsi

@@ -126,6 +126,11 @@
 		function = "nand";
 	};
 
+	pinctrl_pcie: pcie {
+		groups = "pcie";
+		function = "pcie";
+	};
+
 	pinctrl_sd: sd {
 		groups = "sd";
 		function = "sd";

arch/arm/dts/uniphier-pro4-ace.dts

@@ -87,7 +87,7 @@
 };
 
 &mdio {
-	ethphy: ethphy@1 {
+	ethphy: ethernet-phy@1 {
 		reg = <1>;
 	};
 };

arch/arm/dts/uniphier-pro4-ref.dts

@@ -22,7 +22,7 @@
 		serial0 = &serial0;
 		serial1 = &serial1;
 		serial2 = &serial2;
-		serial3 = &serial3;
+		serial3 = &serialsc;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		i2c2 = &i2c2;
@@ -43,6 +43,10 @@
 	interrupts = <2 8>;
 };
 
+&serialsc {
+	interrupts = <2 8>;
+};
+
 &serial0 {
 	status = "okay";
 };
@@ -85,7 +89,7 @@
 };
 
 &mdio {
-	ethphy: ethphy@0 {
+	ethphy: ethernet-phy@0 {
 		reg = <0>;
 	};
 };

arch/arm/dts/uniphier-pro4-sanji.dts

@@ -25,6 +25,7 @@
 		i2c3 = &i2c3;
 		i2c5 = &i2c5;
 		i2c6 = &i2c6;
+		ethernet0 = ð
 	};
 
 	memory@80000000 {
@@ -81,7 +82,7 @@
 };
 
 &mdio {
-	ethphy: ethphy@1 {
+	ethphy: ethernet-phy@1 {
 		reg = <1>;
 	};
 };

arch/arm/dts/uniphier-pro5.dtsi

@@ -465,40 +465,182 @@
 			};
 		};
 
-		usb0: usb@65b00000 {
-			compatible = "socionext,uniphier-pro5-dwc3";
+		usb0: usb@65a00000 {
+			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
 			status = "disabled";
-			reg = <0x65b00000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
+			reg = <0x65a00000 0xcd00>;
+			interrupt-names = "host";
+			interrupts = <0 134 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_usb0>;
-			dwc3@65a00000 {
-				compatible = "snps,dwc3";
-				reg = <0x65a00000 0x10000>;
-				interrupts = <0 134 4>;
+			clock-names = "ref", "bus_early", "suspend";
+			clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
+			resets = <&usb0_rst 15>;
+			phys = <&usb0_hsphy0>, <&usb0_ssphy0>;
 			dr_mode = "host";
-				tx-fifo-resize;
-			};
 		};
 
-		usb1: usb@65d00000 {
-			compatible = "socionext,uniphier-pro5-dwc3";
-			status = "disabled";
-			reg = <0x65d00000 0x1000>;
+		usb-glue@65b00000 {
+			compatible = "socionext,uniphier-pro5-dwc3-glue",
+				     "simple-mfd";
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges;
+			ranges = <0 0x65b00000 0x400>;
+
+			usb0_rst: reset@0 {
+				compatible = "socionext,uniphier-pro5-usb3-reset";
+				reg = <0x0 0x4>;
+				#reset-cells = <1>;
+				clock-names = "gio", "link";
+				clocks = <&sys_clk 12>, <&sys_clk 14>;
+				reset-names = "gio", "link";
+				resets = <&sys_rst 12>, <&sys_rst 14>;
+			};
+
+			usb0_vbus0: regulator@100 {
+				compatible = "socionext,uniphier-pro5-usb3-regulator";
+				reg = <0x100 0x10>;
+				clock-names = "gio", "link";
+				clocks = <&sys_clk 12>, <&sys_clk 14>;
+				reset-names = "gio", "link";
+				resets = <&sys_rst 12>, <&sys_rst 14>;
+			};
+
+			usb0_hsphy0: hs-phy@280 {
+				compatible = "socionext,uniphier-pro5-usb3-hsphy";
+				reg = <0x280 0x10>;
+				#phy-cells = <0>;
+				clock-names = "gio", "link";
+				clocks = <&sys_clk 12>, <&sys_clk 14>;
+				reset-names = "gio", "link";
+				resets = <&sys_rst 12>, <&sys_rst 14>;
+				vbus-supply = <&usb0_vbus0>;
+			};
+
+			usb0_ssphy0: ss-phy@380 {
+				compatible = "socionext,uniphier-pro5-usb3-ssphy";
+				reg = <0x380 0x10>;
+				#phy-cells = <0>;
+				clock-names = "gio", "link";
+				clocks = <&sys_clk 12>, <&sys_clk 14>;
+				reset-names = "gio", "link";
+				resets = <&sys_rst 12>, <&sys_rst 14>;
+				vbus-supply = <&usb0_vbus0>;
+			};
+		};
+
+		usb1: usb@65c00000 {
+			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
+			status = "disabled";
+			reg = <0x65c00000 0xcd00>;
+			interrupt-names = "host";
+			interrupts = <0 137 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
-			dwc3@65c00000 {
-				compatible = "snps,dwc3";
-				reg = <0x65c00000 0x10000>;
-				interrupts = <0 137 4>;
+			clock-names = "ref", "bus_early", "suspend";
+			clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
+			resets = <&usb1_rst 15>;
+			phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
 			dr_mode = "host";
-				tx-fifo-resize;
 		};
+
+		usb-glue@65d00000 {
+			compatible = "socionext,uniphier-pro5-dwc3-glue",
+				     "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x65d00000 0x400>;
+
+			usb1_rst: reset@0 {
+				compatible = "socionext,uniphier-pro5-usb3-reset";
+				reg = <0x0 0x4>;
+				#reset-cells = <1>;
+				clock-names = "gio", "link";
+				clocks = <&sys_clk 12>, <&sys_clk 15>;
+				reset-names = "gio", "link";
+				resets = <&sys_rst 12>, <&sys_rst 15>;
+			};
+
+			usb1_vbus0: regulator@100 {
+				compatible = "socionext,uniphier-pro5-usb3-regulator";
+				reg = <0x100 0x10>;
+				clock-names = "gio", "link";
+				clocks = <&sys_clk 12>, <&sys_clk 15>;
+				reset-names = "gio", "link";
+				resets = <&sys_rst 12>, <&sys_rst 15>;
+			};
+
+			usb1_vbus1: regulator@110 {
+				compatible = "socionext,uniphier-pro5-usb3-regulator";
+				reg = <0x110 0x10>;
+				clock-names = "gio", "link";
+				clocks = <&sys_clk 12>, <&sys_clk 15>;
+				reset-names = "gio", "link";
+				resets = <&sys_rst 12>, <&sys_rst 15>;
+			};
+
+			usb1_hsphy0: hs-phy@280 {
+				compatible = "socionext,uniphier-pro5-usb3-hsphy";
+				reg = <0x280 0x10>;
+				#phy-cells = <0>;
+				clock-names = "gio", "link";
+				clocks = <&sys_clk 12>, <&sys_clk 15>;
+				reset-names = "gio", "link";
+				resets = <&sys_rst 12>, <&sys_rst 15>;
+				vbus-supply = <&usb1_vbus0>;
+			};
+
+			usb1_hsphy1: hs-phy@290 {
+				compatible = "socionext,uniphier-pro5-usb3-hsphy";
+				reg = <0x290 0x10>;
+				#phy-cells = <0>;
+				clock-names = "gio", "link";
+				clocks = <&sys_clk 12>, <&sys_clk 15>;
+				reset-names = "gio", "link";
+				resets = <&sys_rst 12>, <&sys_rst 15>;
+				vbus-supply = <&usb1_vbus1>;
+			};
+
+			usb1_ssphy0: ss-phy@380 {
+				compatible = "socionext,uniphier-pro5-usb3-ssphy";
+				reg = <0x380 0x10>;
+				#phy-cells = <0>;
+				clock-names = "gio", "link";
+				clocks = <&sys_clk 12>, <&sys_clk 15>;
+				reset-names = "gio", "link";
+				resets = <&sys_rst 12>, <&sys_rst 15>;
+				vbus-supply = <&usb1_vbus0>;
+			};
+		};
+
+		pcie_ep: pcie-ep@66000000 {
+			compatible = "socionext,uniphier-pro5-pcie-ep",
+				     "snps,dw-pcie-ep";
+			status = "disabled";
+			reg-names = "dbi", "dbi2", "link", "addr_space";
+			reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
+			      <0x66010000 0x10000>, <0x67000000 0x400000>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_pcie>;
+			clock-names = "gio", "link";
+			clocks = <&sys_clk 12>, <&sys_clk 24>;
+			reset-names = "gio", "link";
+			resets = <&sys_rst 12>, <&sys_rst 24>;
+			num-ib-windows = <16>;
+			num-ob-windows = <16>;
+			num-lanes = <4>;
+			phy-names = "pcie-phy";
+			phys = <&pcie_phy>;
+		};
+
+		pcie_phy: phy@66038000 {
+			compatible = "socionext,uniphier-pro5-pcie-phy";
+			reg = <0x66038000 0x4000>;
+			#phy-cells = <0>;
+			clock-names = "gio", "link";
+			clocks = <&sys_clk 12>, <&sys_clk 24>;
+			reset-names = "gio", "link";
+			resets = <&sys_rst 12>, <&sys_rst 24>;
 		};
 
 		nand: nand-controller@68000000 {

arch/arm/dts/uniphier-pxs2-gentil.dts

@@ -87,7 +87,7 @@
 };
 
 &mdio {
-	ethphy: ethphy@1 {
+	ethphy: ethernet-phy@1 {
 		reg = <1>;
 	};
 };

arch/arm/dts/uniphier-pxs2-vodka.dts

@@ -88,7 +88,7 @@
 };
 
 &mdio {
-	ethphy: ethphy@1 {
+	ethphy: ethernet-phy@1 {
 		reg = <1>;
 	};
 };

arch/arm/dts/uniphier-pxs3-ref.dts

@@ -19,7 +19,7 @@
 
 	aliases {
 		serial0 = &serial0;
-		serial1 = &serial1;
+		serial1 = &serialsc;
 		serial2 = &serial2;
 		serial3 = &serial3;
 		i2c0 = &i2c0;
@@ -43,6 +43,10 @@
 	interrupts = <4 8>;
 };
 
+&serialsc {
+	interrupts = <4 8>;
+};
+
 &spi0 {
 	status = "okay";
 };
@@ -97,7 +101,7 @@
 };
 
 &mdio0 {
-	ethphy0: ethphy@0 {
+	ethphy0: ethernet-phy@0 {
 		reg = <0>;
 	};
 };
@@ -108,7 +112,7 @@
 };
 
 &mdio1 {
-	ethphy1: ethphy@0 {
+	ethphy1: ethernet-phy@0 {
 		reg = <0>;
 	};
 };

arch/arm/dts/uniphier-pxs3.dtsi

@@ -871,7 +871,9 @@
 			compatible = "socionext,uniphier-pxs3-pcie-phy";
 			reg = <0x66038000 0x4000>;
 			#phy-cells = <0>;
+			clock-names = "link";
 			clocks = <&sys_clk 24>;
+			reset-names = "link";
 			resets = <&sys_rst 24>;
 			socionext,syscon = <&soc_glue>;
 		};

arch/arm/dts/uniphier-sld8-ref.dts

@@ -20,7 +20,7 @@
 
 	aliases {
 		serial0 = &serial0;
-		serial1 = &serial1;
+		serial1 = &serialsc;
 		serial2 = &serial2;
 		serial3 = &serial3;
 		i2c0 = &i2c0;
@@ -39,6 +39,10 @@
 	interrupts = <0 8>;
 };
 
+&serialsc {
+	interrupts = <0 8>;
+};
+
 &serial0 {
 	status = "okay";
 };

arch/arm/dts/uniphier-support-card.dtsi

@@ -8,26 +8,19 @@
 &system_bus {
 	status = "okay";
 	ranges = <1 0x00000000 0x42000000 0x02000000>;
-
-	support_card: support-card@1,1f00000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x00000000 1 0x01f00000 0x00100000>;
 	interrupt-parent = <&gpio>;
 
-		ethsc: ethernet@0 {
+	ethsc: ethernet@1,1f00000 {
 		compatible = "smsc,lan9118", "smsc,lan9115";
-			reg = <0x00000000 0x1000>;
+		reg = <1 0x01f00000 0x1000>;
 		phy-mode = "mii";
 		reg-io-width = <4>;
 	};
 
-		serialsc: uart@b0000 {
+	serialsc: serial@1,1fb0000 {
 		compatible = "ns16550a";
-			reg = <0x000b0000 0x20>;
+		reg = <1 0x01fb0000 0x20>;
 		clock-frequency = <12288000>;
 		reg-shift = <1>;
 	};
-	};
 };

arch/arm/mach-uniphier/Makefile

@@ -20,7 +20,6 @@ obj-y += reset.o
 endif
 
 obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
-obj-y += pinctrl-glue.o
 obj-$(CONFIG_MMC) += mmc-first-dev.o
 obj-y += fdt-fixup.o
 

arch/arm/mach-uniphier/board_late_init.c

@@ -9,9 +9,7 @@
 #include <init.h>
 #include <spl.h>
 #include <linux/libfdt.h>
-#include <nand.h>
 #include <stdio.h>
-#include <linux/io.h>
 #include <linux/printk.h>
 
 #include "init.h"
@@ -53,6 +51,7 @@ fail:
 
 static void uniphier_set_env_addr(const char *env, const char *offset_env)
 {
+	DECLARE_GLOBAL_DATA_PTR;
 	unsigned long offset = 0;
 	const char *str;
 	char *end;

arch/arm/mach-uniphier/init.h

@@ -73,7 +73,6 @@ void uniphier_pxs3_clk_init(void);
 unsigned int uniphier_boot_device_raw(void);
 int uniphier_have_internal_stm(void);
 int uniphier_boot_from_backend(void);
-int uniphier_pin_init(const char *pinconfig_name);
 
 #ifdef CONFIG_ARM64
 void uniphier_mem_map_init(unsigned long dram_base, unsigned long dram_size);

arch/arm/mach-uniphier/pinctrl-glue.c

-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- */
-
-#include <linux/errno.h>
-#include <dm.h>
-#include <dm/pinctrl.h>
-
-#include "init.h"
-
-int uniphier_pin_init(const char *pinconfig_name)
-{
-	struct udevice *pctldev, *config;
-	int ret;
-
-	ret = uclass_first_device(UCLASS_PINCTRL, &pctldev);
-	if (ret)
-		return ret;
-
-	device_foreach_child(config, pctldev) {
-		if (strcmp(config->name, pinconfig_name))
-			continue;
-
-		return pinctrl_generic_set_state(pctldev, config);
-	}
-
-	return -ENODEV;
-}

arch/arm/mach-uniphier/sg-regs.h

@@ -10,6 +10,8 @@
 #ifndef UNIPHIER_SG_REGS_H
 #define UNIPHIER_SG_REGS_H
 
+#include <linux/bitops.h>
+
 #ifndef __ASSEMBLY__
 #include <linux/compiler.h>
 #ifdef CONFIG_ARCH_UNIPHIER_V8_MULTI
@@ -24,6 +26,9 @@ extern void __iomem *sg_base;
 
 /* Revision */
 #define SG_REVISION		0x0000
+#define   SG_REVISION_TYPE_MASK		GENMASK(23, 16)
+#define   SG_REVISION_MODEL_MASK	GENMASK(10, 8)
+#define   SG_REVISION_REV_MASK		GENMASK(4, 0)
 
 /* Memory Configuration */
 #define SG_MEMCONF		0x0400

arch/arm/mach-uniphier/soc-info.c

@@ -4,31 +4,30 @@
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  */
 
+#include <linux/bitfield.h>
 #include <linux/io.h>
 #include <linux/types.h>
 
 #include "sg-regs.h"
 #include "soc-info.h"
 
-static unsigned int __uniphier_get_revision_field(unsigned int mask,
-						  unsigned int shift)
-{
-	u32 revision = readl(sg_base + SG_REVISION);
-
-	return (revision >> shift) & mask;
-}
-
 unsigned int uniphier_get_soc_id(void)
 {
-	return __uniphier_get_revision_field(0xff, 16);
+	u32 rev = readl(sg_base + SG_REVISION);
+
+	return FIELD_GET(SG_REVISION_TYPE_MASK, rev);
 }
 
 unsigned int uniphier_get_soc_model(void)
 {
-	return __uniphier_get_revision_field(0x7, 8);
+	u32 rev = readl(sg_base + SG_REVISION);
+
+	return FIELD_GET(SG_REVISION_MODEL_MASK, rev);
 }
 
 unsigned int uniphier_get_soc_revision(void)
 {
-	return __uniphier_get_revision_field(0x1f, 0);
+	u32 rev = readl(sg_base + SG_REVISION);
+
+	return FIELD_GET(SG_REVISION_REV_MASK, rev);
 }

drivers/serial/serial_uniphier.c

@@ -137,7 +137,7 @@ static int uniphier_serial_probe(struct udevice *dev)
 
 	priv->uartclk = clk_data->clk_rate;
 
-	/* flush the trasmitter empty before changing hw setting */
+	/* flush the trasmitter before changing hw setting */
 	while (!(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_TEMT))
 		;
 

include/configs/uniphier.h

@@ -7,8 +7,8 @@
 
 /* U-Boot - Common settings for UniPhier Family */
 
-#ifndef __CONFIG_UNIPHIER_COMMON_H__
-#define __CONFIG_UNIPHIER_COMMON_H__
+#ifndef __CONFIG_UNIPHIER_H__
+#define __CONFIG_UNIPHIER_H__
 
 #ifndef CONFIG_SPL_BUILD
 #include <config_distro_bootcmd.h>
@@ -210,4 +210,4 @@
 
 #define CONFIG_SPL_PAD_TO			0x20000
 
-#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
+#endif /* __CONFIG_UNIPHIER_H__ */