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65282edb
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体验新版 GitCode,发现更多精彩内容 >>
提交
65282edb
编写于
8月 04, 2020
作者:
M
Masahiro Yamada
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
ARM: dts: uniphier: resync DT with Linux 5.9-rc1
Signed-off-by:
N
Masahiro Yamada
<
yamada.masahiro@socionext.com
>
上级
351b74cb
变更
18
隐藏空白更改
内联
并排
Showing
18 changed file
with
235 addition
and
61 deletion
+235
-61
arch/arm/dts/uniphier-ld11-global.dts
arch/arm/dts/uniphier-ld11-global.dts
+1
-1
arch/arm/dts/uniphier-ld11-ref.dts
arch/arm/dts/uniphier-ld11-ref.dts
+6
-2
arch/arm/dts/uniphier-ld20-global.dts
arch/arm/dts/uniphier-ld20-global.dts
+1
-1
arch/arm/dts/uniphier-ld20-ref.dts
arch/arm/dts/uniphier-ld20-ref.dts
+6
-2
arch/arm/dts/uniphier-ld20.dtsi
arch/arm/dts/uniphier-ld20.dtsi
+2
-0
arch/arm/dts/uniphier-ld4-ref.dts
arch/arm/dts/uniphier-ld4-ref.dts
+5
-1
arch/arm/dts/uniphier-ld6b-ref.dts
arch/arm/dts/uniphier-ld6b-ref.dts
+6
-1
arch/arm/dts/uniphier-pinctrl.dtsi
arch/arm/dts/uniphier-pinctrl.dtsi
+5
-0
arch/arm/dts/uniphier-pro4-ace.dts
arch/arm/dts/uniphier-pro4-ace.dts
+1
-1
arch/arm/dts/uniphier-pro4-ref.dts
arch/arm/dts/uniphier-pro4-ref.dts
+6
-2
arch/arm/dts/uniphier-pro4-sanji.dts
arch/arm/dts/uniphier-pro4-sanji.dts
+2
-1
arch/arm/dts/uniphier-pro5.dtsi
arch/arm/dts/uniphier-pro5.dtsi
+166
-24
arch/arm/dts/uniphier-pxs2-gentil.dts
arch/arm/dts/uniphier-pxs2-gentil.dts
+1
-1
arch/arm/dts/uniphier-pxs2-vodka.dts
arch/arm/dts/uniphier-pxs2-vodka.dts
+1
-1
arch/arm/dts/uniphier-pxs3-ref.dts
arch/arm/dts/uniphier-pxs3-ref.dts
+7
-3
arch/arm/dts/uniphier-pxs3.dtsi
arch/arm/dts/uniphier-pxs3.dtsi
+2
-0
arch/arm/dts/uniphier-sld8-ref.dts
arch/arm/dts/uniphier-sld8-ref.dts
+5
-1
arch/arm/dts/uniphier-support-card.dtsi
arch/arm/dts/uniphier-support-card.dtsi
+12
-19
未找到文件。
arch/arm/dts/uniphier-ld11-global.dts
浏览文件 @
65282edb
...
...
@@ -157,7 +157,7 @@
};
&
mdio
{
ethphy
:
ethphy
@
1
{
ethphy
:
eth
ernet
-
phy
@
1
{
reg
=
<
1
>;
};
};
...
...
arch/arm/dts/uniphier-ld11-ref.dts
浏览文件 @
65282edb
...
...
@@ -20,7 +20,7 @@
aliases
{
serial0
=
&
serial0
;
serial1
=
&
serial
1
;
serial1
=
&
serial
sc
;
serial2
=
&
serial2
;
serial3
=
&
serial3
;
i2c0
=
&
i2c0
;
...
...
@@ -42,6 +42,10 @@
interrupts
=
<
0
8
>;
};
&
serialsc
{
interrupts
=
<
0
8
>;
};
&
serial0
{
status
=
"okay"
;
};
...
...
@@ -76,7 +80,7 @@
};
&
mdio
{
ethphy
:
ethphy
@
1
{
ethphy
:
eth
ernet
-
phy
@
1
{
reg
=
<
1
>;
};
};
arch/arm/dts/uniphier-ld20-global.dts
浏览文件 @
65282edb
...
...
@@ -141,7 +141,7 @@
};
&
mdio
{
ethphy
:
ethphy
@
1
{
ethphy
:
eth
ernet
-
phy
@
1
{
reg
=
<
1
>;
};
};
...
...
arch/arm/dts/uniphier-ld20-ref.dts
浏览文件 @
65282edb
...
...
@@ -20,7 +20,7 @@
aliases
{
serial0
=
&
serial0
;
serial1
=
&
serial
1
;
serial1
=
&
serial
sc
;
serial2
=
&
serial2
;
serial3
=
&
serial3
;
i2c0
=
&
i2c0
;
...
...
@@ -42,6 +42,10 @@
interrupts
=
<
0
8
>;
};
&
serialsc
{
interrupts
=
<
0
8
>;
};
&
serial0
{
status
=
"okay"
;
};
...
...
@@ -64,7 +68,7 @@
};
&
mdio
{
ethphy
:
ethphy
@
0
{
ethphy
:
eth
ernet
-
phy
@
0
{
reg
=
<
0
>;
};
};
...
...
arch/arm/dts/uniphier-ld20.dtsi
浏览文件 @
65282edb
...
...
@@ -955,7 +955,9 @@
compatible = "socionext,uniphier-ld20-pcie-phy";
reg = <0x66038000 0x4000>;
#phy-cells = <0>;
clock-names = "link";
clocks = <&sys_clk 24>;
reset-names = "link";
resets = <&sys_rst 24>;
socionext,syscon = <&soc_glue>;
};
...
...
arch/arm/dts/uniphier-ld4-ref.dts
浏览文件 @
65282edb
...
...
@@ -20,7 +20,7 @@
aliases
{
serial0
=
&
serial0
;
serial1
=
&
serial
1
;
serial1
=
&
serial
sc
;
serial2
=
&
serial2
;
serial3
=
&
serial3
;
i2c0
=
&
i2c0
;
...
...
@@ -39,6 +39,10 @@
interrupts
=
<
1
8
>;
};
&
serialsc
{
interrupts
=
<
1
8
>;
};
&
serial0
{
status
=
"okay"
;
};
...
...
arch/arm/dts/uniphier-ld6b-ref.dts
浏览文件 @
65282edb
...
...
@@ -22,6 +22,7 @@
serial0
=
&
serial0
;
serial1
=
&
serial1
;
serial2
=
&
serial2
;
serial3
=
&
serialsc
;
i2c0
=
&
i2c0
;
i2c1
=
&
i2c1
;
i2c2
=
&
i2c2
;
...
...
@@ -42,6 +43,10 @@
interrupts
=
<
4
8
>;
};
&
serialsc
{
interrupts
=
<
4
8
>;
};
&
serial0
{
status
=
"okay"
;
};
...
...
@@ -76,7 +81,7 @@
};
&
mdio
{
ethphy
:
ethphy
@
0
{
ethphy
:
eth
ernet
-
phy
@
0
{
reg
=
<
0
>;
};
};
...
...
arch/arm/dts/uniphier-pinctrl.dtsi
浏览文件 @
65282edb
...
...
@@ -126,6 +126,11 @@
function = "nand";
};
pinctrl_pcie: pcie {
groups = "pcie";
function = "pcie";
};
pinctrl_sd: sd {
groups = "sd";
function = "sd";
...
...
arch/arm/dts/uniphier-pro4-ace.dts
浏览文件 @
65282edb
...
...
@@ -87,7 +87,7 @@
};
&
mdio
{
ethphy
:
ethphy
@
1
{
ethphy
:
eth
ernet
-
phy
@
1
{
reg
=
<
1
>;
};
};
...
...
arch/arm/dts/uniphier-pro4-ref.dts
浏览文件 @
65282edb
...
...
@@ -22,7 +22,7 @@
serial0
=
&
serial0
;
serial1
=
&
serial1
;
serial2
=
&
serial2
;
serial3
=
&
serial
3
;
serial3
=
&
serial
sc
;
i2c0
=
&
i2c0
;
i2c1
=
&
i2c1
;
i2c2
=
&
i2c2
;
...
...
@@ -43,6 +43,10 @@
interrupts
=
<
2
8
>;
};
&
serialsc
{
interrupts
=
<
2
8
>;
};
&
serial0
{
status
=
"okay"
;
};
...
...
@@ -85,7 +89,7 @@
};
&
mdio
{
ethphy
:
ethphy
@
0
{
ethphy
:
eth
ernet
-
phy
@
0
{
reg
=
<
0
>;
};
};
...
...
arch/arm/dts/uniphier-pro4-sanji.dts
浏览文件 @
65282edb
...
...
@@ -25,6 +25,7 @@
i2c3
=
&
i2c3
;
i2c5
=
&
i2c5
;
i2c6
=
&
i2c6
;
ethernet0
=
&
eth
;
};
memory
@
80000000
{
...
...
@@ -81,7 +82,7 @@
};
&
mdio
{
ethphy
:
ethphy
@
1
{
ethphy
:
eth
ernet
-
phy
@
1
{
reg
=
<
1
>;
};
};
...
...
arch/arm/dts/uniphier-pro5.dtsi
浏览文件 @
65282edb
...
...
@@ -465,40 +465,182 @@
};
};
usb0: usb@65
b
00000 {
compatible = "socionext,uniphier-
pro5-
dwc3";
usb0: usb@65
a
00000 {
compatible = "socionext,uniphier-
dwc3", "snps,
dwc3";
status = "disabled";
reg = <0x65b00000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x65a00000 0xcd00>;
interrupt-names = "host";
interrupts = <0 134 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
dwc3@65a00000 {
compatible = "snps,dwc3";
reg = <0x65a00000 0x10000>;
interrupts = <0 134 4>;
dr_mode = "host";
tx-fifo-resize;
};
clock-names = "ref", "bus_early", "suspend";
clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
resets = <&usb0_rst 15>;
phys = <&usb0_hsphy0>, <&usb0_ssphy0>;
dr_mode = "host";
};
usb1: usb@65d00000 {
compatible = "socionext,uniphier-pro5-dwc3";
status = "disabled";
reg = <0x65d00000 0x1000>;
usb-glue@65b00000 {
compatible = "socionext,uniphier-pro5-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ranges = <0 0x65b00000 0x400>;
usb0_rst: reset@0 {
compatible = "socionext,uniphier-pro5-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 14>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 14>;
};
usb0_vbus0: regulator@100 {
compatible = "socionext,uniphier-pro5-usb3-regulator";
reg = <0x100 0x10>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 14>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 14>;
};
usb0_hsphy0: hs-phy@280 {
compatible = "socionext,uniphier-pro5-usb3-hsphy";
reg = <0x280 0x10>;
#phy-cells = <0>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 14>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 14>;
vbus-supply = <&usb0_vbus0>;
};
usb0_ssphy0: ss-phy@380 {
compatible = "socionext,uniphier-pro5-usb3-ssphy";
reg = <0x380 0x10>;
#phy-cells = <0>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 14>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 14>;
vbus-supply = <&usb0_vbus0>;
};
};
usb1: usb@65c00000 {
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";
reg = <0x65c00000 0xcd00>;
interrupt-names = "host";
interrupts = <0 137 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
dwc3@65c00000 {
compatible = "snps,dwc3";
reg = <0x65c00000 0x10000>;
interrupts = <0 137 4>;
dr_mode = "host";
tx-fifo-resize;
clock-names = "ref", "bus_early", "suspend";
clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
resets = <&usb1_rst 15>;
phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
dr_mode = "host";
};
usb-glue@65d00000 {
compatible = "socionext,uniphier-pro5-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65d00000 0x400>;
usb1_rst: reset@0 {
compatible = "socionext,uniphier-pro5-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 15>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 15>;
};
usb1_vbus0: regulator@100 {
compatible = "socionext,uniphier-pro5-usb3-regulator";
reg = <0x100 0x10>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 15>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 15>;
};
usb1_vbus1: regulator@110 {
compatible = "socionext,uniphier-pro5-usb3-regulator";
reg = <0x110 0x10>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 15>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 15>;
};
usb1_hsphy0: hs-phy@280 {
compatible = "socionext,uniphier-pro5-usb3-hsphy";
reg = <0x280 0x10>;
#phy-cells = <0>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 15>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 15>;
vbus-supply = <&usb1_vbus0>;
};
usb1_hsphy1: hs-phy@290 {
compatible = "socionext,uniphier-pro5-usb3-hsphy";
reg = <0x290 0x10>;
#phy-cells = <0>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 15>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 15>;
vbus-supply = <&usb1_vbus1>;
};
usb1_ssphy0: ss-phy@380 {
compatible = "socionext,uniphier-pro5-usb3-ssphy";
reg = <0x380 0x10>;
#phy-cells = <0>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 15>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 15>;
vbus-supply = <&usb1_vbus0>;
};
};
pcie_ep: pcie-ep@66000000 {
compatible = "socionext,uniphier-pro5-pcie-ep",
"snps,dw-pcie-ep";
status = "disabled";
reg-names = "dbi", "dbi2", "link", "addr_space";
reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
<0x66010000 0x10000>, <0x67000000 0x400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 24>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 24>;
num-ib-windows = <16>;
num-ob-windows = <16>;
num-lanes = <4>;
phy-names = "pcie-phy";
phys = <&pcie_phy>;
};
pcie_phy: phy@66038000 {
compatible = "socionext,uniphier-pro5-pcie-phy";
reg = <0x66038000 0x4000>;
#phy-cells = <0>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 24>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 24>;
};
nand: nand-controller@68000000 {
...
...
arch/arm/dts/uniphier-pxs2-gentil.dts
浏览文件 @
65282edb
...
...
@@ -87,7 +87,7 @@
};
&
mdio
{
ethphy
:
ethphy
@
1
{
ethphy
:
eth
ernet
-
phy
@
1
{
reg
=
<
1
>;
};
};
...
...
arch/arm/dts/uniphier-pxs2-vodka.dts
浏览文件 @
65282edb
...
...
@@ -88,7 +88,7 @@
};
&
mdio
{
ethphy
:
ethphy
@
1
{
ethphy
:
eth
ernet
-
phy
@
1
{
reg
=
<
1
>;
};
};
...
...
arch/arm/dts/uniphier-pxs3-ref.dts
浏览文件 @
65282edb
...
...
@@ -19,7 +19,7 @@
aliases
{
serial0
=
&
serial0
;
serial1
=
&
serial
1
;
serial1
=
&
serial
sc
;
serial2
=
&
serial2
;
serial3
=
&
serial3
;
i2c0
=
&
i2c0
;
...
...
@@ -43,6 +43,10 @@
interrupts
=
<
4
8
>;
};
&
serialsc
{
interrupts
=
<
4
8
>;
};
&
spi0
{
status
=
"okay"
;
};
...
...
@@ -97,7 +101,7 @@
};
&
mdio0
{
ethphy0
:
ethphy
@
0
{
ethphy0
:
eth
ernet
-
phy
@
0
{
reg
=
<
0
>;
};
};
...
...
@@ -108,7 +112,7 @@
};
&
mdio1
{
ethphy1
:
ethphy
@
0
{
ethphy1
:
eth
ernet
-
phy
@
0
{
reg
=
<
0
>;
};
};
...
...
arch/arm/dts/uniphier-pxs3.dtsi
浏览文件 @
65282edb
...
...
@@ -871,7 +871,9 @@
compatible = "socionext,uniphier-pxs3-pcie-phy";
reg = <0x66038000 0x4000>;
#phy-cells = <0>;
clock-names = "link";
clocks = <&sys_clk 24>;
reset-names = "link";
resets = <&sys_rst 24>;
socionext,syscon = <&soc_glue>;
};
...
...
arch/arm/dts/uniphier-sld8-ref.dts
浏览文件 @
65282edb
...
...
@@ -20,7 +20,7 @@
aliases
{
serial0
=
&
serial0
;
serial1
=
&
serial
1
;
serial1
=
&
serial
sc
;
serial2
=
&
serial2
;
serial3
=
&
serial3
;
i2c0
=
&
i2c0
;
...
...
@@ -39,6 +39,10 @@
interrupts
=
<
0
8
>;
};
&
serialsc
{
interrupts
=
<
0
8
>;
};
&
serial0
{
status
=
"okay"
;
};
...
...
arch/arm/dts/uniphier-support-card.dtsi
浏览文件 @
65282edb
...
...
@@ -8,26 +8,19 @@
&system_bus {
status = "okay";
ranges = <1 0x00000000 0x42000000 0x02000000>;
interrupt-parent = <&gpio>;
support_card: support-card@1,1f00000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 1 0x01f00000 0x00100000>;
interrupt-parent = <&gpio>;
ethsc: ethernet@0 {
compatible = "smsc,lan9118", "smsc,lan9115";
reg = <0x00000000 0x1000>;
phy-mode = "mii";
reg-io-width = <4>;
};
ethsc: ethernet@1,1f00000 {
compatible = "smsc,lan9118", "smsc,lan9115";
reg = <1 0x01f00000 0x1000>;
phy-mode = "mii";
reg-io-width = <4>;
};
serialsc: uart@b0000 {
compatible = "ns16550a";
reg = <0x000b0000 0x20>;
clock-frequency = <12288000>;
reg-shift = <1>;
};
serialsc: serial@1,1fb0000 {
compatible = "ns16550a";
reg = <1 0x01fb0000 0x20>;
clock-frequency = <12288000>;
reg-shift = <1>;
};
};
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