[PATCH] Update AMCC Katmai 440SPe eval board support

This patch updates the recently added Katmai board support. The biggest
change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2
driver.

Please note, that still some problems are left with some memory
configurations. See the driver for more details.
Signed-off-by: NStefan Roese <sr@denx.de>

board/amcc/katmai/katmai.c

@@ -28,7 +28,6 @@
 #include <i2c.h>
 #include <asm-ppc/io.h>
 
-#include "katmai.h"
 #include "../cpu/ppc4xx/440spe_pcie.h"
 
 #undef PCIE_ENDPOINT
@@ -40,7 +39,6 @@ void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
 int board_early_init_f (void)
 {
 	unsigned long mfr;
-	unsigned long pfc;
 
 	/*----------------------------------------------------------------------+
 	 * Interrupt controller setup for the Katmai 440SPe Evaluation board.
@@ -228,15 +226,11 @@ int board_early_init_f (void)
 	mfr &= ~SDR0_MFR_ECS_MASK;
 /*	mtsdr(sdr_mfr, mfr); */
 
-	/*
-	 * Setup GPIO signalling per defines in katmai.h
-	 */
-	pfc = PFC0_KATMAI;
-	mtsdr(SDR0_PFC0, pfc);
+	mtsdr(SDR0_PFC0, CFG_PFC0);
 
-	out32(GPIO0_OR_ADDR, GPIO_OR_KATMAI);
-	out32(GPIO0_ODR_ADDR, GPIO_ODR_KATMAI);
-	out32(GPIO0_TCR_ADDR, GPIO_TCR_KATMAI);
+	out32(GPIO0_OR, CFG_GPIO_OR);
+	out32(GPIO0_ODR, CFG_GPIO_ODR);
+	out32(GPIO0_TCR, CFG_GPIO_TCR);
 
 	return 0;
 }
@@ -378,6 +372,23 @@ int is_pci_host(struct pci_controller *hose)
 	return 1;
 }
 
+int katmai_pcie_card_present(int port)
+{
+	u32 val;
+
+	val = in32(GPIO0_IR);
+	switch (port) {
+	case 0:
+		return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT0));
+	case 1:
+		return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT1));
+	case 2:
+		return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT2));
+	default:
+		return 0;
+	}
+}
+
 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
 
 void pcie_setup_hoses(void)
@@ -391,6 +402,10 @@ void pcie_setup_hoses(void)
 	 */
 	bus = 1;
 	for (i = 0; i <= 2; i++) {
+		/* Check for katmai card presence */
+		if (!katmai_pcie_card_present(i))
+			continue;
+
 #ifdef PCIE_ENDPOINT
  		if (ppc440spe_init_pcie_endport(i)) {
 #else

board/amcc/katmai/katmai.h

-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __KATMAI_H_
-#define __KATMAI_H_
-
-/*----------------------------------------------------------------------------
- *                    XX
- *   XXXX    XX XXX   XXX     XXXX
- * XX        XX  XX   XX    XX  XX
- * XX  XXX   XX  XX   XX    XX  XX
- * XX  XX    XXXXX    XX    XX  XX
- *  XXXX     XX      XXXX    XXXX
- *          XXXX
- *
- *  The 440SPe provices 32 bits of GPIO.  By default all GPIO pins
- *  are disabled, and must be explicitly enabled by setting a
- *  bit in the SDR0_PFC0 indirect DCR.  Each GPIO maps 1-to-1 with the
- *  corresponding bit in the SDR0_PFC0 register (note that bit numbers
- *  reflect the PowerPC convention where bit 0 is the most-significant
- *  bit).
- *
- *   Katmai specific:
- *      RS232_RX_EN# is held HIGH during reset by hardware, keeping the
- *      RS232_CTS, DSR & DCD  signals coming from the MAX3411 (U26) in
- *      Hi-Z condition. This prevents contention between the MAX3411 (U26)
- *      and 74CBTLV3125PG (U2) during reset.
- *
- *      RS232_RX_EN# is connected as GPIO pin 30.  Once the processor
- *      is released from reset, this pin must be configured as an output and
- *      then driven high to enable the receive signals from the UART transciever.
- *----------------------------------------------------------------------------*/
-#define GPIO_ENABLE(gpio)       (0x80000000 >> (gpio))
-
-#define PFC0_KATMAI             GPIO_ENABLE(30)
-#define GPIO_OR_KATMAI          GPIO_ENABLE(30)     /* Drive all outputs low except GPIO 30 */
-#define GPIO_TCR_KATMAI         GPIO_ENABLE(30)
-#define GPIO_ODR_KATMAI         0                   /* Disable open drain for all outputs */
-
-#define GPIO0_OR_ADDR           (CFG_PERIPHERAL_BASE + 0x700)
-#define GPIO0_TCR_ADDR          (CFG_PERIPHERAL_BASE + 0x704)
-#define GPIO0_ODR_ADDR          (CFG_PERIPHERAL_BASE + 0x718)
-#define GPIO0_IR_ADDR           (CFG_PERIPHERAL_BASE + 0x71C)
-
-#endif /* __KATMAI_H_ */

cpu/ppc4xx/start.S

@@ -1912,4 +1912,47 @@ pll_wait:
         TLBRE(3,3,0)
 	blr
 	function_epilog(mftlb1)
+
+/*----------------------------------------------------------------------------+
+| dcbz_area.
++----------------------------------------------------------------------------*/
+        function_prolog(dcbz_area)
+        rlwinm. r5,r4,0,27,31
+        rlwinm  r5,r4,27,5,31
+        beq     ..d_ra2
+        addi    r5,r5,0x0001
+..d_ra2:mtctr   r5
+..d_ag2:dcbz    r0,r3
+        addi    r3,r3,32
+        bdnz    ..d_ag2
+        sync
+        blr
+        function_epilog(dcbz_area)
+
+/*----------------------------------------------------------------------------+
+| dflush.  Assume 32K at vector address is cachable.
++----------------------------------------------------------------------------*/
+        function_prolog(dflush)
+        mfmsr   r9
+        rlwinm  r8,r9,0,15,13
+        rlwinm  r8,r8,0,17,15
+        mtmsr   r8
+        addi    r3,r0,0x0000
+        mtspr   dvlim,r3
+        mfspr   r3,ivpr
+        addi    r4,r0,1024
+        mtctr   r4
+..dflush_loop:
+        lwz     r6,0x0(r3)
+        addi    r3,r3,32
+        bdnz    ..dflush_loop
+        addi    r3,r3,-32
+        mtctr   r4
+..ag:   dcbf    r0,r3
+        addi    r3,r3,-32
+        bdnz    ..ag
+        sync
+        mtmsr   r9
+        blr
+        function_epilog(dflush)
 #endif /* CONFIG_440 */

cpu/ppc4xx/tlb.c

@@ -166,13 +166,13 @@ static void program_tlb_addr(unsigned long base_addr, unsigned long mem_size,
  * Common usage for boards with SDRAM DIMM modules to dynamically
  * configure the TLB's for the SDRAM
  */
-void program_tlb(u32 start, u32 size)
+void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value)
 {
 	region_t region_array;
 
 	region_array.base = start;
 	region_array.size = size;
-	region_array.tlb_word2_i_value = TLB_WORD2_I_ENABLE;	/* disable cache (for now) */
+	region_array.tlb_word2_i_value = tlb_word2_i_value;	/* en-/disable cache */
 
 	/* Call the routine to add in the tlb entries for the memory regions */
 	program_tlb_addr(region_array.base, region_array.size,

include/configs/katmai.h

@@ -107,11 +107,8 @@
  * DDR SDRAM
  *----------------------------------------------------------------------*/
 #define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
-#define SPD_EEPROM_ADDRESS {0x51, 0x52}	/* SPD i2c spd addresses	*/
-#define IIC0_DIMM0_ADDR		0x51
-#define IIC0_DIMM1_ADDR		0x52
+#define SPD_EEPROM_ADDRESS	{0x51, 0x52}	/* SPD i2c spd addresses*/
 #undef  CONFIG_STRESS
-#undef  ENABLE_ECC
 
 /*-----------------------------------------------------------------------
  * I2C
@@ -384,6 +381,22 @@
 				 EBC_CFG_PME_DISABLE  |	\
 				 EBC_CFG_PR_16)
 
+/*-----------------------------------------------------------------------
+ * GPIO Setup
+ *----------------------------------------------------------------------*/
+#define CFG_GPIO_PCIE_PRESENT0	17
+#define CFG_GPIO_PCIE_PRESENT1	21
+#define CFG_GPIO_PCIE_PRESENT2	23
+#define CFG_GPIO_RS232_FORCEOFF	30
+
+#define CFG_PFC0		(GPIO_VAL(CFG_GPIO_PCIE_PRESENT0) | \
+				 GPIO_VAL(CFG_GPIO_PCIE_PRESENT1) | \
+				 GPIO_VAL(CFG_GPIO_PCIE_PRESENT2) | \
+				 GPIO_VAL(CFG_GPIO_RS232_FORCEOFF))
+#define CFG_GPIO_OR		GPIO_VAL(CFG_GPIO_RS232_FORCEOFF)
+#define CFG_GPIO_TCR		GPIO_VAL(CFG_GPIO_RS232_FORCEOFF)
+#define CFG_GPIO_ODR		0
+
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is

include/ppc440.h

@@ -3190,7 +3190,8 @@
 #define GPIO0			0
 #define GPIO1			1
 
-#if defined(CONFIG_440GP) || defined(CONFIG_440GX)
+#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 #define GPIO0_BASE             (CFG_PERIPHERAL_BASE+0x00000700)
 
 #define GPIO0_OR               (GPIO0_BASE+0x0)
@@ -3275,6 +3276,8 @@
 #define GPIO_IN_SEL	    0x40000000	    /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
 					    /* For the other GPIO number, you must shift */
 
+#define GPIO_VAL(gpio)		(0x80000000 >> (gpio))
+
 #ifndef __ASSEMBLY__
 
 typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
@@ -3285,7 +3288,6 @@ typedef struct { unsigned long	add;	/* gpio core base address */
 	gpio_select_t  alt_nb; /* Selected Alternate */
 } gpio_param_s;
 
-
 #endif /* __ASSEMBLY__ */
 
 /*