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b685c734
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b685c734
编写于
1月 08, 2016
作者:
T
Tom Rini
浏览文件
操作
浏览文件
下载
差异文件
Merge branch 'master' of
git://www.denx.de/git/u-boot-imx
上级
7ba34ff0
587c3f8e
变更
9
隐藏空白更改
内联
并排
Showing
9 changed file
with
41 addition
and
79 deletion
+41
-79
board/freescale/common/pfuze.c
board/freescale/common/pfuze.c
+2
-1
board/freescale/mx6sabresd/mx6sabresd.c
board/freescale/mx6sabresd/mx6sabresd.c
+2
-34
board/wandboard/wandboard.c
board/wandboard/wandboard.c
+2
-34
drivers/gpio/mxs_gpio.c
drivers/gpio/mxs_gpio.c
+15
-0
drivers/net/phy/atheros.c
drivers/net/phy/atheros.c
+1
-1
drivers/thermal/imx_thermal.c
drivers/thermal/imx_thermal.c
+15
-8
drivers/watchdog/imx_watchdog.c
drivers/watchdog/imx_watchdog.c
+1
-1
include/configs/mx6ul_14x14_evk.h
include/configs/mx6ul_14x14_evk.h
+2
-0
include/fsl_wdog.h
include/fsl_wdog.h
+1
-0
未找到文件。
board/freescale/common/pfuze.c
浏览文件 @
b685c734
...
...
@@ -13,7 +13,8 @@
int
pfuze_mode_init
(
struct
pmic
*
p
,
u32
mode
)
{
unsigned
char
offset
,
i
,
switch_num
;
u32
id
,
ret
;
u32
id
;
int
ret
;
pmic_reg_read
(
p
,
PFUZE100_DEVICEID
,
&
id
);
id
=
id
&
0xf
;
...
...
board/freescale/mx6sabresd/mx6sabresd.c
浏览文件 @
b685c734
...
...
@@ -94,8 +94,9 @@ static void setup_iomux_enet(void)
/* Reset AR8031 PHY */
gpio_direction_output
(
IMX_GPIO_NR
(
1
,
25
)
,
0
);
udelay
(
50
0
);
mdelay
(
1
0
);
gpio_set_value
(
IMX_GPIO_NR
(
1
,
25
),
1
);
udelay
(
100
);
}
static
iomux_v3_cfg_t
const
usdhc2_pads
[]
=
{
...
...
@@ -340,39 +341,6 @@ int board_mmc_init(bd_t *bis)
}
#endif
int
mx6_rgmii_rework
(
struct
phy_device
*
phydev
)
{
unsigned
short
val
;
/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
phy_write
(
phydev
,
MDIO_DEVAD_NONE
,
0xd
,
0x7
);
phy_write
(
phydev
,
MDIO_DEVAD_NONE
,
0xe
,
0x8016
);
phy_write
(
phydev
,
MDIO_DEVAD_NONE
,
0xd
,
0x4007
);
val
=
phy_read
(
phydev
,
MDIO_DEVAD_NONE
,
0xe
);
val
&=
0xffe3
;
val
|=
0x18
;
phy_write
(
phydev
,
MDIO_DEVAD_NONE
,
0xe
,
val
);
/* introduce tx clock delay */
phy_write
(
phydev
,
MDIO_DEVAD_NONE
,
0x1d
,
0x5
);
val
=
phy_read
(
phydev
,
MDIO_DEVAD_NONE
,
0x1e
);
val
|=
0x0100
;
phy_write
(
phydev
,
MDIO_DEVAD_NONE
,
0x1e
,
val
);
return
0
;
}
int
board_phy_config
(
struct
phy_device
*
phydev
)
{
mx6_rgmii_rework
(
phydev
);
if
(
phydev
->
drv
->
config
)
phydev
->
drv
->
config
(
phydev
);
return
0
;
}
#if defined(CONFIG_VIDEO_IPUV3)
static
void
disable_lvds
(
struct
display_info_t
const
*
dev
)
{
...
...
board/wandboard/wandboard.c
浏览文件 @
b685c734
...
...
@@ -121,8 +121,9 @@ static void setup_iomux_enet(void)
/* Reset AR8031 PHY */
gpio_direction_output
(
ETH_PHY_RESET
,
0
);
udelay
(
50
0
);
mdelay
(
1
0
);
gpio_set_value
(
ETH_PHY_RESET
,
1
);
udelay
(
100
);
}
static
struct
fsl_esdhc_cfg
usdhc_cfg
[
2
]
=
{
...
...
@@ -187,39 +188,6 @@ int board_mmc_init(bd_t *bis)
return
0
;
}
static
int
mx6_rgmii_rework
(
struct
phy_device
*
phydev
)
{
unsigned
short
val
;
/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
phy_write
(
phydev
,
MDIO_DEVAD_NONE
,
0xd
,
0x7
);
phy_write
(
phydev
,
MDIO_DEVAD_NONE
,
0xe
,
0x8016
);
phy_write
(
phydev
,
MDIO_DEVAD_NONE
,
0xd
,
0x4007
);
val
=
phy_read
(
phydev
,
MDIO_DEVAD_NONE
,
0xe
);
val
&=
0xffe3
;
val
|=
0x18
;
phy_write
(
phydev
,
MDIO_DEVAD_NONE
,
0xe
,
val
);
/* introduce tx clock delay */
phy_write
(
phydev
,
MDIO_DEVAD_NONE
,
0x1d
,
0x5
);
val
=
phy_read
(
phydev
,
MDIO_DEVAD_NONE
,
0x1e
);
val
|=
0x0100
;
phy_write
(
phydev
,
MDIO_DEVAD_NONE
,
0x1e
,
val
);
return
0
;
}
int
board_phy_config
(
struct
phy_device
*
phydev
)
{
mx6_rgmii_rework
(
phydev
);
if
(
phydev
->
drv
->
config
)
phydev
->
drv
->
config
(
phydev
);
return
0
;
}
#if defined(CONFIG_VIDEO_IPUV3)
struct
i2c_pads_info
mx6q_i2c2_pad_info
=
{
.
scl
=
{
...
...
drivers/gpio/mxs_gpio.c
浏览文件 @
b685c734
...
...
@@ -114,3 +114,18 @@ int gpio_free(unsigned gpio)
{
return
0
;
}
int
name_to_gpio
(
const
char
*
name
)
{
unsigned
bank
,
pin
;
char
*
end
;
bank
=
simple_strtoul
(
name
,
&
end
,
10
);
if
(
!*
end
||
*
end
!=
':'
)
return
bank
;
pin
=
simple_strtoul
(
end
+
1
,
NULL
,
10
);
return
(
bank
<<
MXS_PAD_BANK_SHIFT
)
|
(
pin
<<
MXS_PAD_PIN_SHIFT
);
}
drivers/net/phy/atheros.c
浏览文件 @
b685c734
...
...
@@ -51,7 +51,7 @@ static struct phy_driver AR8031_driver = {
.
uid
=
0x4dd074
,
.
mask
=
0xffffffef
,
.
features
=
PHY_GBIT_FEATURES
,
.
config
=
ar80
21
_config
,
.
config
=
ar80
35
_config
,
.
startup
=
genphy_startup
,
.
shutdown
=
genphy_shutdown
,
};
...
...
drivers/thermal/imx_thermal.c
浏览文件 @
b685c734
...
...
@@ -130,7 +130,7 @@ static int read_cpu_temperature(struct udevice *dev)
#elif defined(CONFIG_MX7)
static
int
read_cpu_temperature
(
struct
udevice
*
dev
)
{
unsigned
int
reg
,
tmp
,
start
;
unsigned
int
reg
,
tmp
;
unsigned
int
raw_25c
,
te1
;
int
temperature
;
unsigned
int
*
priv
=
dev_get_priv
(
dev
);
...
...
@@ -169,18 +169,25 @@ static int read_cpu_temperature(struct udevice *dev)
writel
(
TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK
,
&
ccm_anatop
->
tempsense1_clr
);
writel
(
TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK
,
&
ccm_anatop
->
tempsense1_set
);
start
=
get_timer
(
0
);
/* Wait max 100ms */
do
{
if
(
soc_rev
()
>=
CHIP_REV_1_1
)
{
while
((
readl
(
&
ccm_anatop
->
tempsense1
)
&
TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK
)
==
0
)
;
reg
=
readl
(
&
ccm_anatop
->
tempsense1
);
tmp
=
(
reg
&
TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK
)
>>
TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT
;
}
else
{
/*
* Since we can not rely on finish bit, use 1ms delay to get
* temperature. From RM, 17us is enough to get data, but
* to gurantee to get the data, delay 100ms here.
* Since we can not rely on finish bit, use 10ms
* delay to get temperature. From RM, 17us is
* enough to get data, but to gurantee to get
* the data, delay 10ms here.
*/
udelay
(
10000
);
reg
=
readl
(
&
ccm_anatop
->
tempsense1
);
tmp
=
(
reg
&
TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK
)
>>
TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT
;
}
while
(
get_timer
(
0
)
<
(
start
+
100
));
}
writel
(
TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK
,
&
ccm_anatop
->
tempsense1_clr
);
...
...
drivers/watchdog/imx_watchdog.c
浏览文件 @
b685c734
...
...
@@ -43,7 +43,7 @@ void reset_cpu(ulong addr)
{
struct
watchdog_regs
*
wdog
=
(
struct
watchdog_regs
*
)
WDOG1_BASE_ADDR
;
clrsetbits_le16
(
&
wdog
->
wcr
,
0
,
WCR_WDE
);
clrsetbits_le16
(
&
wdog
->
wcr
,
WCR_WT_MSK
,
WCR_WDE
);
writew
(
0x5555
,
&
wdog
->
wsr
);
writew
(
0xaaaa
,
&
wdog
->
wsr
);
/* load minimum 1/2 second timeout */
...
...
include/configs/mx6ul_14x14_evk.h
浏览文件 @
b685c734
...
...
@@ -241,6 +241,7 @@
#define CONFIG_IMX_THERMAL
#ifndef CONFIG_SPL_BUILD
#define CONFIG_VIDEO
#ifdef CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
...
...
@@ -257,5 +258,6 @@
#define CONFIG_VIDEO_BMP_LOGO
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#endif
#endif
#endif
include/fsl_wdog.h
浏览文件 @
b685c734
...
...
@@ -16,3 +16,4 @@ struct watchdog_regs {
#define WCR_WDT 0x08
#define WCR_SRS 0x10
#define SET_WCR_WT(x) (x << 8)
#define WCR_WT_MSK SET_WCR_WT(0xFF)
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