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体验新版 GitCode,发现更多精彩内容 >>
提交
b38eaec5
编写于
5月 03, 2016
作者:
R
Robert P. J. Day
提交者:
Tom Rini
5月 03, 2016
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
include/configs: Numerous typo fixes: "controler" -> "controller".
Signed-off-by:
N
Robert P. J. Day
<
rpjday@crashcourse.ca
>
上级
700877a6
变更
34
隐藏空白更改
内联
并排
Showing
34 changed file
with
82 addition
and
82 deletion
+82
-82
include/configs/B4860QDS.h
include/configs/B4860QDS.h
+1
-1
include/configs/BSC9132QDS.h
include/configs/BSC9132QDS.h
+1
-1
include/configs/C29XPCIE.h
include/configs/C29XPCIE.h
+1
-1
include/configs/MPC8536DS.h
include/configs/MPC8536DS.h
+3
-3
include/configs/MPC8544DS.h
include/configs/MPC8544DS.h
+3
-3
include/configs/MPC8548CDS.h
include/configs/MPC8548CDS.h
+1
-1
include/configs/MPC8572DS.h
include/configs/MPC8572DS.h
+3
-3
include/configs/MPC8610HPCD.h
include/configs/MPC8610HPCD.h
+1
-1
include/configs/MPC8641HPCN.h
include/configs/MPC8641HPCN.h
+2
-2
include/configs/P1010RDB.h
include/configs/P1010RDB.h
+2
-2
include/configs/P1022DS.h
include/configs/P1022DS.h
+3
-3
include/configs/P1023RDB.h
include/configs/P1023RDB.h
+3
-3
include/configs/P2041RDB.h
include/configs/P2041RDB.h
+3
-3
include/configs/T102xQDS.h
include/configs/T102xQDS.h
+3
-3
include/configs/T102xRDB.h
include/configs/T102xRDB.h
+4
-4
include/configs/T1040QDS.h
include/configs/T1040QDS.h
+4
-4
include/configs/T104xRDB.h
include/configs/T104xRDB.h
+4
-4
include/configs/T208xQDS.h
include/configs/T208xQDS.h
+4
-4
include/configs/T208xRDB.h
include/configs/T208xRDB.h
+4
-4
include/configs/T4240RDB.h
include/configs/T4240RDB.h
+3
-3
include/configs/controlcenterd.h
include/configs/controlcenterd.h
+1
-1
include/configs/corenet_ds.h
include/configs/corenet_ds.h
+2
-2
include/configs/cyrus.h
include/configs/cyrus.h
+2
-2
include/configs/km/kmp204x-common.h
include/configs/km/kmp204x-common.h
+2
-2
include/configs/ls1021aqds.h
include/configs/ls1021aqds.h
+2
-2
include/configs/ls1021atwr.h
include/configs/ls1021atwr.h
+2
-2
include/configs/ls2080a_common.h
include/configs/ls2080a_common.h
+4
-4
include/configs/p1_p2_rdb_pc.h
include/configs/p1_p2_rdb_pc.h
+2
-2
include/configs/p1_twr.h
include/configs/p1_twr.h
+2
-2
include/configs/sbc8641d.h
include/configs/sbc8641d.h
+2
-2
include/configs/t4qds.h
include/configs/t4qds.h
+3
-3
include/configs/xpedite517x.h
include/configs/xpedite517x.h
+2
-2
include/configs/xpedite537x.h
include/configs/xpedite537x.h
+2
-2
include/configs/xpedite550x.h
include/configs/xpedite550x.h
+1
-1
未找到文件。
include/configs/B4860QDS.h
浏览文件 @
b38eaec5
...
...
@@ -83,7 +83,7 @@
#define CONFIG_FSL_IFC
/* Enable IFC Support */
#define CONFIG_FSL_CAAM
/* Enable SEC/CAAM */
#define CONFIG_PCI
/* Enable PCI/PCIE */
#define CONFIG_PCIE1
/* PCIE controler 1 */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 */
#define CONFIG_FSL_PCI_INIT
/* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT
/* enable 64-bit PCI resources */
...
...
include/configs/BSC9132QDS.h
浏览文件 @
b38eaec5
...
...
@@ -85,7 +85,7 @@
#define CONFIG_PCI
/* Enable PCI/PCIE */
#if defined(CONFIG_PCI)
#define CONFIG_PCIE1
/* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 (slot 1) */
#define CONFIG_FSL_PCI_INIT
/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE
/* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET
/* need PCIe reset errata */
...
...
include/configs/C29XPCIE.h
浏览文件 @
b38eaec5
...
...
@@ -92,7 +92,7 @@
#define CONFIG_PCI
/* Enable PCI/PCIE */
#ifdef CONFIG_PCI
#define CONFIG_PCIE1
/* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 (slot 1) */
#define CONFIG_FSL_PCI_INIT
/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_FSL_PCIE_RESET
/* need PCIe reset errata */
...
...
include/configs/MPC8536DS.h
浏览文件 @
b38eaec5
...
...
@@ -51,9 +51,9 @@
#define CONFIG_FSL_ELBC 1
/* Has Enhanced localbus controller */
#define CONFIG_PCI 1
/* Enable PCI/PCIE */
#define CONFIG_PCI1 1
/* Enable PCI controller 1 */
#define CONFIG_PCIE1 1
/* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2 1
/* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3 1
/* PCIE controler 3 (ULI bridge) */
#define CONFIG_PCIE1 1
/* PCIE control
l
er 1 (slot 1) */
#define CONFIG_PCIE2 1
/* PCIE control
l
er 2 (slot 2) */
#define CONFIG_PCIE3 1
/* PCIE control
l
er 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1
/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1
/* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1
/* need PCIe reset errata */
...
...
include/configs/MPC8544DS.h
浏览文件 @
b38eaec5
...
...
@@ -25,9 +25,9 @@
#define CONFIG_PCI 1
/* Enable PCI/PCIE */
#define CONFIG_PCI1 1
/* PCI controller 1 */
#define CONFIG_PCIE1 1
/* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2 1
/* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3 1
/* PCIE controler 3 (ULI bridge) */
#define CONFIG_PCIE1 1
/* PCIE control
l
er 1 (slot 1) */
#define CONFIG_PCIE2 1
/* PCIE control
l
er 2 (slot 2) */
#define CONFIG_PCIE3 1
/* PCIE control
l
er 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1
/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1
/* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1
/* need PCIe reset errata */
...
...
include/configs/MPC8548CDS.h
浏览文件 @
b38eaec5
...
...
@@ -34,7 +34,7 @@
#define CONFIG_PCI
/* enable any pci type devices */
#define CONFIG_PCI1
/* PCI controller 1 */
#define CONFIG_PCIE1
/* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 (slot 1) */
#undef CONFIG_PCI2
#define CONFIG_FSL_PCI_INIT 1
/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1
/* indirect PCI bridge support */
...
...
include/configs/MPC8572DS.h
浏览文件 @
b38eaec5
...
...
@@ -40,9 +40,9 @@
#define CONFIG_FSL_ELBC 1
/* Has Enhanced localbus controller */
#define CONFIG_PCI 1
/* Enable PCI/PCIE */
#define CONFIG_PCIE1 1
/* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2 1
/* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3 1
/* PCIE controler 3 (ULI bridge) */
#define CONFIG_PCIE1 1
/* PCIE control
l
er 1 (slot 1) */
#define CONFIG_PCIE2 1
/* PCIE control
l
er 2 (slot 2) */
#define CONFIG_PCIE3 1
/* PCIE control
l
er 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1
/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1
/* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1
/* need PCIe reset errata */
...
...
include/configs/MPC8610HPCD.h
浏览文件 @
b38eaec5
...
...
@@ -45,7 +45,7 @@
#define CONFIG_SYS_SCRATCH_VA 0xc0000000
#define CONFIG_PCI 1
/* Enable PCI/PCIE*/
#define CONFIG_PCI1 1
/* PCI controler 1 */
#define CONFIG_PCI1 1
/* PCI control
l
er 1 */
#define CONFIG_PCIE1 1
/* PCIe 1 connected to ULI bridge */
#define CONFIG_PCIE2 1
/* PCIe 2 connected to slot */
#define CONFIG_FSL_PCI_INIT 1
/* Use common FSL init code */
...
...
include/configs/MPC8641HPCN.h
浏览文件 @
b38eaec5
...
...
@@ -46,8 +46,8 @@
#define CONFIG_SRIO1
/* SRIO port 1 */
#define CONFIG_PCI 1
/* Enable PCI/PCIE */
#define CONFIG_PCIE1 1
/* PCIE controler 1 (ULI bridge) */
#define CONFIG_PCIE2 1
/* PCIE controler 2 (slot) */
#define CONFIG_PCIE1 1
/* PCIE control
l
er 1 (ULI bridge) */
#define CONFIG_PCIE2 1
/* PCIE control
l
er 2 (slot) */
#define CONFIG_FSL_PCI_INIT 1
/* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT 1
/* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1
/* Use common FSL law init code */
...
...
include/configs/P1010RDB.h
浏览文件 @
b38eaec5
...
...
@@ -176,8 +176,8 @@
#define CONFIG_PCI
/* Enable PCI/PCIE */
#if defined(CONFIG_PCI)
#define CONFIG_PCIE1
/* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2
/* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 (slot 1) */
#define CONFIG_PCIE2
/* PCIE control
l
er 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT
/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE
/* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET
/* need PCIe reset errata */
...
...
include/configs/P1022DS.h
浏览文件 @
b38eaec5
...
...
@@ -134,9 +134,9 @@
#define CONFIG_FSL_ELBC
/* Has Enhanced localbus controller */
#define CONFIG_PCI
/* Enable PCI/PCIE */
#define CONFIG_PCIE1
/* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2
/* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3
/* PCIE controler 3 (ULI bridge) */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 (slot 1) */
#define CONFIG_PCIE2
/* PCIE control
l
er 2 (slot 2) */
#define CONFIG_PCIE3
/* PCIE control
l
er 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT
/* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET
/* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT
/* enable 64-bit PCI resources */
...
...
include/configs/P1023RDB.h
浏览文件 @
b38eaec5
...
...
@@ -33,9 +33,9 @@
#define CONFIG_FSL_ELBC
/* Has Enhanced localbus controller */
#define CONFIG_PCI
/* Enable PCI/PCIE */
#define CONFIG_PCI_INDIRECT_BRIDGE
/* indirect PCI bridge support */
#define CONFIG_PCIE1
/* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2
/* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3
/* PCIE controler 3 (slot 3) */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 (slot 1) */
#define CONFIG_PCIE2
/* PCIE control
l
er 2 (slot 2) */
#define CONFIG_PCIE3
/* PCIE control
l
er 3 (slot 3) */
#define CONFIG_FSL_PCI_INIT
/* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET
/* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT
/* enable 64-bit PCI resources */
...
...
include/configs/P2041RDB.h
浏览文件 @
b38eaec5
...
...
@@ -52,9 +52,9 @@
#define CONFIG_FSL_ELBC
/* Has Enhanced localbus controller */
#define CONFIG_FSL_CAAM
/* Enable SEC/CAAM */
#define CONFIG_PCI
/* Enable PCI/PCIE */
#define CONFIG_PCIE1
/* PCIE controler 1 */
#define CONFIG_PCIE2
/* PCIE controler 2 */
#define CONFIG_PCIE3
/* PCIE controler 3 */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 */
#define CONFIG_PCIE2
/* PCIE control
l
er 2 */
#define CONFIG_PCIE3
/* PCIE control
l
er 3 */
#define CONFIG_FSL_PCI_INIT
/* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT
/* enable 64-bit PCI resources */
...
...
include/configs/T102xQDS.h
浏览文件 @
b38eaec5
...
...
@@ -577,9 +577,9 @@ unsigned long get_board_ddr_clk(void);
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CONFIG_PCI
/* Enable PCI/PCIE */
#define CONFIG_PCIE1
/* PCIE controler 1 */
#define CONFIG_PCIE2
/* PCIE controler 2 */
#define CONFIG_PCIE3
/* PCIE controler 3 */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 */
#define CONFIG_PCIE2
/* PCIE control
l
er 2 */
#define CONFIG_PCIE3
/* PCIE control
l
er 3 */
#define CONFIG_FSL_PCI_INIT
/* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT
/* enable 64-bit PCI resources */
#define CONFIG_PCI_INDIRECT_BRIDGE
...
...
include/configs/T102xRDB.h
浏览文件 @
b38eaec5
...
...
@@ -563,11 +563,11 @@ unsigned long get_board_ddr_clk(void);
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CONFIG_PCI
/* Enable PCI/PCIE */
#define CONFIG_PCIE1
/* PCIE controler 1 */
#define CONFIG_PCIE2
/* PCIE controler 2 */
#define CONFIG_PCIE3
/* PCIE controler 3 */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 */
#define CONFIG_PCIE2
/* PCIE control
l
er 2 */
#define CONFIG_PCIE3
/* PCIE control
l
er 3 */
#ifdef CONFIG_PPC_T1040
#define CONFIG_PCIE4
/* PCIE controler 4 */
#define CONFIG_PCIE4
/* PCIE control
l
er 4 */
#endif
#define CONFIG_FSL_PCI_INIT
/* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT
/* enable 64-bit PCI resources */
...
...
include/configs/T1040QDS.h
浏览文件 @
b38eaec5
...
...
@@ -65,10 +65,10 @@
#define CONFIG_FSL_CAAM
/* Enable SEC/CAAM */
#define CONFIG_PCI
/* Enable PCI/PCIE */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE1
/* PCIE controler 1 */
#define CONFIG_PCIE2
/* PCIE controler 2 */
#define CONFIG_PCIE3
/* PCIE controler 3 */
#define CONFIG_PCIE4
/* PCIE controler 4 */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 */
#define CONFIG_PCIE2
/* PCIE control
l
er 2 */
#define CONFIG_PCIE3
/* PCIE control
l
er 3 */
#define CONFIG_PCIE4
/* PCIE control
l
er 4 */
#define CONFIG_FSL_PCI_INIT
/* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT
/* enable 64-bit PCI resources */
...
...
include/configs/T104xRDB.h
浏览文件 @
b38eaec5
...
...
@@ -130,10 +130,10 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
#define CONFIG_FSL_CAAM
/* Enable SEC/CAAM */
#define CONFIG_PCI
/* Enable PCI/PCIE */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE1
/* PCIE controler 1 */
#define CONFIG_PCIE2
/* PCIE controler 2 */
#define CONFIG_PCIE3
/* PCIE controler 3 */
#define CONFIG_PCIE4
/* PCIE controler 4 */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 */
#define CONFIG_PCIE2
/* PCIE control
l
er 2 */
#define CONFIG_PCIE3
/* PCIE control
l
er 3 */
#define CONFIG_PCIE4
/* PCIE control
l
er 4 */
#define CONFIG_FSL_PCI_INIT
/* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT
/* enable 64-bit PCI resources */
...
...
include/configs/T208xQDS.h
浏览文件 @
b38eaec5
...
...
@@ -550,10 +550,10 @@ unsigned long get_board_ddr_clk(void);
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CONFIG_PCI
/* Enable PCI/PCIE */
#define CONFIG_PCIE1
/* PCIE controler 1 */
#define CONFIG_PCIE2
/* PCIE controler 2 */
#define CONFIG_PCIE3
/* PCIE controler 3 */
#define CONFIG_PCIE4
/* PCIE controler 4 */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 */
#define CONFIG_PCIE2
/* PCIE control
l
er 2 */
#define CONFIG_PCIE3
/* PCIE control
l
er 3 */
#define CONFIG_PCIE4
/* PCIE control
l
er 4 */
#define CONFIG_FSL_PCIE_RESET
#define CONFIG_FSL_PCI_INIT
/* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT
/* enable 64-bit PCI resources */
...
...
include/configs/T208xRDB.h
浏览文件 @
b38eaec5
...
...
@@ -500,10 +500,10 @@ unsigned long get_board_ddr_clk(void);
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CONFIG_PCI
/* Enable PCI/PCIE */
#define CONFIG_PCIE1
/* PCIE controler 1 */
#define CONFIG_PCIE2
/* PCIE controler 2 */
#define CONFIG_PCIE3
/* PCIE controler 3 */
#define CONFIG_PCIE4
/* PCIE controler 4 */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 */
#define CONFIG_PCIE2
/* PCIE control
l
er 2 */
#define CONFIG_PCIE3
/* PCIE control
l
er 3 */
#define CONFIG_PCIE4
/* PCIE control
l
er 4 */
#define CONFIG_FSL_PCI_INIT
/* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT
/* enable 64-bit PCI resources */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
...
...
include/configs/T4240RDB.h
浏览文件 @
b38eaec5
...
...
@@ -92,9 +92,9 @@
#define CONFIG_FSL_IFC
/* Enable IFC Support */
#define CONFIG_FSL_CAAM
/* Enable SEC/CAAM */
#define CONFIG_PCI
/* Enable PCI/PCIE */
#define CONFIG_PCIE1
/* PCIE controler 1 */
#define CONFIG_PCIE2
/* PCIE controler 2 */
#define CONFIG_PCIE3
/* PCIE controler 3 */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 */
#define CONFIG_PCIE2
/* PCIE control
l
er 2 */
#define CONFIG_PCIE3
/* PCIE control
l
er 3 */
#define CONFIG_FSL_PCI_INIT
/* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT
/* enable 64-bit PCI resources */
...
...
include/configs/controlcenterd.h
浏览文件 @
b38eaec5
...
...
@@ -245,7 +245,7 @@
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CONFIG_PCI
/* Enable PCI/PCIE */
#define CONFIG_PCIE1
/* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 (slot 1) */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_PNP
/* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW
/* show pci devices on startup */
...
...
include/configs/corenet_ds.h
浏览文件 @
b38eaec5
...
...
@@ -67,8 +67,8 @@
#define CONFIG_FSL_ELBC
/* Has Enhanced localbus controller */
#define CONFIG_FSL_CAAM
/* Enable SEC/CAAM */
#define CONFIG_PCI
/* Enable PCI/PCIE */
#define CONFIG_PCIE1
/* PCIE controler 1 */
#define CONFIG_PCIE2
/* PCIE controler 2 */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 */
#define CONFIG_PCIE2
/* PCIE control
l
er 2 */
#define CONFIG_FSL_PCI_INIT
/* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT
/* enable 64-bit PCI resources */
...
...
include/configs/cyrus.h
浏览文件 @
b38eaec5
...
...
@@ -59,8 +59,8 @@
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_ELBC
/* Has Enhanced localbus controller */
#define CONFIG_PCI
/* Enable PCI/PCIE */
#define CONFIG_PCIE1
/* PCIE controler 1 */
#define CONFIG_PCIE2
/* PCIE controler 2 */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 */
#define CONFIG_PCIE2
/* PCIE control
l
er 2 */
#define CONFIG_FSL_PCI_INIT
/* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT
/* enable 64-bit PCI resources */
...
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include/configs/km/kmp204x-common.h
浏览文件 @
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...
...
@@ -45,8 +45,8 @@
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_ELBC
/* Has Enhanced localbus controller */
#define CONFIG_PCI
/* Enable PCI/PCIE */
#define CONFIG_PCIE1
/* PCIE controler 1 */
#define CONFIG_PCIE3
/* PCIE controler 3 */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 */
#define CONFIG_PCIE3
/* PCIE control
l
er 3 */
#define CONFIG_FSL_PCI_INIT
/* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT
/* enable 64-bit PCI resources */
...
...
include/configs/ls1021aqds.h
浏览文件 @
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...
@@ -528,8 +528,8 @@ unsigned long get_board_ddr_clk(void);
/* PCIe */
#define CONFIG_PCI
/* Enable PCI/PCIE */
#define CONFIG_PCIE1
/* PCIE controler 1 */
#define CONFIG_PCIE2
/* PCIE controler 2 */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 */
#define CONFIG_PCIE2
/* PCIE control
l
er 2 */
#define CONFIG_PCIE_LAYERSCAPE
/* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
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include/configs/ls1021atwr.h
浏览文件 @
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...
@@ -377,8 +377,8 @@
/* PCIe */
#define CONFIG_PCI
/* Enable PCI/PCIE */
#define CONFIG_PCIE1
/* PCIE controler 1 */
#define CONFIG_PCIE2
/* PCIE controler 2 */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 */
#define CONFIG_PCIE2
/* PCIE control
l
er 2 */
#define CONFIG_PCIE_LAYERSCAPE
/* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
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include/configs/ls2080a_common.h
浏览文件 @
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...
@@ -185,10 +185,10 @@ unsigned long long get_qixis_addr(void);
#endif
/* PCIe */
#define CONFIG_PCIE1
/* PCIE controler 1 */
#define CONFIG_PCIE2
/* PCIE controler 2 */
#define CONFIG_PCIE3
/* PCIE controler 3 */
#define CONFIG_PCIE4
/* PCIE controler 4 */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 */
#define CONFIG_PCIE2
/* PCIE control
l
er 2 */
#define CONFIG_PCIE3
/* PCIE control
l
er 3 */
#define CONFIG_PCIE4
/* PCIE control
l
er 4 */
#define CONFIG_PCIE_LAYERSCAPE
/* Use common FSL Layerscape PCIe code */
#ifdef CONFIG_LS2080A
#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
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...
include/configs/p1_p2_rdb_pc.h
浏览文件 @
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...
@@ -306,8 +306,8 @@
#define CONFIG_FSL_ELBC
#define CONFIG_PCI
#define CONFIG_PCIE1
/* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2
/* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 (slot 1) */
#define CONFIG_PCIE2
/* PCIE control
l
er 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT
/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE
/* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET
/* need PCIe reset errata */
...
...
include/configs/p1_twr.h
浏览文件 @
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...
...
@@ -48,8 +48,8 @@
#define CONFIG_FSL_ELBC
#define CONFIG_PCI
#define CONFIG_PCIE1
/* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2
/* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 (slot 1) */
#define CONFIG_PCIE2
/* PCIE control
l
er 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT
/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE
/* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET
/* need PCIe reset errata */
...
...
include/configs/sbc8641d.h
浏览文件 @
b38eaec5
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...
@@ -44,8 +44,8 @@
#define CONFIG_SRIO1
/* SRIO port 1 */
#define CONFIG_PCI 1
/* Enable PCIE */
#define CONFIG_PCIE1 1
/* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2 1
/* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE1 1
/* PCIE control
l
er 1 (slot 1) */
#define CONFIG_PCIE2 1
/* PCIE control
l
er 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT 1
/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1
/* indirect PCI bridge support */
#define CONFIG_FSL_LAW 1
/* Use common FSL init code */
...
...
include/configs/t4qds.h
浏览文件 @
b38eaec5
...
...
@@ -32,9 +32,9 @@
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_IFC
/* Enable IFC Support */
#define CONFIG_PCI
/* Enable PCI/PCIE */
#define CONFIG_PCIE1
/* PCIE controler 1 */
#define CONFIG_PCIE2
/* PCIE controler 2 */
#define CONFIG_PCIE3
/* PCIE controler 3 */
#define CONFIG_PCIE1
/* PCIE control
l
er 1 */
#define CONFIG_PCIE2
/* PCIE control
l
er 2 */
#define CONFIG_PCIE3
/* PCIE control
l
er 3 */
#define CONFIG_FSL_PCI_INIT
/* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT
/* enable 64-bit PCI resources */
...
...
include/configs/xpedite517x.h
浏览文件 @
b38eaec5
...
...
@@ -30,8 +30,8 @@
#define CONFIG_PCI 1
/* Enable PCI/PCIE */
#define CONFIG_PCI_PNP 1
/* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1
/* show pci devices on startup */
#define CONFIG_PCIE1 1
/* PCIE controler 1 */
#define CONFIG_PCIE2 1
/* PCIE controler 2 */
#define CONFIG_PCIE1 1
/* PCIE control
l
er 1 */
#define CONFIG_PCIE2 1
/* PCIE control
l
er 2 */
#define CONFIG_FSL_PCI_INIT 1
/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1
/* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1
/* enable 64-bit PCI resources */
...
...
include/configs/xpedite537x.h
浏览文件 @
b38eaec5
...
...
@@ -30,8 +30,8 @@
#define CONFIG_PCI 1
/* Enable PCI/PCIE */
#define CONFIG_PCI_PNP 1
/* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1
/* show pci devices on startup */
#define CONFIG_PCIE1 1
/* PCIE controler 1 */
#define CONFIG_PCIE2 1
/* PCIE controler 2 */
#define CONFIG_PCIE1 1
/* PCIE control
l
er 1 */
#define CONFIG_PCIE2 1
/* PCIE control
l
er 2 */
#define CONFIG_FSL_PCI_INIT 1
/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1
/* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1
/* enable 64-bit PCI resources */
...
...
include/configs/xpedite550x.h
浏览文件 @
b38eaec5
...
...
@@ -31,7 +31,7 @@
#define CONFIG_PCI 1
/* Enable PCI/PCIE */
#define CONFIG_PCI_PNP 1
/* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1
/* show pci devices on startup */
#define CONFIG_PCIE1 1
/* PCIE controler 1 (PEX8112 or XMC) */
#define CONFIG_PCIE1 1
/* PCIE control
l
er 1 (PEX8112 or XMC) */
#define CONFIG_FSL_PCI_INIT 1
/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1
/* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1
/* enable 64-bit PCI resources */
...
...
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